mt8135-resets.h revision 295436
1139804Simp/* 21541Srgrimes * Copyright (c) 2014 MediaTek Inc. 31541Srgrimes * Author: Flora Fu, MediaTek 41541Srgrimes * 51541Srgrimes * This program is free software; you can redistribute it and/or modify 61541Srgrimes * it under the terms of the GNU General Public License version 2 as 71541Srgrimes * published by the Free Software Foundation. 81541Srgrimes * 91541Srgrimes * This program is distributed in the hope that it will be useful, 101541Srgrimes * but WITHOUT ANY WARRANTY; without even the implied warranty of 111541Srgrimes * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 121541Srgrimes * GNU General Public License for more details. 131541Srgrimes */ 141541Srgrimes 151541Srgrimes#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135 161541Srgrimes#define _DT_BINDINGS_RESET_CONTROLLER_MT8135 171541Srgrimes 181541Srgrimes/* INFRACFG resets */ 191541Srgrimes#define MT8135_INFRA_EMI_REG_RST 0 201541Srgrimes#define MT8135_INFRA_DRAMC0_A0_RST 1 211541Srgrimes#define MT8135_INFRA_CCIF0_RST 2 221541Srgrimes#define MT8135_INFRA_APCIRQ_EINT_RST 3 231541Srgrimes#define MT8135_INFRA_APXGPT_RST 4 241541Srgrimes#define MT8135_INFRA_SCPSYS_RST 5 251541Srgrimes#define MT8135_INFRA_CCIF1_RST 6 261541Srgrimes#define MT8135_INFRA_PMIC_WRAP_RST 7 271541Srgrimes#define MT8135_INFRA_KP_RST 8 281541Srgrimes#define MT8135_INFRA_EMI_RST 32 2922521Sdyson#define MT8135_INFRA_DRAMC0_RST 34 3050477Speter#define MT8135_INFRA_SMI_RST 35 311541Srgrimes#define MT8135_INFRA_M4U_RST 36 3222521Sdyson 3322521Sdyson/* PERICFG resets */ 34159082Sdds#define MT8135_PERI_UART0_SW_RST 0 35159082Sdds#define MT8135_PERI_UART1_SW_RST 1 36159082Sdds#define MT8135_PERI_UART2_SW_RST 2 37159082Sdds#define MT8135_PERI_UART3_SW_RST 3 38159082Sdds#define MT8135_PERI_IRDA_SW_RST 4 39159082Sdds#define MT8135_PERI_PTP_SW_RST 5 4022521Sdyson#define MT8135_PERI_AP_HIF_SW_RST 6 4122521Sdyson#define MT8135_PERI_GPCU_SW_RST 7 4254444Seivind#define MT8135_PERI_MD_HIF_SW_RST 8 4354444Seivind#define MT8135_PERI_NLI_SW_RST 9 4454444Seivind#define MT8135_PERI_AUXADC_SW_RST 10 4554444Seivind#define MT8135_PERI_DMA_SW_RST 11 4654444Seivind#define MT8135_PERI_NFI_SW_RST 14 4745058Seivind#define MT8135_PERI_PWM_SW_RST 15 4822521Sdyson#define MT8135_PERI_THERM_SW_RST 16 4922521Sdyson#define MT8135_PERI_MSDC0_SW_RST 17 5022521Sdyson#define MT8135_PERI_MSDC1_SW_RST 18 5122521Sdyson#define MT8135_PERI_MSDC2_SW_RST 19 52116615Sse#define MT8135_PERI_MSDC3_SW_RST 20 53116615Sse#define MT8135_PERI_I2C0_SW_RST 22 54116615Sse#define MT8135_PERI_I2C1_SW_RST 23 55159082Sdds#define MT8135_PERI_I2C2_SW_RST 24 56159082Sdds#define MT8135_PERI_I2C3_SW_RST 25 57159082Sdds#define MT8135_PERI_I2C4_SW_RST 26 58116615Sse#define MT8135_PERI_I2C5_SW_RST 27 59116615Sse#define MT8135_PERI_I2C6_SW_RST 28 60116615Sse#define MT8135_PERI_USB_SW_RST 29 6122521Sdyson#define MT8135_PERI_SPI1_SW_RST 33 6251679Seivind#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34 6351679Seivind 6451679Seivind#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */ 6551679Seivind