altr,rst-mgr-a10.h revision 295011
1295011Sandrew/* 2295011Sandrew * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 3295011Sandrew * 4295011Sandrew * This software is licensed under the terms of the GNU General Public 5295011Sandrew * License version 2, as published by the Free Software Foundation, and 6295011Sandrew * may be copied, distributed, and modified under those terms. 7295011Sandrew * 8295011Sandrew * This program is distributed in the hope that it will be useful, 9295011Sandrew * but WITHOUT ANY WARRANTY; without even the implied warranty of 10295011Sandrew * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11295011Sandrew * GNU General Public License for more details. 12295011Sandrew */ 13295011Sandrew 14295011Sandrew#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 15295011Sandrew#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 16295011Sandrew 17295011Sandrew/* MPUMODRST */ 18295011Sandrew#define CPU0_RESET 0 19295011Sandrew#define CPU1_RESET 1 20295011Sandrew#define WDS_RESET 2 21295011Sandrew#define SCUPER_RESET 3 22295011Sandrew 23295011Sandrew/* PER0MODRST */ 24295011Sandrew#define EMAC0_RESET 32 25295011Sandrew#define EMAC1_RESET 33 26295011Sandrew#define EMAC2_RESET 34 27295011Sandrew#define USB0_RESET 35 28295011Sandrew#define USB1_RESET 36 29295011Sandrew#define NAND_RESET 37 30295011Sandrew#define QSPI_RESET 38 31295011Sandrew#define SDMMC_RESET 39 32295011Sandrew#define EMAC0_OCP_RESET 40 33295011Sandrew#define EMAC1_OCP_RESET 41 34295011Sandrew#define EMAC2_OCP_RESET 42 35295011Sandrew#define USB0_OCP_RESET 43 36295011Sandrew#define USB1_OCP_RESET 44 37295011Sandrew#define NAND_OCP_RESET 45 38295011Sandrew#define QSPI_OCP_RESET 46 39295011Sandrew#define SDMMC_OCP_RESET 47 40295011Sandrew#define DMA_RESET 48 41295011Sandrew#define SPIM0_RESET 49 42295011Sandrew#define SPIM1_RESET 50 43295011Sandrew#define SPIS0_RESET 51 44295011Sandrew#define SPIS1_RESET 52 45295011Sandrew#define DMA_OCP_RESET 53 46295011Sandrew#define EMAC_PTP_RESET 54 47295011Sandrew/* 55 is empty*/ 48295011Sandrew#define DMAIF0_RESET 56 49295011Sandrew#define DMAIF1_RESET 57 50295011Sandrew#define DMAIF2_RESET 58 51295011Sandrew#define DMAIF3_RESET 59 52295011Sandrew#define DMAIF4_RESET 60 53295011Sandrew#define DMAIF5_RESET 61 54295011Sandrew#define DMAIF6_RESET 62 55295011Sandrew#define DMAIF7_RESET 63 56295011Sandrew 57295011Sandrew/* PER1MODRST */ 58295011Sandrew#define L4WD0_RESET 64 59295011Sandrew#define L4WD1_RESET 65 60295011Sandrew#define L4SYSTIMER0_RESET 66 61295011Sandrew#define L4SYSTIMER1_RESET 67 62295011Sandrew#define SPTIMER0_RESET 68 63295011Sandrew#define SPTIMER1_RESET 69 64295011Sandrew/* 70-71 is reserved */ 65295011Sandrew#define I2C0_RESET 72 66295011Sandrew#define I2C1_RESET 73 67295011Sandrew#define I2C2_RESET 74 68295011Sandrew#define I2C3_RESET 75 69295011Sandrew#define I2C4_RESET 76 70295011Sandrew/* 77-79 is reserved */ 71295011Sandrew#define UART0_RESET 80 72295011Sandrew#define UART1_RESET 81 73295011Sandrew/* 82-87 is reserved */ 74295011Sandrew#define GPIO0_RESET 88 75295011Sandrew#define GPIO1_RESET 89 76295011Sandrew#define GPIO2_RESET 90 77295011Sandrew 78295011Sandrew/* BRGMODRST */ 79295011Sandrew#define HPS2FPGA_RESET 96 80295011Sandrew#define LWHPS2FPGA_RESET 97 81295011Sandrew#define FPGA2HPS_RESET 98 82295011Sandrew#define F2SSDRAM0_RESET 99 83295011Sandrew#define F2SSDRAM1_RESET 100 84295011Sandrew#define F2SSDRAM2_RESET 101 85295011Sandrew#define DDRSCH_RESET 102 86295011Sandrew 87295011Sandrew/* SYSMODRST*/ 88295011Sandrew#define ROM_RESET 128 89295011Sandrew#define OCRAM_RESET 129 90295011Sandrew/* 130 is reserved */ 91295011Sandrew#define FPGAMGR_RESET 131 92295011Sandrew#define S2F_RESET 132 93295011Sandrew#define SYSDBG_RESET 133 94295011Sandrew#define OCRAM_OCP_RESET 134 95295011Sandrew 96295011Sandrew/* COLDMODRST */ 97295011Sandrew#define CLKMGRCOLD_RESET 160 98295011Sandrew/* 161-162 is reserved */ 99295011Sandrew#define S2FCOLD_RESET 163 100295011Sandrew#define TIMESTAMPCOLD_RESET 164 101295011Sandrew#define TAPCOLD_RESET 165 102295011Sandrew#define HMCCOLD_RESET 166 103295011Sandrew#define IOMGRCOLD_RESET 167 104295011Sandrew 105295011Sandrew/* NRSTMODRST */ 106295011Sandrew#define NRSTPINOE_RESET 192 107295011Sandrew 108295011Sandrew/* DBGMODRST */ 109295011Sandrew#define DBG_RESET 224 110295011Sandrew#endif 111