1262569Simp/* 2262569Simp * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com> 3262569Simp * 4262569Simp * This program is free software; you can redistribute it and/or modify 5262569Simp * it under the terms of the GNU General Public License version 2 as 6262569Simp * published by the Free Software Foundation. 7262569Simp * 8262569Simp * Device Tree binding constants for Samsung S3C64xx clock controller. 9262569Simp*/ 10262569Simp 11262569Simp#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H 12262569Simp#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H 13262569Simp 14262569Simp/* 15262569Simp * Let each exported clock get a unique index, which is used on DT-enabled 16262569Simp * platforms to lookup the clock from a clock specifier. These indices are 17262569Simp * therefore considered an ABI and so must not be changed. This implies 18262569Simp * that new clocks should be added either in free spaces between clock groups 19262569Simp * or at the end. 20262569Simp */ 21262569Simp 22262569Simp/* Core clocks. */ 23262569Simp#define CLK27M 1 24262569Simp#define CLK48M 2 25262569Simp#define FOUT_APLL 3 26262569Simp#define FOUT_MPLL 4 27262569Simp#define FOUT_EPLL 5 28262569Simp#define ARMCLK 6 29262569Simp#define HCLKX2 7 30262569Simp#define HCLK 8 31262569Simp#define PCLK 9 32262569Simp 33262569Simp/* HCLK bus clocks. */ 34262569Simp#define HCLK_3DSE 16 35262569Simp#define HCLK_UHOST 17 36262569Simp#define HCLK_SECUR 18 37262569Simp#define HCLK_SDMA1 19 38262569Simp#define HCLK_SDMA0 20 39262569Simp#define HCLK_IROM 21 40262569Simp#define HCLK_DDR1 22 41262569Simp#define HCLK_MEM1 23 42262569Simp#define HCLK_MEM0 24 43262569Simp#define HCLK_USB 25 44262569Simp#define HCLK_HSMMC2 26 45262569Simp#define HCLK_HSMMC1 27 46262569Simp#define HCLK_HSMMC0 28 47262569Simp#define HCLK_MDP 29 48262569Simp#define HCLK_DHOST 30 49262569Simp#define HCLK_IHOST 31 50262569Simp#define HCLK_DMA1 32 51262569Simp#define HCLK_DMA0 33 52262569Simp#define HCLK_JPEG 34 53262569Simp#define HCLK_CAMIF 35 54262569Simp#define HCLK_SCALER 36 55262569Simp#define HCLK_2D 37 56262569Simp#define HCLK_TV 38 57262569Simp#define HCLK_POST0 39 58262569Simp#define HCLK_ROT 40 59262569Simp#define HCLK_LCD 41 60262569Simp#define HCLK_TZIC 42 61262569Simp#define HCLK_INTC 43 62262569Simp#define HCLK_MFC 44 63262569Simp#define HCLK_DDR0 45 64262569Simp 65262569Simp/* PCLK bus clocks. */ 66262569Simp#define PCLK_IIC1 48 67262569Simp#define PCLK_IIS2 49 68262569Simp#define PCLK_SKEY 50 69262569Simp#define PCLK_CHIPID 51 70262569Simp#define PCLK_SPI1 52 71262569Simp#define PCLK_SPI0 53 72262569Simp#define PCLK_HSIRX 54 73262569Simp#define PCLK_HSITX 55 74262569Simp#define PCLK_GPIO 56 75262569Simp#define PCLK_IIC0 57 76262569Simp#define PCLK_IIS1 58 77262569Simp#define PCLK_IIS0 59 78262569Simp#define PCLK_AC97 60 79262569Simp#define PCLK_TZPC 61 80262569Simp#define PCLK_TSADC 62 81262569Simp#define PCLK_KEYPAD 63 82262569Simp#define PCLK_IRDA 64 83262569Simp#define PCLK_PCM1 65 84262569Simp#define PCLK_PCM0 66 85262569Simp#define PCLK_PWM 67 86262569Simp#define PCLK_RTC 68 87262569Simp#define PCLK_WDT 69 88262569Simp#define PCLK_UART3 70 89262569Simp#define PCLK_UART2 71 90262569Simp#define PCLK_UART1 72 91262569Simp#define PCLK_UART0 73 92262569Simp#define PCLK_MFC 74 93262569Simp 94262569Simp/* Special clocks. */ 95262569Simp#define SCLK_UHOST 80 96262569Simp#define SCLK_MMC2_48 81 97262569Simp#define SCLK_MMC1_48 82 98262569Simp#define SCLK_MMC0_48 83 99262569Simp#define SCLK_MMC2 84 100262569Simp#define SCLK_MMC1 85 101262569Simp#define SCLK_MMC0 86 102262569Simp#define SCLK_SPI1_48 87 103262569Simp#define SCLK_SPI0_48 88 104262569Simp#define SCLK_SPI1 89 105262569Simp#define SCLK_SPI0 90 106262569Simp#define SCLK_DAC27 91 107262569Simp#define SCLK_TV27 92 108262569Simp#define SCLK_SCALER27 93 109262569Simp#define SCLK_SCALER 94 110262569Simp#define SCLK_LCD27 95 111262569Simp#define SCLK_LCD 96 112262569Simp#define SCLK_FIMC 97 113262569Simp#define SCLK_POST0_27 98 114262569Simp#define SCLK_AUDIO2 99 115262569Simp#define SCLK_POST0 100 116262569Simp#define SCLK_AUDIO1 101 117262569Simp#define SCLK_AUDIO0 102 118262569Simp#define SCLK_SECUR 103 119262569Simp#define SCLK_IRDA 104 120262569Simp#define SCLK_UART 105 121262569Simp#define SCLK_MFC 106 122262569Simp#define SCLK_CAM 107 123262569Simp#define SCLK_JPEG 108 124262569Simp#define SCLK_ONENAND 109 125262569Simp 126262569Simp/* MEM0 bus clocks - S3C6410-specific. */ 127262569Simp#define MEM0_CFCON 112 128262569Simp#define MEM0_ONENAND1 113 129262569Simp#define MEM0_ONENAND0 114 130262569Simp#define MEM0_NFCON 115 131262569Simp#define MEM0_SROM 116 132262569Simp 133262569Simp/* Muxes. */ 134262569Simp#define MOUT_APLL 128 135262569Simp#define MOUT_MPLL 129 136262569Simp#define MOUT_EPLL 130 137262569Simp#define MOUT_MFC 131 138262569Simp#define MOUT_AUDIO0 132 139262569Simp#define MOUT_AUDIO1 133 140262569Simp#define MOUT_UART 134 141262569Simp#define MOUT_SPI0 135 142262569Simp#define MOUT_SPI1 136 143262569Simp#define MOUT_MMC0 137 144262569Simp#define MOUT_MMC1 138 145262569Simp#define MOUT_MMC2 139 146262569Simp#define MOUT_UHOST 140 147262569Simp#define MOUT_IRDA 141 148262569Simp#define MOUT_LCD 142 149262569Simp#define MOUT_SCALER 143 150262569Simp#define MOUT_DAC27 144 151262569Simp#define MOUT_TV27 145 152262569Simp#define MOUT_AUDIO2 146 153262569Simp 154262569Simp/* Dividers. */ 155262569Simp#define DOUT_MPLL 160 156262569Simp#define DOUT_SECUR 161 157262569Simp#define DOUT_CAM 162 158262569Simp#define DOUT_JPEG 163 159262569Simp#define DOUT_MFC 164 160262569Simp#define DOUT_MMC0 165 161262569Simp#define DOUT_MMC1 166 162262569Simp#define DOUT_MMC2 167 163262569Simp#define DOUT_LCD 168 164262569Simp#define DOUT_SCALER 169 165262569Simp#define DOUT_UHOST 170 166262569Simp#define DOUT_SPI0 171 167262569Simp#define DOUT_SPI1 172 168262569Simp#define DOUT_AUDIO0 173 169262569Simp#define DOUT_AUDIO1 174 170262569Simp#define DOUT_UART 175 171262569Simp#define DOUT_IRDA 176 172262569Simp#define DOUT_FIMC 177 173262569Simp#define DOUT_AUDIO2 178 174262569Simp 175262569Simp/* Total number of clocks. */ 176262569Simp#define NR_CLKS (DOUT_AUDIO2 + 1) 177262569Simp 178262569Simp#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H */ 179