1270866Simp/* 2270866Simp * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 3270866Simp * 4270866Simp * This program is free software; you can redistribute it and/or modify 5270866Simp * it under the terms of the GNU General Public License version 2 as 6270866Simp * published by the Free Software Foundation. 7270866Simp * 8270866Simp * Device Tree binding constants clock controllers of Samsung S3C2443 and later. 9270866Simp */ 10270866Simp 11270866Simp#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H 12270866Simp#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H 13270866Simp 14270866Simp/* 15270866Simp * Let each exported clock get a unique index, which is used on DT-enabled 16270866Simp * platforms to lookup the clock from a clock specifier. These indices are 17270866Simp * therefore considered an ABI and so must not be changed. This implies 18270866Simp * that new clocks should be added either in free spaces between clock groups 19270866Simp * or at the end. 20270866Simp */ 21270866Simp 22270866Simp/* Core clocks. */ 23270866Simp#define MSYSCLK 1 24270866Simp#define ESYSCLK 2 25270866Simp#define ARMDIV 3 26270866Simp#define ARMCLK 4 27270866Simp#define HCLK 5 28270866Simp#define PCLK 6 29270866Simp 30270866Simp/* Special clocks */ 31270866Simp#define SCLK_HSSPI0 16 32270866Simp#define SCLK_FIMD 17 33270866Simp#define SCLK_I2S0 18 34270866Simp#define SCLK_I2S1 19 35270866Simp#define SCLK_HSMMC1 20 36270866Simp#define SCLK_HSMMC_EXT 21 37270866Simp#define SCLK_CAM 22 38270866Simp#define SCLK_UART 23 39270866Simp#define SCLK_USBH 24 40270866Simp 41270866Simp/* Muxes */ 42270866Simp#define MUX_HSSPI0 32 43270866Simp#define MUX_HSSPI1 33 44270866Simp#define MUX_HSMMC0 34 45270866Simp#define MUX_HSMMC1 35 46270866Simp 47270866Simp/* hclk-gates */ 48270866Simp#define HCLK_DMA0 48 49270866Simp#define HCLK_DMA1 49 50270866Simp#define HCLK_DMA2 50 51270866Simp#define HCLK_DMA3 51 52270866Simp#define HCLK_DMA4 52 53270866Simp#define HCLK_DMA5 53 54270866Simp#define HCLK_DMA6 54 55270866Simp#define HCLK_DMA7 55 56270866Simp#define HCLK_CAM 56 57270866Simp#define HCLK_LCD 57 58270866Simp#define HCLK_USBH 58 59270866Simp#define HCLK_USBD 59 60270866Simp#define HCLK_IROM 60 61270866Simp#define HCLK_HSMMC0 61 62270866Simp#define HCLK_HSMMC1 62 63270866Simp#define HCLK_CFC 63 64270866Simp#define HCLK_SSMC 64 65270866Simp#define HCLK_DRAM 65 66270866Simp#define HCLK_2D 66 67270866Simp 68270866Simp/* pclk-gates */ 69270866Simp#define PCLK_UART0 72 70270866Simp#define PCLK_UART1 73 71270866Simp#define PCLK_UART2 74 72270866Simp#define PCLK_UART3 75 73270866Simp#define PCLK_I2C0 76 74270866Simp#define PCLK_SDI 77 75270866Simp#define PCLK_SPI0 78 76270866Simp#define PCLK_ADC 79 77270866Simp#define PCLK_AC97 80 78270866Simp#define PCLK_I2S0 81 79270866Simp#define PCLK_PWM 82 80270866Simp#define PCLK_WDT 83 81270866Simp#define PCLK_RTC 84 82270866Simp#define PCLK_GPIO 85 83270866Simp#define PCLK_SPI1 86 84270866Simp#define PCLK_CHIPID 87 85270866Simp#define PCLK_I2C1 88 86270866Simp#define PCLK_I2S1 89 87270866Simp#define PCLK_PCM 90 88270866Simp 89270866Simp/* Total number of clocks. */ 90270866Simp#define NR_CLKS (PCLK_PCM + 1) 91270866Simp 92270866Simp#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ 93