1270866Simp/* 2270866Simp * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 3270866Simp * 4270866Simp * This program is free software; you can redistribute it and/or modify 5270866Simp * it under the terms of the GNU General Public License version 2 as 6270866Simp * published by the Free Software Foundation. 7270866Simp * 8270866Simp * Device Tree binding constants clock controllers of Samsung S3C2412. 9270866Simp */ 10270866Simp 11270866Simp#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H 12270866Simp#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H 13270866Simp 14270866Simp/* 15270866Simp * Let each exported clock get a unique index, which is used on DT-enabled 16270866Simp * platforms to lookup the clock from a clock specifier. These indices are 17270866Simp * therefore considered an ABI and so must not be changed. This implies 18270866Simp * that new clocks should be added either in free spaces between clock groups 19270866Simp * or at the end. 20270866Simp */ 21270866Simp 22270866Simp/* Core clocks. */ 23270866Simp 24270866Simp/* id 1 is reserved */ 25270866Simp#define MPLL 2 26270866Simp#define UPLL 3 27270866Simp#define MDIVCLK 4 28270866Simp#define MSYSCLK 5 29270866Simp#define USYSCLK 6 30270866Simp#define HCLK 7 31270866Simp#define PCLK 8 32270866Simp#define ARMDIV 9 33270866Simp#define ARMCLK 10 34270866Simp 35270866Simp 36270866Simp/* Special clocks */ 37270866Simp#define SCLK_CAM 16 38270866Simp#define SCLK_UART 17 39270866Simp#define SCLK_I2S 18 40270866Simp#define SCLK_USBD 19 41270866Simp#define SCLK_USBH 20 42270866Simp 43270866Simp/* pclk-gates */ 44270866Simp#define PCLK_WDT 32 45270866Simp#define PCLK_SPI 33 46270866Simp#define PCLK_I2S 34 47270866Simp#define PCLK_I2C 35 48270866Simp#define PCLK_ADC 36 49270866Simp#define PCLK_RTC 37 50270866Simp#define PCLK_GPIO 38 51270866Simp#define PCLK_UART2 39 52270866Simp#define PCLK_UART1 40 53270866Simp#define PCLK_UART0 41 54270866Simp#define PCLK_SDI 42 55270866Simp#define PCLK_PWM 43 56270866Simp#define PCLK_USBD 44 57270866Simp 58270866Simp/* hclk-gates */ 59270866Simp#define HCLK_HALF 48 60270866Simp#define HCLK_X2 49 61270866Simp#define HCLK_SDRAM 50 62270866Simp#define HCLK_USBH 51 63270866Simp#define HCLK_LCD 52 64270866Simp#define HCLK_NAND 53 65270866Simp#define HCLK_DMA3 54 66270866Simp#define HCLK_DMA2 55 67270866Simp#define HCLK_DMA1 56 68270866Simp#define HCLK_DMA0 57 69270866Simp 70270866Simp/* Total number of clocks. */ 71270866Simp#define NR_CLKS (HCLK_DMA0 + 1) 72270866Simp 73270866Simp#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H */ 74