1295011Sandrew/* 2295011Sandrew * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 3295011Sandrew * Author: Jeffy Chen <jeffy.chen@rock-chips.com> 4295011Sandrew * 5295011Sandrew * This program is free software; you can redistribute it and/or modify 6295011Sandrew * it under the terms of the GNU General Public License as published by 7295011Sandrew * the Free Software Foundation; either version 2 of the License, or 8295011Sandrew * (at your option) any later version. 9295011Sandrew * 10295011Sandrew * This program is distributed in the hope that it will be useful, 11295011Sandrew * but WITHOUT ANY WARRANTY; without even the implied warranty of 12295011Sandrew * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13295011Sandrew * GNU General Public License for more details. 14295011Sandrew */ 15295011Sandrew 16295011Sandrew#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 17295011Sandrew#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 18295011Sandrew 19295011Sandrew/* core clocks */ 20295011Sandrew#define PLL_APLL 1 21295011Sandrew#define PLL_DPLL 2 22295011Sandrew#define PLL_CPLL 3 23295011Sandrew#define PLL_GPLL 4 24295011Sandrew#define ARMCLK 5 25295011Sandrew 26295011Sandrew/* sclk gates (special clocks) */ 27295011Sandrew#define SCLK_SPI0 65 28295011Sandrew#define SCLK_NANDC 67 29295011Sandrew#define SCLK_SDMMC 68 30295011Sandrew#define SCLK_SDIO 69 31295011Sandrew#define SCLK_EMMC 71 32295011Sandrew#define SCLK_UART0 77 33295011Sandrew#define SCLK_UART1 78 34295011Sandrew#define SCLK_UART2 79 35295011Sandrew#define SCLK_I2S0 80 36295011Sandrew#define SCLK_I2S1 81 37295011Sandrew#define SCLK_I2S2 82 38295011Sandrew#define SCLK_SPDIF 83 39295011Sandrew#define SCLK_TIMER0 85 40295011Sandrew#define SCLK_TIMER1 86 41295011Sandrew#define SCLK_TIMER2 87 42295011Sandrew#define SCLK_TIMER3 88 43295011Sandrew#define SCLK_TIMER4 89 44295011Sandrew#define SCLK_TIMER5 90 45295011Sandrew#define SCLK_I2S_OUT 113 46295011Sandrew#define SCLK_SDMMC_DRV 114 47295011Sandrew#define SCLK_SDIO_DRV 115 48295011Sandrew#define SCLK_EMMC_DRV 117 49295011Sandrew#define SCLK_SDMMC_SAMPLE 118 50295011Sandrew#define SCLK_SDIO_SAMPLE 119 51295011Sandrew#define SCLK_EMMC_SAMPLE 121 52295011Sandrew 53295011Sandrew/* aclk gates */ 54295011Sandrew#define ACLK_DMAC 194 55295011Sandrew#define ACLK_PERI 210 56295011Sandrew 57295011Sandrew/* pclk gates */ 58295011Sandrew#define PCLK_GPIO0 320 59295011Sandrew#define PCLK_GPIO1 321 60295011Sandrew#define PCLK_GPIO2 322 61295011Sandrew#define PCLK_GPIO3 323 62295011Sandrew#define PCLK_GRF 329 63295011Sandrew#define PCLK_I2C0 332 64295011Sandrew#define PCLK_I2C1 333 65295011Sandrew#define PCLK_I2C2 334 66295011Sandrew#define PCLK_I2C3 335 67295011Sandrew#define PCLK_SPI0 338 68295011Sandrew#define PCLK_UART0 341 69295011Sandrew#define PCLK_UART1 342 70295011Sandrew#define PCLK_UART2 343 71295011Sandrew#define PCLK_PWM 350 72295011Sandrew#define PCLK_TIMER 353 73295011Sandrew#define PCLK_PERI 363 74295011Sandrew 75295011Sandrew/* hclk gates */ 76295011Sandrew#define HCLK_NANDC 453 77295011Sandrew#define HCLK_SDMMC 456 78295011Sandrew#define HCLK_SDIO 457 79295011Sandrew#define HCLK_EMMC 459 80295011Sandrew#define HCLK_PERI 478 81295011Sandrew 82295011Sandrew#define CLK_NR_CLKS (HCLK_PERI + 1) 83295011Sandrew 84295011Sandrew/* soft-reset indices */ 85295011Sandrew#define SRST_CORE0_PO 0 86295011Sandrew#define SRST_CORE1_PO 1 87295011Sandrew#define SRST_CORE2_PO 2 88295011Sandrew#define SRST_CORE3_PO 3 89295011Sandrew#define SRST_CORE0 4 90295011Sandrew#define SRST_CORE1 5 91295011Sandrew#define SRST_CORE2 6 92295011Sandrew#define SRST_CORE3 7 93295011Sandrew#define SRST_CORE0_DBG 8 94295011Sandrew#define SRST_CORE1_DBG 9 95295011Sandrew#define SRST_CORE2_DBG 10 96295011Sandrew#define SRST_CORE3_DBG 11 97295011Sandrew#define SRST_TOPDBG 12 98295011Sandrew#define SRST_ACLK_CORE 13 99295011Sandrew#define SRST_NOC 14 100295011Sandrew#define SRST_L2C 15 101295011Sandrew 102295011Sandrew#define SRST_CPUSYS_H 18 103295011Sandrew#define SRST_BUSSYS_H 19 104295011Sandrew#define SRST_SPDIF 20 105295011Sandrew#define SRST_INTMEM 21 106295011Sandrew#define SRST_ROM 22 107295011Sandrew#define SRST_OTG_ADP 23 108295011Sandrew#define SRST_I2S0 24 109295011Sandrew#define SRST_I2S1 25 110295011Sandrew#define SRST_I2S2 26 111295011Sandrew#define SRST_ACODEC_P 27 112295011Sandrew#define SRST_DFIMON 28 113295011Sandrew#define SRST_MSCH 29 114295011Sandrew#define SRST_EFUSE1024 30 115295011Sandrew#define SRST_EFUSE256 31 116295011Sandrew 117295011Sandrew#define SRST_GPIO0 32 118295011Sandrew#define SRST_GPIO1 33 119295011Sandrew#define SRST_GPIO2 34 120295011Sandrew#define SRST_GPIO3 35 121295011Sandrew#define SRST_PERIPH_NOC_A 36 122295011Sandrew#define SRST_PERIPH_NOC_BUS_H 37 123295011Sandrew#define SRST_PERIPH_NOC_P 38 124295011Sandrew#define SRST_UART0 39 125295011Sandrew#define SRST_UART1 40 126295011Sandrew#define SRST_UART2 41 127295011Sandrew#define SRST_PHYNOC 42 128295011Sandrew#define SRST_I2C0 43 129295011Sandrew#define SRST_I2C1 44 130295011Sandrew#define SRST_I2C2 45 131295011Sandrew#define SRST_I2C3 46 132295011Sandrew 133295011Sandrew#define SRST_PWM 48 134295011Sandrew#define SRST_A53_GIC 49 135295011Sandrew#define SRST_DAP 51 136295011Sandrew#define SRST_DAP_NOC 52 137295011Sandrew#define SRST_CRYPTO 53 138295011Sandrew#define SRST_SGRF 54 139295011Sandrew#define SRST_GRF 55 140295011Sandrew#define SRST_GMAC 56 141295011Sandrew#define SRST_PERIPH_NOC_H 58 142295011Sandrew#define SRST_MACPHY 63 143295011Sandrew 144295011Sandrew#define SRST_DMA 64 145295011Sandrew#define SRST_NANDC 68 146295011Sandrew#define SRST_USBOTG 69 147295011Sandrew#define SRST_OTGC 70 148295011Sandrew#define SRST_USBHOST0 71 149295011Sandrew#define SRST_HOST_CTRL0 72 150295011Sandrew#define SRST_USBHOST1 73 151295011Sandrew#define SRST_HOST_CTRL1 74 152295011Sandrew#define SRST_USBHOST2 75 153295011Sandrew#define SRST_HOST_CTRL2 76 154295011Sandrew#define SRST_USBPOR0 77 155295011Sandrew#define SRST_USBPOR1 78 156295011Sandrew#define SRST_DDRMSCH 79 157295011Sandrew 158295011Sandrew#define SRST_SMART_CARD 80 159295011Sandrew#define SRST_SDMMC 81 160295011Sandrew#define SRST_SDIO 82 161295011Sandrew#define SRST_EMMC 83 162295011Sandrew#define SRST_SPI 84 163295011Sandrew#define SRST_TSP_H 85 164295011Sandrew#define SRST_TSP 86 165295011Sandrew#define SRST_TSADC 87 166295011Sandrew#define SRST_DDRPHY 88 167295011Sandrew#define SRST_DDRPHY_P 89 168295011Sandrew#define SRST_DDRCTRL 90 169295011Sandrew#define SRST_DDRCTRL_P 91 170295011Sandrew#define SRST_HOST0_ECHI 92 171295011Sandrew#define SRST_HOST1_ECHI 93 172295011Sandrew#define SRST_HOST2_ECHI 94 173295011Sandrew#define SRST_VOP_NOC_A 95 174295011Sandrew 175295011Sandrew#define SRST_HDMI_P 96 176295011Sandrew#define SRST_VIO_ARBI_H 97 177295011Sandrew#define SRST_IEP_NOC_A 98 178295011Sandrew#define SRST_VIO_NOC_H 99 179295011Sandrew#define SRST_VOP_A 100 180295011Sandrew#define SRST_VOP_H 101 181295011Sandrew#define SRST_VOP_D 102 182295011Sandrew#define SRST_UTMI0 103 183295011Sandrew#define SRST_UTMI1 104 184295011Sandrew#define SRST_UTMI2 105 185295011Sandrew#define SRST_UTMI3 106 186295011Sandrew#define SRST_RGA 107 187295011Sandrew#define SRST_RGA_NOC_A 108 188295011Sandrew#define SRST_RGA_A 109 189295011Sandrew#define SRST_RGA_H 110 190295011Sandrew#define SRST_HDCP_A 111 191295011Sandrew 192295011Sandrew#define SRST_VPU_A 112 193295011Sandrew#define SRST_VPU_H 113 194295011Sandrew#define SRST_VPU_NOC_A 116 195295011Sandrew#define SRST_VPU_NOC_H 117 196295011Sandrew#define SRST_RKVDEC_A 118 197295011Sandrew#define SRST_RKVDEC_NOC_A 119 198295011Sandrew#define SRST_RKVDEC_H 120 199295011Sandrew#define SRST_RKVDEC_NOC_H 121 200295011Sandrew#define SRST_RKVDEC_CORE 122 201295011Sandrew#define SRST_RKVDEC_CABAC 123 202295011Sandrew#define SRST_IEP_A 124 203295011Sandrew#define SRST_IEP_H 125 204295011Sandrew#define SRST_GPU_A 126 205295011Sandrew#define SRST_GPU_NOC_A 127 206295011Sandrew 207295011Sandrew#define SRST_CORE_DBG 128 208295011Sandrew#define SRST_DBG_P 129 209295011Sandrew#define SRST_TIMER0 130 210295011Sandrew#define SRST_TIMER1 131 211295011Sandrew#define SRST_TIMER2 132 212295011Sandrew#define SRST_TIMER3 133 213295011Sandrew#define SRST_TIMER4 134 214295011Sandrew#define SRST_TIMER5 135 215295011Sandrew#define SRST_VIO_H2P 136 216295011Sandrew#define SRST_HDMIPHY 139 217295011Sandrew#define SRST_VDAC 140 218295011Sandrew#define SRST_TIMER_6CH_P 141 219295011Sandrew 220295011Sandrew#endif 221