qcom,gcc-msm8996.h revision 295011
1295011Sandrew/* 2295011Sandrew * Copyright (c) 2015, The Linux Foundation. All rights reserved. 3295011Sandrew * 4295011Sandrew * This software is licensed under the terms of the GNU General Public 5295011Sandrew * License version 2, as published by the Free Software Foundation, and 6295011Sandrew * may be copied, distributed, and modified under those terms. 7295011Sandrew * 8295011Sandrew * This program is distributed in the hope that it will be useful, 9295011Sandrew * but WITHOUT ANY WARRANTY; without even the implied warranty of 10295011Sandrew * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11295011Sandrew * GNU General Public License for more details. 12295011Sandrew */ 13295011Sandrew 14295011Sandrew#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H 15295011Sandrew#define _DT_BINDINGS_CLK_MSM_GCC_8996_H 16295011Sandrew 17295011Sandrew#define GPLL0_EARLY 0 18295011Sandrew#define GPLL0 1 19295011Sandrew#define GPLL1_EARLY 2 20295011Sandrew#define GPLL1 3 21295011Sandrew#define GPLL2_EARLY 4 22295011Sandrew#define GPLL2 5 23295011Sandrew#define GPLL3_EARLY 6 24295011Sandrew#define GPLL3 7 25295011Sandrew#define GPLL4_EARLY 8 26295011Sandrew#define GPLL4 9 27295011Sandrew#define SYSTEM_NOC_CLK_SRC 10 28295011Sandrew#define CONFIG_NOC_CLK_SRC 11 29295011Sandrew#define PERIPH_NOC_CLK_SRC 12 30295011Sandrew#define MMSS_BIMC_GFX_CLK_SRC 13 31295011Sandrew#define USB30_MASTER_CLK_SRC 14 32295011Sandrew#define USB30_MOCK_UTMI_CLK_SRC 15 33295011Sandrew#define USB3_PHY_AUX_CLK_SRC 16 34295011Sandrew#define USB20_MASTER_CLK_SRC 17 35295011Sandrew#define USB20_MOCK_UTMI_CLK_SRC 18 36295011Sandrew#define SDCC1_APPS_CLK_SRC 19 37295011Sandrew#define SDCC1_ICE_CORE_CLK_SRC 20 38295011Sandrew#define SDCC2_APPS_CLK_SRC 21 39295011Sandrew#define SDCC3_APPS_CLK_SRC 22 40295011Sandrew#define SDCC4_APPS_CLK_SRC 23 41295011Sandrew#define BLSP1_QUP1_SPI_APPS_CLK_SRC 24 42295011Sandrew#define BLSP1_QUP1_I2C_APPS_CLK_SRC 25 43295011Sandrew#define BLSP1_UART1_APPS_CLK_SRC 26 44295011Sandrew#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 45295011Sandrew#define BLSP1_QUP2_I2C_APPS_CLK_SRC 28 46295011Sandrew#define BLSP1_UART2_APPS_CLK_SRC 29 47295011Sandrew#define BLSP1_QUP3_SPI_APPS_CLK_SRC 30 48295011Sandrew#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 49295011Sandrew#define BLSP1_UART3_APPS_CLK_SRC 32 50295011Sandrew#define BLSP1_QUP4_SPI_APPS_CLK_SRC 33 51295011Sandrew#define BLSP1_QUP4_I2C_APPS_CLK_SRC 34 52295011Sandrew#define BLSP1_UART4_APPS_CLK_SRC 35 53295011Sandrew#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 54295011Sandrew#define BLSP1_QUP5_I2C_APPS_CLK_SRC 37 55295011Sandrew#define BLSP1_UART5_APPS_CLK_SRC 38 56295011Sandrew#define BLSP1_QUP6_SPI_APPS_CLK_SRC 39 57295011Sandrew#define BLSP1_QUP6_I2C_APPS_CLK_SRC 40 58295011Sandrew#define BLSP1_UART6_APPS_CLK_SRC 41 59295011Sandrew#define BLSP2_QUP1_SPI_APPS_CLK_SRC 42 60295011Sandrew#define BLSP2_QUP1_I2C_APPS_CLK_SRC 43 61295011Sandrew#define BLSP2_UART1_APPS_CLK_SRC 44 62295011Sandrew#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 63295011Sandrew#define BLSP2_QUP2_I2C_APPS_CLK_SRC 46 64295011Sandrew#define BLSP2_UART2_APPS_CLK_SRC 47 65295011Sandrew#define BLSP2_QUP3_SPI_APPS_CLK_SRC 48 66295011Sandrew#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 67295011Sandrew#define BLSP2_UART3_APPS_CLK_SRC 50 68295011Sandrew#define BLSP2_QUP4_SPI_APPS_CLK_SRC 51 69295011Sandrew#define BLSP2_QUP4_I2C_APPS_CLK_SRC 52 70295011Sandrew#define BLSP2_UART4_APPS_CLK_SRC 53 71295011Sandrew#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 72295011Sandrew#define BLSP2_QUP5_I2C_APPS_CLK_SRC 55 73295011Sandrew#define BLSP2_UART5_APPS_CLK_SRC 56 74295011Sandrew#define BLSP2_QUP6_SPI_APPS_CLK_SRC 57 75295011Sandrew#define BLSP2_QUP6_I2C_APPS_CLK_SRC 58 76295011Sandrew#define BLSP2_UART6_APPS_CLK_SRC 59 77295011Sandrew#define PDM2_CLK_SRC 60 78295011Sandrew#define TSIF_REF_CLK_SRC 61 79295011Sandrew#define CE1_CLK_SRC 62 80295011Sandrew#define GCC_SLEEP_CLK_SRC 63 81295011Sandrew#define BIMC_CLK_SRC 64 82295011Sandrew#define HMSS_AHB_CLK_SRC 65 83295011Sandrew#define BIMC_HMSS_AXI_CLK_SRC 66 84295011Sandrew#define HMSS_RBCPR_CLK_SRC 67 85295011Sandrew#define HMSS_GPLL0_CLK_SRC 68 86295011Sandrew#define GP1_CLK_SRC 69 87295011Sandrew#define GP2_CLK_SRC 70 88295011Sandrew#define GP3_CLK_SRC 71 89295011Sandrew#define PCIE_AUX_CLK_SRC 72 90295011Sandrew#define UFS_AXI_CLK_SRC 73 91295011Sandrew#define UFS_ICE_CORE_CLK_SRC 74 92295011Sandrew#define QSPI_SER_CLK_SRC 75 93295011Sandrew#define GCC_SYS_NOC_AXI_CLK 76 94295011Sandrew#define GCC_SYS_NOC_HMSS_AHB_CLK 77 95295011Sandrew#define GCC_SNOC_CNOC_AHB_CLK 78 96295011Sandrew#define GCC_SNOC_PNOC_AHB_CLK 79 97295011Sandrew#define GCC_SYS_NOC_AT_CLK 80 98295011Sandrew#define GCC_SYS_NOC_USB3_AXI_CLK 81 99295011Sandrew#define GCC_SYS_NOC_UFS_AXI_CLK 82 100295011Sandrew#define GCC_CFG_NOC_AHB_CLK 83 101295011Sandrew#define GCC_PERIPH_NOC_AHB_CLK 84 102295011Sandrew#define GCC_PERIPH_NOC_USB20_AHB_CLK 85 103295011Sandrew#define GCC_TIC_CLK 86 104295011Sandrew#define GCC_IMEM_AXI_CLK 87 105295011Sandrew#define GCC_MMSS_SYS_NOC_AXI_CLK 88 106295011Sandrew#define GCC_MMSS_NOC_CFG_AHB_CLK 89 107295011Sandrew#define GCC_MMSS_BIMC_GFX_CLK 90 108295011Sandrew#define GCC_USB30_MASTER_CLK 91 109295011Sandrew#define GCC_USB30_SLEEP_CLK 92 110295011Sandrew#define GCC_USB30_MOCK_UTMI_CLK 93 111295011Sandrew#define GCC_USB3_PHY_AUX_CLK 94 112295011Sandrew#define GCC_USB3_PHY_PIPE_CLK 95 113295011Sandrew#define GCC_USB20_MASTER_CLK 96 114295011Sandrew#define GCC_USB20_SLEEP_CLK 97 115295011Sandrew#define GCC_USB20_MOCK_UTMI_CLK 98 116295011Sandrew#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99 117295011Sandrew#define GCC_SDCC1_APPS_CLK 100 118295011Sandrew#define GCC_SDCC1_AHB_CLK 101 119295011Sandrew#define GCC_SDCC1_ICE_CORE_CLK 102 120295011Sandrew#define GCC_SDCC2_APPS_CLK 103 121295011Sandrew#define GCC_SDCC2_AHB_CLK 104 122295011Sandrew#define GCC_SDCC3_APPS_CLK 105 123295011Sandrew#define GCC_SDCC3_AHB_CLK 106 124295011Sandrew#define GCC_SDCC4_APPS_CLK 107 125295011Sandrew#define GCC_SDCC4_AHB_CLK 108 126295011Sandrew#define GCC_BLSP1_AHB_CLK 109 127295011Sandrew#define GCC_BLSP1_SLEEP_CLK 110 128295011Sandrew#define GCC_BLSP1_QUP1_SPI_APPS_CLK 111 129295011Sandrew#define GCC_BLSP1_QUP1_I2C_APPS_CLK 112 130295011Sandrew#define GCC_BLSP1_UART1_APPS_CLK 113 131295011Sandrew#define GCC_BLSP1_QUP2_SPI_APPS_CLK 114 132295011Sandrew#define GCC_BLSP1_QUP2_I2C_APPS_CLK 115 133295011Sandrew#define GCC_BLSP1_UART2_APPS_CLK 116 134295011Sandrew#define GCC_BLSP1_QUP3_SPI_APPS_CLK 117 135295011Sandrew#define GCC_BLSP1_QUP3_I2C_APPS_CLK 118 136295011Sandrew#define GCC_BLSP1_UART3_APPS_CLK 119 137295011Sandrew#define GCC_BLSP1_QUP4_SPI_APPS_CLK 120 138295011Sandrew#define GCC_BLSP1_QUP4_I2C_APPS_CLK 121 139295011Sandrew#define GCC_BLSP1_UART4_APPS_CLK 122 140295011Sandrew#define GCC_BLSP1_QUP5_SPI_APPS_CLK 123 141295011Sandrew#define GCC_BLSP1_QUP5_I2C_APPS_CLK 124 142295011Sandrew#define GCC_BLSP1_UART5_APPS_CLK 125 143295011Sandrew#define GCC_BLSP1_QUP6_SPI_APPS_CLK 126 144295011Sandrew#define GCC_BLSP1_QUP6_I2C_APPS_CLK 127 145295011Sandrew#define GCC_BLSP1_UART6_APPS_CLK 128 146295011Sandrew#define GCC_BLSP2_AHB_CLK 129 147295011Sandrew#define GCC_BLSP2_SLEEP_CLK 130 148295011Sandrew#define GCC_BLSP2_QUP1_SPI_APPS_CLK 131 149295011Sandrew#define GCC_BLSP2_QUP1_I2C_APPS_CLK 132 150295011Sandrew#define GCC_BLSP2_UART1_APPS_CLK 133 151295011Sandrew#define GCC_BLSP2_QUP2_SPI_APPS_CLK 134 152295011Sandrew#define GCC_BLSP2_QUP2_I2C_APPS_CLK 135 153295011Sandrew#define GCC_BLSP2_UART2_APPS_CLK 136 154295011Sandrew#define GCC_BLSP2_QUP3_SPI_APPS_CLK 137 155295011Sandrew#define GCC_BLSP2_QUP3_I2C_APPS_CLK 138 156295011Sandrew#define GCC_BLSP2_UART3_APPS_CLK 139 157295011Sandrew#define GCC_BLSP2_QUP4_SPI_APPS_CLK 140 158295011Sandrew#define GCC_BLSP2_QUP4_I2C_APPS_CLK 141 159295011Sandrew#define GCC_BLSP2_UART4_APPS_CLK 142 160295011Sandrew#define GCC_BLSP2_QUP5_SPI_APPS_CLK 143 161295011Sandrew#define GCC_BLSP2_QUP5_I2C_APPS_CLK 144 162295011Sandrew#define GCC_BLSP2_UART5_APPS_CLK 145 163295011Sandrew#define GCC_BLSP2_QUP6_SPI_APPS_CLK 146 164295011Sandrew#define GCC_BLSP2_QUP6_I2C_APPS_CLK 147 165295011Sandrew#define GCC_BLSP2_UART6_APPS_CLK 148 166295011Sandrew#define GCC_PDM_AHB_CLK 149 167295011Sandrew#define GCC_PDM_XO4_CLK 150 168295011Sandrew#define GCC_PDM2_CLK 151 169295011Sandrew#define GCC_PRNG_AHB_CLK 152 170295011Sandrew#define GCC_TSIF_AHB_CLK 153 171295011Sandrew#define GCC_TSIF_REF_CLK 154 172295011Sandrew#define GCC_TSIF_INACTIVITY_TIMERS_CLK 155 173295011Sandrew#define GCC_TCSR_AHB_CLK 156 174295011Sandrew#define GCC_BOOT_ROM_AHB_CLK 157 175295011Sandrew#define GCC_MSG_RAM_AHB_CLK 158 176295011Sandrew#define GCC_TLMM_AHB_CLK 159 177295011Sandrew#define GCC_TLMM_CLK 160 178295011Sandrew#define GCC_MPM_AHB_CLK 161 179295011Sandrew#define GCC_SPMI_SER_CLK 162 180295011Sandrew#define GCC_SPMI_CNOC_AHB_CLK 163 181295011Sandrew#define GCC_CE1_CLK 164 182295011Sandrew#define GCC_CE1_AXI_CLK 165 183295011Sandrew#define GCC_CE1_AHB_CLK 166 184295011Sandrew#define GCC_BIMC_HMSS_AXI_CLK 167 185295011Sandrew#define GCC_BIMC_GFX_CLK 168 186295011Sandrew#define GCC_HMSS_AHB_CLK 169 187295011Sandrew#define GCC_HMSS_SLV_AXI_CLK 170 188295011Sandrew#define GCC_HMSS_MSTR_AXI_CLK 171 189295011Sandrew#define GCC_HMSS_RBCPR_CLK 172 190295011Sandrew#define GCC_GP1_CLK 173 191295011Sandrew#define GCC_GP2_CLK 174 192295011Sandrew#define GCC_GP3_CLK 175 193295011Sandrew#define GCC_PCIE_0_SLV_AXI_CLK 176 194295011Sandrew#define GCC_PCIE_0_MSTR_AXI_CLK 177 195295011Sandrew#define GCC_PCIE_0_CFG_AHB_CLK 178 196295011Sandrew#define GCC_PCIE_0_AUX_CLK 179 197295011Sandrew#define GCC_PCIE_0_PIPE_CLK 180 198295011Sandrew#define GCC_PCIE_1_SLV_AXI_CLK 181 199295011Sandrew#define GCC_PCIE_1_MSTR_AXI_CLK 182 200295011Sandrew#define GCC_PCIE_1_CFG_AHB_CLK 183 201295011Sandrew#define GCC_PCIE_1_AUX_CLK 184 202295011Sandrew#define GCC_PCIE_1_PIPE_CLK 185 203295011Sandrew#define GCC_PCIE_2_SLV_AXI_CLK 186 204295011Sandrew#define GCC_PCIE_2_MSTR_AXI_CLK 187 205295011Sandrew#define GCC_PCIE_2_CFG_AHB_CLK 188 206295011Sandrew#define GCC_PCIE_2_AUX_CLK 189 207295011Sandrew#define GCC_PCIE_2_PIPE_CLK 190 208295011Sandrew#define GCC_PCIE_PHY_CFG_AHB_CLK 191 209295011Sandrew#define GCC_PCIE_PHY_AUX_CLK 192 210295011Sandrew#define GCC_UFS_AXI_CLK 193 211295011Sandrew#define GCC_UFS_AHB_CLK 194 212295011Sandrew#define GCC_UFS_TX_CFG_CLK 195 213295011Sandrew#define GCC_UFS_RX_CFG_CLK 196 214295011Sandrew#define GCC_UFS_TX_SYMBOL_0_CLK 197 215295011Sandrew#define GCC_UFS_RX_SYMBOL_0_CLK 198 216295011Sandrew#define GCC_UFS_RX_SYMBOL_1_CLK 199 217295011Sandrew#define GCC_UFS_UNIPRO_CORE_CLK 200 218295011Sandrew#define GCC_UFS_ICE_CORE_CLK 201 219295011Sandrew#define GCC_UFS_SYS_CLK_CORE_CLK 202 220295011Sandrew#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203 221295011Sandrew#define GCC_AGGRE0_SNOC_AXI_CLK 204 222295011Sandrew#define GCC_AGGRE0_CNOC_AHB_CLK 205 223295011Sandrew#define GCC_SMMU_AGGRE0_AXI_CLK 206 224295011Sandrew#define GCC_SMMU_AGGRE0_AHB_CLK 207 225295011Sandrew#define GCC_AGGRE1_PNOC_AHB_CLK 208 226295011Sandrew#define GCC_AGGRE2_UFS_AXI_CLK 209 227295011Sandrew#define GCC_AGGRE2_USB3_AXI_CLK 210 228295011Sandrew#define GCC_QSPI_AHB_CLK 211 229295011Sandrew#define GCC_QSPI_SER_CLK 212 230295011Sandrew#define GCC_USB3_CLKREF_CLK 213 231295011Sandrew#define GCC_HDMI_CLKREF_CLK 214 232295011Sandrew#define GCC_UFS_CLKREF_CLK 215 233295011Sandrew#define GCC_PCIE_CLKREF_CLK 216 234295011Sandrew#define GCC_RX2_USB2_CLKREF_CLK 217 235295011Sandrew#define GCC_RX1_USB2_CLKREF_CLK 218 236295011Sandrew 237295011Sandrew#define GCC_SYSTEM_NOC_BCR 0 238295011Sandrew#define GCC_CONFIG_NOC_BCR 1 239295011Sandrew#define GCC_PERIPH_NOC_BCR 2 240295011Sandrew#define GCC_IMEM_BCR 3 241295011Sandrew#define GCC_MMSS_BCR 4 242295011Sandrew#define GCC_PIMEM_BCR 5 243295011Sandrew#define GCC_QDSS_BCR 6 244295011Sandrew#define GCC_USB_30_BCR 7 245295011Sandrew#define GCC_USB_20_BCR 8 246295011Sandrew#define GCC_QUSB2PHY_PRIM_BCR 9 247295011Sandrew#define GCC_QUSB2PHY_SEC_BCR 10 248295011Sandrew#define GCC_USB_PHY_CFG_AHB2PHY_BCR 11 249295011Sandrew#define GCC_SDCC1_BCR 12 250295011Sandrew#define GCC_SDCC2_BCR 13 251295011Sandrew#define GCC_SDCC3_BCR 14 252295011Sandrew#define GCC_SDCC4_BCR 15 253295011Sandrew#define GCC_BLSP1_BCR 16 254295011Sandrew#define GCC_BLSP1_QUP1_BCR 17 255295011Sandrew#define GCC_BLSP1_UART1_BCR 18 256295011Sandrew#define GCC_BLSP1_QUP2_BCR 19 257295011Sandrew#define GCC_BLSP1_UART2_BCR 20 258295011Sandrew#define GCC_BLSP1_QUP3_BCR 21 259295011Sandrew#define GCC_BLSP1_UART3_BCR 22 260295011Sandrew#define GCC_BLSP1_QUP4_BCR 23 261295011Sandrew#define GCC_BLSP1_UART4_BCR 24 262295011Sandrew#define GCC_BLSP1_QUP5_BCR 25 263295011Sandrew#define GCC_BLSP1_UART5_BCR 26 264295011Sandrew#define GCC_BLSP1_QUP6_BCR 27 265295011Sandrew#define GCC_BLSP1_UART6_BCR 28 266295011Sandrew#define GCC_BLSP2_BCR 29 267295011Sandrew#define GCC_BLSP2_QUP1_BCR 30 268295011Sandrew#define GCC_BLSP2_UART1_BCR 31 269295011Sandrew#define GCC_BLSP2_QUP2_BCR 32 270295011Sandrew#define GCC_BLSP2_UART2_BCR 33 271295011Sandrew#define GCC_BLSP2_QUP3_BCR 34 272295011Sandrew#define GCC_BLSP2_UART3_BCR 35 273295011Sandrew#define GCC_BLSP2_QUP4_BCR 36 274295011Sandrew#define GCC_BLSP2_UART4_BCR 37 275295011Sandrew#define GCC_BLSP2_QUP5_BCR 38 276295011Sandrew#define GCC_BLSP2_UART5_BCR 39 277295011Sandrew#define GCC_BLSP2_QUP6_BCR 40 278295011Sandrew#define GCC_BLSP2_UART6_BCR 41 279295011Sandrew#define GCC_PDM_BCR 42 280295011Sandrew#define GCC_PRNG_BCR 43 281295011Sandrew#define GCC_TSIF_BCR 44 282295011Sandrew#define GCC_TCSR_BCR 45 283295011Sandrew#define GCC_BOOT_ROM_BCR 46 284295011Sandrew#define GCC_MSG_RAM_BCR 47 285295011Sandrew#define GCC_TLMM_BCR 48 286295011Sandrew#define GCC_MPM_BCR 49 287295011Sandrew#define GCC_SEC_CTRL_BCR 50 288295011Sandrew#define GCC_SPMI_BCR 51 289295011Sandrew#define GCC_SPDM_BCR 52 290295011Sandrew#define GCC_CE1_BCR 53 291295011Sandrew#define GCC_BIMC_BCR 54 292295011Sandrew#define GCC_SNOC_BUS_TIMEOUT0_BCR 55 293295011Sandrew#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 294295011Sandrew#define GCC_SNOC_BUS_TIMEOUT1_BCR 57 295295011Sandrew#define GCC_SNOC_BUS_TIMEOUT3_BCR 58 296295011Sandrew#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59 297295011Sandrew#define GCC_PNOC_BUS_TIMEOUT0_BCR 60 298295011Sandrew#define GCC_PNOC_BUS_TIMEOUT1_BCR 61 299295011Sandrew#define GCC_PNOC_BUS_TIMEOUT2_BCR 62 300295011Sandrew#define GCC_PNOC_BUS_TIMEOUT3_BCR 63 301295011Sandrew#define GCC_PNOC_BUS_TIMEOUT4_BCR 64 302295011Sandrew#define GCC_CNOC_BUS_TIMEOUT0_BCR 65 303295011Sandrew#define GCC_CNOC_BUS_TIMEOUT1_BCR 66 304295011Sandrew#define GCC_CNOC_BUS_TIMEOUT2_BCR 67 305295011Sandrew#define GCC_CNOC_BUS_TIMEOUT3_BCR 68 306295011Sandrew#define GCC_CNOC_BUS_TIMEOUT4_BCR 69 307295011Sandrew#define GCC_CNOC_BUS_TIMEOUT5_BCR 70 308295011Sandrew#define GCC_CNOC_BUS_TIMEOUT6_BCR 71 309295011Sandrew#define GCC_CNOC_BUS_TIMEOUT7_BCR 72 310295011Sandrew#define GCC_CNOC_BUS_TIMEOUT8_BCR 73 311295011Sandrew#define GCC_CNOC_BUS_TIMEOUT9_BCR 74 312295011Sandrew#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75 313295011Sandrew#define GCC_APB2JTAG_BCR 76 314295011Sandrew#define GCC_RBCPR_CX_BCR 77 315295011Sandrew#define GCC_RBCPR_MX_BCR 78 316295011Sandrew#define GCC_PCIE_0_BCR 79 317295011Sandrew#define GCC_PCIE_0_PHY_BCR 80 318295011Sandrew#define GCC_PCIE_1_BCR 81 319295011Sandrew#define GCC_PCIE_1_PHY_BCR 82 320295011Sandrew#define GCC_PCIE_2_BCR 83 321295011Sandrew#define GCC_PCIE_2_PHY_BCR 84 322295011Sandrew#define GCC_PCIE_PHY_BCR 85 323295011Sandrew#define GCC_DCD_BCR 86 324295011Sandrew#define GCC_OBT_ODT_BCR 87 325295011Sandrew#define GCC_UFS_BCR 88 326295011Sandrew#define GCC_SSC_BCR 89 327295011Sandrew#define GCC_VS_BCR 90 328295011Sandrew#define GCC_AGGRE0_NOC_BCR 91 329295011Sandrew#define GCC_AGGRE1_NOC_BCR 92 330295011Sandrew#define GCC_AGGRE2_NOC_BCR 93 331295011Sandrew#define GCC_DCC_BCR 94 332295011Sandrew#define GCC_IPA_BCR 95 333295011Sandrew#define GCC_QSPI_BCR 96 334295011Sandrew#define GCC_SKL_BCR 97 335295011Sandrew#define GCC_MSMPU_BCR 98 336295011Sandrew#define GCC_MSS_Q6_BCR 99 337295011Sandrew#define GCC_QREFS_VBG_CAL_BCR 100 338295011Sandrew 339295011Sandrew#endif 340