qcom,gcc-msm8960.h revision 262569
1262569Simp/* 2262569Simp * Copyright (c) 2013, The Linux Foundation. All rights reserved. 3262569Simp * 4262569Simp * This software is licensed under the terms of the GNU General Public 5262569Simp * License version 2, as published by the Free Software Foundation, and 6262569Simp * may be copied, distributed, and modified under those terms. 7262569Simp * 8262569Simp * This program is distributed in the hope that it will be useful, 9262569Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 10262569Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11262569Simp * GNU General Public License for more details. 12262569Simp */ 13262569Simp 14262569Simp#ifndef _DT_BINDINGS_CLK_MSM_GCC_8960_H 15262569Simp#define _DT_BINDINGS_CLK_MSM_GCC_8960_H 16262569Simp 17262569Simp#define AFAB_CLK_SRC 0 18262569Simp#define AFAB_CORE_CLK 1 19262569Simp#define SFAB_MSS_Q6_SW_A_CLK 2 20262569Simp#define SFAB_MSS_Q6_FW_A_CLK 3 21262569Simp#define QDSS_STM_CLK 4 22262569Simp#define SCSS_A_CLK 5 23262569Simp#define SCSS_H_CLK 6 24262569Simp#define SCSS_XO_SRC_CLK 7 25262569Simp#define AFAB_EBI1_CH0_A_CLK 8 26262569Simp#define AFAB_EBI1_CH1_A_CLK 9 27262569Simp#define AFAB_AXI_S0_FCLK 10 28262569Simp#define AFAB_AXI_S1_FCLK 11 29262569Simp#define AFAB_AXI_S2_FCLK 12 30262569Simp#define AFAB_AXI_S3_FCLK 13 31262569Simp#define AFAB_AXI_S4_FCLK 14 32262569Simp#define SFAB_CORE_CLK 15 33262569Simp#define SFAB_AXI_S0_FCLK 16 34262569Simp#define SFAB_AXI_S1_FCLK 17 35262569Simp#define SFAB_AXI_S2_FCLK 18 36262569Simp#define SFAB_AXI_S3_FCLK 19 37262569Simp#define SFAB_AXI_S4_FCLK 20 38262569Simp#define SFAB_AHB_S0_FCLK 21 39262569Simp#define SFAB_AHB_S1_FCLK 22 40262569Simp#define SFAB_AHB_S2_FCLK 23 41262569Simp#define SFAB_AHB_S3_FCLK 24 42262569Simp#define SFAB_AHB_S4_FCLK 25 43262569Simp#define SFAB_AHB_S5_FCLK 26 44262569Simp#define SFAB_AHB_S6_FCLK 27 45262569Simp#define SFAB_AHB_S7_FCLK 28 46262569Simp#define QDSS_AT_CLK_SRC 29 47262569Simp#define QDSS_AT_CLK 30 48262569Simp#define QDSS_TRACECLKIN_CLK_SRC 31 49262569Simp#define QDSS_TRACECLKIN_CLK 32 50262569Simp#define QDSS_TSCTR_CLK_SRC 33 51262569Simp#define QDSS_TSCTR_CLK 34 52262569Simp#define SFAB_ADM0_M0_A_CLK 35 53262569Simp#define SFAB_ADM0_M1_A_CLK 36 54262569Simp#define SFAB_ADM0_M2_A_CLK 37 55262569Simp#define ADM0_CLK 38 56262569Simp#define ADM0_PBUS_CLK 39 57262569Simp#define MSS_XPU_CLK 40 58262569Simp#define IMEM0_A_CLK 41 59262569Simp#define QDSS_H_CLK 42 60262569Simp#define PCIE_A_CLK 43 61262569Simp#define PCIE_AUX_CLK 44 62262569Simp#define PCIE_PHY_REF_CLK 45 63262569Simp#define PCIE_H_CLK 46 64262569Simp#define SFAB_CLK_SRC 47 65262569Simp#define MAHB0_CLK 48 66262569Simp#define Q6SW_CLK_SRC 49 67262569Simp#define Q6SW_CLK 50 68262569Simp#define Q6FW_CLK_SRC 51 69262569Simp#define Q6FW_CLK 52 70262569Simp#define SFAB_MSS_M_A_CLK 53 71262569Simp#define SFAB_USB3_M_A_CLK 54 72262569Simp#define SFAB_LPASS_Q6_A_CLK 55 73262569Simp#define SFAB_AFAB_M_A_CLK 56 74262569Simp#define AFAB_SFAB_M0_A_CLK 57 75262569Simp#define AFAB_SFAB_M1_A_CLK 58 76262569Simp#define SFAB_SATA_S_H_CLK 59 77262569Simp#define DFAB_CLK_SRC 60 78262569Simp#define DFAB_CLK 61 79262569Simp#define SFAB_DFAB_M_A_CLK 62 80262569Simp#define DFAB_SFAB_M_A_CLK 63 81262569Simp#define DFAB_SWAY0_H_CLK 64 82262569Simp#define DFAB_SWAY1_H_CLK 65 83262569Simp#define DFAB_ARB0_H_CLK 66 84262569Simp#define DFAB_ARB1_H_CLK 67 85262569Simp#define PPSS_H_CLK 68 86262569Simp#define PPSS_PROC_CLK 69 87262569Simp#define PPSS_TIMER0_CLK 70 88262569Simp#define PPSS_TIMER1_CLK 71 89262569Simp#define PMEM_A_CLK 72 90262569Simp#define DMA_BAM_H_CLK 73 91262569Simp#define SIC_H_CLK 74 92262569Simp#define SPS_TIC_H_CLK 75 93262569Simp#define SLIMBUS_H_CLK 76 94262569Simp#define SLIMBUS_XO_SRC_CLK 77 95262569Simp#define CFPB_2X_CLK_SRC 78 96262569Simp#define CFPB_CLK 79 97262569Simp#define CFPB0_H_CLK 80 98262569Simp#define CFPB1_H_CLK 81 99262569Simp#define CFPB2_H_CLK 82 100262569Simp#define SFAB_CFPB_M_H_CLK 83 101262569Simp#define CFPB_MASTER_H_CLK 84 102262569Simp#define SFAB_CFPB_S_HCLK 85 103262569Simp#define CFPB_SPLITTER_H_CLK 86 104262569Simp#define TSIF_H_CLK 87 105262569Simp#define TSIF_INACTIVITY_TIMERS_CLK 88 106262569Simp#define TSIF_REF_SRC 89 107262569Simp#define TSIF_REF_CLK 90 108262569Simp#define CE1_H_CLK 91 109262569Simp#define CE1_CORE_CLK 92 110262569Simp#define CE1_SLEEP_CLK 93 111262569Simp#define CE2_H_CLK 94 112262569Simp#define CE2_CORE_CLK 95 113262569Simp#define CE2_SLEEP_CLK 96 114262569Simp#define SFPB_H_CLK_SRC 97 115262569Simp#define SFPB_H_CLK 98 116262569Simp#define SFAB_SFPB_M_H_CLK 99 117262569Simp#define SFAB_SFPB_S_H_CLK 100 118262569Simp#define RPM_PROC_CLK 101 119262569Simp#define RPM_BUS_H_CLK 102 120262569Simp#define RPM_SLEEP_CLK 103 121262569Simp#define RPM_TIMER_CLK 104 122262569Simp#define RPM_MSG_RAM_H_CLK 105 123262569Simp#define PMIC_ARB0_H_CLK 106 124262569Simp#define PMIC_ARB1_H_CLK 107 125262569Simp#define PMIC_SSBI2_SRC 108 126262569Simp#define PMIC_SSBI2_CLK 109 127262569Simp#define SDC1_H_CLK 110 128262569Simp#define SDC2_H_CLK 111 129262569Simp#define SDC3_H_CLK 112 130262569Simp#define SDC4_H_CLK 113 131262569Simp#define SDC5_H_CLK 114 132262569Simp#define SDC1_SRC 115 133262569Simp#define SDC2_SRC 116 134262569Simp#define SDC3_SRC 117 135262569Simp#define SDC4_SRC 118 136262569Simp#define SDC5_SRC 119 137262569Simp#define SDC1_CLK 120 138262569Simp#define SDC2_CLK 121 139262569Simp#define SDC3_CLK 122 140262569Simp#define SDC4_CLK 123 141262569Simp#define SDC5_CLK 124 142262569Simp#define DFAB_A2_H_CLK 125 143262569Simp#define USB_HS1_H_CLK 126 144262569Simp#define USB_HS1_XCVR_SRC 127 145262569Simp#define USB_HS1_XCVR_CLK 128 146262569Simp#define USB_HSIC_H_CLK 129 147262569Simp#define USB_HSIC_XCVR_FS_SRC 130 148262569Simp#define USB_HSIC_XCVR_FS_CLK 131 149262569Simp#define USB_HSIC_SYSTEM_CLK_SRC 132 150262569Simp#define USB_HSIC_SYSTEM_CLK 133 151262569Simp#define CFPB0_C0_H_CLK 134 152262569Simp#define CFPB0_C1_H_CLK 135 153262569Simp#define CFPB0_D0_H_CLK 136 154262569Simp#define CFPB0_D1_H_CLK 137 155262569Simp#define USB_FS1_H_CLK 138 156262569Simp#define USB_FS1_XCVR_FS_SRC 139 157262569Simp#define USB_FS1_XCVR_FS_CLK 140 158262569Simp#define USB_FS1_SYSTEM_CLK 141 159262569Simp#define USB_FS2_H_CLK 142 160262569Simp#define USB_FS2_XCVR_FS_SRC 143 161262569Simp#define USB_FS2_XCVR_FS_CLK 144 162262569Simp#define USB_FS2_SYSTEM_CLK 145 163262569Simp#define GSBI_COMMON_SIM_SRC 146 164262569Simp#define GSBI1_H_CLK 147 165262569Simp#define GSBI2_H_CLK 148 166262569Simp#define GSBI3_H_CLK 149 167262569Simp#define GSBI4_H_CLK 150 168262569Simp#define GSBI5_H_CLK 151 169262569Simp#define GSBI6_H_CLK 152 170262569Simp#define GSBI7_H_CLK 153 171262569Simp#define GSBI8_H_CLK 154 172262569Simp#define GSBI9_H_CLK 155 173262569Simp#define GSBI10_H_CLK 156 174262569Simp#define GSBI11_H_CLK 157 175262569Simp#define GSBI12_H_CLK 158 176262569Simp#define GSBI1_UART_SRC 159 177262569Simp#define GSBI1_UART_CLK 160 178262569Simp#define GSBI2_UART_SRC 161 179262569Simp#define GSBI2_UART_CLK 162 180262569Simp#define GSBI3_UART_SRC 163 181262569Simp#define GSBI3_UART_CLK 164 182262569Simp#define GSBI4_UART_SRC 165 183262569Simp#define GSBI4_UART_CLK 166 184262569Simp#define GSBI5_UART_SRC 167 185262569Simp#define GSBI5_UART_CLK 168 186262569Simp#define GSBI6_UART_SRC 169 187262569Simp#define GSBI6_UART_CLK 170 188262569Simp#define GSBI7_UART_SRC 171 189262569Simp#define GSBI7_UART_CLK 172 190262569Simp#define GSBI8_UART_SRC 173 191262569Simp#define GSBI8_UART_CLK 174 192262569Simp#define GSBI9_UART_SRC 175 193262569Simp#define GSBI9_UART_CLK 176 194262569Simp#define GSBI10_UART_SRC 177 195262569Simp#define GSBI10_UART_CLK 178 196262569Simp#define GSBI11_UART_SRC 179 197262569Simp#define GSBI11_UART_CLK 180 198262569Simp#define GSBI12_UART_SRC 181 199262569Simp#define GSBI12_UART_CLK 182 200262569Simp#define GSBI1_QUP_SRC 183 201262569Simp#define GSBI1_QUP_CLK 184 202262569Simp#define GSBI2_QUP_SRC 185 203262569Simp#define GSBI2_QUP_CLK 186 204262569Simp#define GSBI3_QUP_SRC 187 205262569Simp#define GSBI3_QUP_CLK 188 206262569Simp#define GSBI4_QUP_SRC 189 207262569Simp#define GSBI4_QUP_CLK 190 208262569Simp#define GSBI5_QUP_SRC 191 209262569Simp#define GSBI5_QUP_CLK 192 210262569Simp#define GSBI6_QUP_SRC 193 211262569Simp#define GSBI6_QUP_CLK 194 212262569Simp#define GSBI7_QUP_SRC 195 213262569Simp#define GSBI7_QUP_CLK 196 214262569Simp#define GSBI8_QUP_SRC 197 215262569Simp#define GSBI8_QUP_CLK 198 216262569Simp#define GSBI9_QUP_SRC 199 217262569Simp#define GSBI9_QUP_CLK 200 218262569Simp#define GSBI10_QUP_SRC 201 219262569Simp#define GSBI10_QUP_CLK 202 220262569Simp#define GSBI11_QUP_SRC 203 221262569Simp#define GSBI11_QUP_CLK 204 222262569Simp#define GSBI12_QUP_SRC 205 223262569Simp#define GSBI12_QUP_CLK 206 224262569Simp#define GSBI1_SIM_CLK 207 225262569Simp#define GSBI2_SIM_CLK 208 226262569Simp#define GSBI3_SIM_CLK 209 227262569Simp#define GSBI4_SIM_CLK 210 228262569Simp#define GSBI5_SIM_CLK 211 229262569Simp#define GSBI6_SIM_CLK 212 230262569Simp#define GSBI7_SIM_CLK 213 231262569Simp#define GSBI8_SIM_CLK 214 232262569Simp#define GSBI9_SIM_CLK 215 233262569Simp#define GSBI10_SIM_CLK 216 234262569Simp#define GSBI11_SIM_CLK 217 235262569Simp#define GSBI12_SIM_CLK 218 236262569Simp#define USB_HSIC_HSIC_CLK_SRC 219 237262569Simp#define USB_HSIC_HSIC_CLK 220 238262569Simp#define USB_HSIC_HSIO_CAL_CLK 221 239262569Simp#define SPDM_CFG_H_CLK 222 240262569Simp#define SPDM_MSTR_H_CLK 223 241262569Simp#define SPDM_FF_CLK_SRC 224 242262569Simp#define SPDM_FF_CLK 225 243262569Simp#define SEC_CTRL_CLK 226 244262569Simp#define SEC_CTRL_ACC_CLK_SRC 227 245262569Simp#define SEC_CTRL_ACC_CLK 228 246262569Simp#define TLMM_H_CLK 229 247262569Simp#define TLMM_CLK 230 248262569Simp#define SFAB_MSS_S_H_CLK 231 249262569Simp#define MSS_SLP_CLK 232 250262569Simp#define MSS_Q6SW_JTAG_CLK 233 251262569Simp#define MSS_Q6FW_JTAG_CLK 234 252262569Simp#define MSS_S_H_CLK 235 253262569Simp#define MSS_CXO_SRC_CLK 236 254262569Simp#define SATA_H_CLK 237 255262569Simp#define SATA_SRC_CLK 238 256262569Simp#define SATA_RXOOB_CLK 239 257262569Simp#define SATA_PMALIVE_CLK 240 258262569Simp#define SATA_PHY_REF_CLK 241 259262569Simp#define TSSC_CLK_SRC 242 260262569Simp#define TSSC_CLK 243 261262569Simp#define PDM_SRC 244 262262569Simp#define PDM_CLK 245 263262569Simp#define GP0_SRC 246 264262569Simp#define GP0_CLK 247 265262569Simp#define GP1_SRC 248 266262569Simp#define GP1_CLK 249 267262569Simp#define GP2_SRC 250 268262569Simp#define GP2_CLK 251 269262569Simp#define MPM_CLK 252 270262569Simp#define EBI1_CLK_SRC 253 271262569Simp#define EBI1_CH0_CLK 254 272262569Simp#define EBI1_CH1_CLK 255 273262569Simp#define EBI1_2X_CLK 256 274262569Simp#define EBI1_CH0_DQ_CLK 257 275262569Simp#define EBI1_CH1_DQ_CLK 258 276262569Simp#define EBI1_CH0_CA_CLK 259 277262569Simp#define EBI1_CH1_CA_CLK 260 278262569Simp#define EBI1_XO_CLK 261 279262569Simp#define SFAB_SMPSS_S_H_CLK 262 280262569Simp#define PRNG_SRC 263 281262569Simp#define PRNG_CLK 264 282262569Simp#define PXO_SRC 265 283262569Simp#define LPASS_CXO_CLK 266 284262569Simp#define LPASS_PXO_CLK 267 285262569Simp#define SPDM_CY_PORT0_CLK 268 286262569Simp#define SPDM_CY_PORT1_CLK 269 287262569Simp#define SPDM_CY_PORT2_CLK 270 288262569Simp#define SPDM_CY_PORT3_CLK 271 289262569Simp#define SPDM_CY_PORT4_CLK 272 290262569Simp#define SPDM_CY_PORT5_CLK 273 291262569Simp#define SPDM_CY_PORT6_CLK 274 292262569Simp#define SPDM_CY_PORT7_CLK 275 293262569Simp#define PLL0 276 294262569Simp#define PLL0_VOTE 277 295262569Simp#define PLL3 278 296262569Simp#define PLL3_VOTE 279 297262569Simp#define PLL4_VOTE 280 298262569Simp#define PLL5 281 299262569Simp#define PLL5_VOTE 282 300262569Simp#define PLL6 283 301262569Simp#define PLL6_VOTE 284 302262569Simp#define PLL7_VOTE 285 303262569Simp#define PLL8 286 304262569Simp#define PLL8_VOTE 287 305262569Simp#define PLL9 288 306262569Simp#define PLL10 289 307262569Simp#define PLL11 290 308262569Simp#define PLL12 291 309262569Simp#define PLL13 292 310262569Simp#define PLL14 293 311262569Simp#define PLL14_VOTE 294 312262569Simp 313262569Simp#endif 314