1270866Simp#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H 2270866Simp#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H 3270866Simp 4270866Simp/* core clocks */ 5270866Simp#define CLK_FIN_PLL 1 6270866Simp#define CLK_FOUT_APLL 2 7270866Simp#define CLK_FOUT_CPLL 3 8270866Simp#define CLK_FOUT_MPLL 4 9270866Simp#define CLK_FOUT_BPLL 5 10270866Simp#define CLK_FOUT_KPLL 6 11270866Simp 12270866Simp/* gate for special clocks (sclk) */ 13270866Simp#define CLK_SCLK_UART0 128 14270866Simp#define CLK_SCLK_UART1 129 15270866Simp#define CLK_SCLK_UART2 130 16270866Simp#define CLK_SCLK_UART3 131 17270866Simp#define CLK_SCLK_MMC0 132 18270866Simp#define CLK_SCLK_MMC1 133 19270866Simp#define CLK_SCLK_MMC2 134 20270866Simp 21270866Simp/* gate clocks */ 22270866Simp#define CLK_UART0 257 23270866Simp#define CLK_UART1 258 24270866Simp#define CLK_UART2 259 25270866Simp#define CLK_UART3 260 26270866Simp#define CLK_MCT 315 27270866Simp#define CLK_MMC0 351 28270866Simp#define CLK_MMC1 352 29270866Simp#define CLK_MMC2 353 30270866Simp 31270866Simp#define CLK_NR_CLKS 512 32270866Simp 33270866Simp#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ 34