1262569Simp/* 2262569Simp * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3271133Simp * Author: Andrzej Hajda <a.hajda@samsung.com> 4262569Simp * 5262569Simp * This program is free software; you can redistribute it and/or modify 6262569Simp * it under the terms of the GNU General Public License version 2 as 7262569Simp * published by the Free Software Foundation. 8262569Simp * 9262569Simp * Device Tree binding constants for Exynos4 clock controller. 10262569Simp*/ 11262569Simp 12262569Simp#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H 13262569Simp#define _DT_BINDINGS_CLOCK_EXYNOS_4_H 14262569Simp 15262569Simp/* core clocks */ 16262569Simp#define CLK_XXTI 1 17262569Simp#define CLK_XUSBXTI 2 18262569Simp#define CLK_FIN_PLL 3 19262569Simp#define CLK_FOUT_APLL 4 20262569Simp#define CLK_FOUT_MPLL 5 21262569Simp#define CLK_FOUT_EPLL 6 22262569Simp#define CLK_FOUT_VPLL 7 23262569Simp#define CLK_SCLK_APLL 8 24262569Simp#define CLK_SCLK_MPLL 9 25262569Simp#define CLK_SCLK_EPLL 10 26262569Simp#define CLK_SCLK_VPLL 11 27262569Simp#define CLK_ARM_CLK 12 28262569Simp#define CLK_ACLK200 13 29262569Simp#define CLK_ACLK100 14 30262569Simp#define CLK_ACLK160 15 31262569Simp#define CLK_ACLK133 16 32262569Simp#define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */ 33262569Simp#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */ 34262569Simp#define CLK_MOUT_CORE 19 35262569Simp#define CLK_MOUT_APLL 20 36271133Simp#define CLK_SCLK_HDMIPHY 22 37271133Simp#define CLK_OUT_DMC 23 38271133Simp#define CLK_OUT_TOP 24 39271133Simp#define CLK_OUT_LEFTBUS 25 40271133Simp#define CLK_OUT_RIGHTBUS 26 41271133Simp#define CLK_OUT_CPU 27 42262569Simp 43262569Simp/* gate for special clocks (sclk) */ 44262569Simp#define CLK_SCLK_FIMC0 128 45262569Simp#define CLK_SCLK_FIMC1 129 46262569Simp#define CLK_SCLK_FIMC2 130 47262569Simp#define CLK_SCLK_FIMC3 131 48262569Simp#define CLK_SCLK_CAM0 132 49262569Simp#define CLK_SCLK_CAM1 133 50262569Simp#define CLK_SCLK_CSIS0 134 51262569Simp#define CLK_SCLK_CSIS1 135 52262569Simp#define CLK_SCLK_HDMI 136 53262569Simp#define CLK_SCLK_MIXER 137 54262569Simp#define CLK_SCLK_DAC 138 55262569Simp#define CLK_SCLK_PIXEL 139 56262569Simp#define CLK_SCLK_FIMD0 140 57262569Simp#define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */ 58262569Simp#define CLK_SCLK_MDNIE_PWM0 142 59262569Simp#define CLK_SCLK_MIPI0 143 60262569Simp#define CLK_SCLK_AUDIO0 144 61262569Simp#define CLK_SCLK_MMC0 145 62262569Simp#define CLK_SCLK_MMC1 146 63262569Simp#define CLK_SCLK_MMC2 147 64262569Simp#define CLK_SCLK_MMC3 148 65262569Simp#define CLK_SCLK_MMC4 149 66262569Simp#define CLK_SCLK_SATA 150 /* Exynos4210 only */ 67262569Simp#define CLK_SCLK_UART0 151 68262569Simp#define CLK_SCLK_UART1 152 69262569Simp#define CLK_SCLK_UART2 153 70262569Simp#define CLK_SCLK_UART3 154 71262569Simp#define CLK_SCLK_UART4 155 72262569Simp#define CLK_SCLK_AUDIO1 156 73262569Simp#define CLK_SCLK_AUDIO2 157 74262569Simp#define CLK_SCLK_SPDIF 158 75262569Simp#define CLK_SCLK_SPI0 159 76262569Simp#define CLK_SCLK_SPI1 160 77262569Simp#define CLK_SCLK_SPI2 161 78262569Simp#define CLK_SCLK_SLIMBUS 162 79262569Simp#define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ 80262569Simp#define CLK_SCLK_MIPI1 164 /* Exynos4210 only */ 81262569Simp#define CLK_SCLK_PCM1 165 82262569Simp#define CLK_SCLK_PCM2 166 83262569Simp#define CLK_SCLK_I2S1 167 84262569Simp#define CLK_SCLK_I2S2 168 85262569Simp#define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */ 86262569Simp#define CLK_SCLK_MFC 170 87262569Simp#define CLK_SCLK_PCM0 171 88262569Simp#define CLK_SCLK_G3D 172 89262569Simp#define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */ 90262569Simp#define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */ 91262569Simp#define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */ 92262569Simp#define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */ 93262569Simp#define CLK_SCLK_FIMG2D 177 94262569Simp 95262569Simp/* gate clocks */ 96295436Sandrew#define CLK_SSS 255 97262569Simp#define CLK_FIMC0 256 98262569Simp#define CLK_FIMC1 257 99262569Simp#define CLK_FIMC2 258 100262569Simp#define CLK_FIMC3 259 101262569Simp#define CLK_CSIS0 260 102262569Simp#define CLK_CSIS1 261 103262569Simp#define CLK_JPEG 262 104262569Simp#define CLK_SMMU_FIMC0 263 105262569Simp#define CLK_SMMU_FIMC1 264 106262569Simp#define CLK_SMMU_FIMC2 265 107262569Simp#define CLK_SMMU_FIMC3 266 108262569Simp#define CLK_SMMU_JPEG 267 109262569Simp#define CLK_VP 268 110262569Simp#define CLK_MIXER 269 111262569Simp#define CLK_TVENC 270 /* Exynos4210 only */ 112262569Simp#define CLK_HDMI 271 113262569Simp#define CLK_SMMU_TV 272 114262569Simp#define CLK_MFC 273 115262569Simp#define CLK_SMMU_MFCL 274 116262569Simp#define CLK_SMMU_MFCR 275 117262569Simp#define CLK_G3D 276 118262569Simp#define CLK_G2D 277 119279385Simp#define CLK_ROTATOR 278 120279385Simp#define CLK_MDMA 279 121279385Simp#define CLK_SMMU_G2D 280 122279385Simp#define CLK_SMMU_ROTATOR 281 123279385Simp#define CLK_SMMU_MDMA 282 124262569Simp#define CLK_FIMD0 283 125262569Simp#define CLK_MIE0 284 126262569Simp#define CLK_MDNIE0 285 /* Exynos4412 only */ 127262569Simp#define CLK_DSIM0 286 128262569Simp#define CLK_SMMU_FIMD0 287 129262569Simp#define CLK_FIMD1 288 /* Exynos4210 only */ 130262569Simp#define CLK_MIE1 289 /* Exynos4210 only */ 131262569Simp#define CLK_DSIM1 290 /* Exynos4210 only */ 132262569Simp#define CLK_SMMU_FIMD1 291 /* Exynos4210 only */ 133262569Simp#define CLK_PDMA0 292 134262569Simp#define CLK_PDMA1 293 135262569Simp#define CLK_PCIE_PHY 294 136262569Simp#define CLK_SATA_PHY 295 /* Exynos4210 only */ 137262569Simp#define CLK_TSI 296 138262569Simp#define CLK_SDMMC0 297 139262569Simp#define CLK_SDMMC1 298 140262569Simp#define CLK_SDMMC2 299 141262569Simp#define CLK_SDMMC3 300 142262569Simp#define CLK_SDMMC4 301 143262569Simp#define CLK_SATA 302 /* Exynos4210 only */ 144262569Simp#define CLK_SROMC 303 145262569Simp#define CLK_USB_HOST 304 146262569Simp#define CLK_USB_DEVICE 305 147262569Simp#define CLK_PCIE 306 148262569Simp#define CLK_ONENAND 307 149262569Simp#define CLK_NFCON 308 150262569Simp#define CLK_SMMU_PCIE 309 151262569Simp#define CLK_GPS 310 152262569Simp#define CLK_SMMU_GPS 311 153262569Simp#define CLK_UART0 312 154262569Simp#define CLK_UART1 313 155262569Simp#define CLK_UART2 314 156262569Simp#define CLK_UART3 315 157262569Simp#define CLK_UART4 316 158262569Simp#define CLK_I2C0 317 159262569Simp#define CLK_I2C1 318 160262569Simp#define CLK_I2C2 319 161262569Simp#define CLK_I2C3 320 162262569Simp#define CLK_I2C4 321 163262569Simp#define CLK_I2C5 322 164262569Simp#define CLK_I2C6 323 165262569Simp#define CLK_I2C7 324 166262569Simp#define CLK_I2C_HDMI 325 167262569Simp#define CLK_TSADC 326 168262569Simp#define CLK_SPI0 327 169262569Simp#define CLK_SPI1 328 170262569Simp#define CLK_SPI2 329 171262569Simp#define CLK_I2S1 330 172262569Simp#define CLK_I2S2 331 173262569Simp#define CLK_PCM0 332 174262569Simp#define CLK_I2S0 333 175262569Simp#define CLK_PCM1 334 176262569Simp#define CLK_PCM2 335 177262569Simp#define CLK_PWM 336 178262569Simp#define CLK_SLIMBUS 337 179262569Simp#define CLK_SPDIF 338 180262569Simp#define CLK_AC97 339 181262569Simp#define CLK_MODEMIF 340 182262569Simp#define CLK_CHIPID 341 183262569Simp#define CLK_SYSREG 342 184262569Simp#define CLK_HDMI_CEC 343 185262569Simp#define CLK_MCT 344 186262569Simp#define CLK_WDT 345 187262569Simp#define CLK_RTC 346 188262569Simp#define CLK_KEYIF 347 189262569Simp#define CLK_AUDSS 348 190262569Simp#define CLK_MIPI_HSI 349 /* Exynos4210 only */ 191262569Simp#define CLK_PIXELASYNCM0 351 192262569Simp#define CLK_PIXELASYNCM1 352 193262569Simp#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */ 194262569Simp#define CLK_FIMC_LITE1 354 /* Exynos4x12 only */ 195262569Simp#define CLK_PPMUISPX 355 /* Exynos4x12 only */ 196262569Simp#define CLK_PPMUISPMX 356 /* Exynos4x12 only */ 197262569Simp#define CLK_FIMC_ISP 357 /* Exynos4x12 only */ 198262569Simp#define CLK_FIMC_DRC 358 /* Exynos4x12 only */ 199262569Simp#define CLK_FIMC_FD 359 /* Exynos4x12 only */ 200262569Simp#define CLK_MCUISP 360 /* Exynos4x12 only */ 201262569Simp#define CLK_GICISP 361 /* Exynos4x12 only */ 202262569Simp#define CLK_SMMU_ISP 362 /* Exynos4x12 only */ 203262569Simp#define CLK_SMMU_DRC 363 /* Exynos4x12 only */ 204262569Simp#define CLK_SMMU_FD 364 /* Exynos4x12 only */ 205262569Simp#define CLK_SMMU_LITE0 365 /* Exynos4x12 only */ 206262569Simp#define CLK_SMMU_LITE1 366 /* Exynos4x12 only */ 207262569Simp#define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */ 208262569Simp#define CLK_MPWM_ISP 368 /* Exynos4x12 only */ 209262569Simp#define CLK_I2C0_ISP 369 /* Exynos4x12 only */ 210262569Simp#define CLK_I2C1_ISP 370 /* Exynos4x12 only */ 211262569Simp#define CLK_MTCADC_ISP 371 /* Exynos4x12 only */ 212262569Simp#define CLK_PWM_ISP 372 /* Exynos4x12 only */ 213262569Simp#define CLK_WDT_ISP 373 /* Exynos4x12 only */ 214262569Simp#define CLK_UART_ISP 374 /* Exynos4x12 only */ 215262569Simp#define CLK_ASYNCAXIM 375 /* Exynos4x12 only */ 216262569Simp#define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */ 217262569Simp#define CLK_SPI0_ISP 377 /* Exynos4x12 only */ 218262569Simp#define CLK_SPI1_ISP 378 /* Exynos4x12 only */ 219262569Simp#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ 220262569Simp#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ 221262569Simp#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ 222262569Simp#define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */ 223262569Simp#define CLK_TMU_APBIF 383 224262569Simp 225262569Simp/* mux clocks */ 226262569Simp#define CLK_MOUT_FIMC0 384 227262569Simp#define CLK_MOUT_FIMC1 385 228262569Simp#define CLK_MOUT_FIMC2 386 229262569Simp#define CLK_MOUT_FIMC3 387 230262569Simp#define CLK_MOUT_CAM0 388 231262569Simp#define CLK_MOUT_CAM1 389 232262569Simp#define CLK_MOUT_CSIS0 390 233262569Simp#define CLK_MOUT_CSIS1 391 234262569Simp#define CLK_MOUT_G3D0 392 235262569Simp#define CLK_MOUT_G3D1 393 236262569Simp#define CLK_MOUT_G3D 394 237262569Simp#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ 238279385Simp#define CLK_MOUT_HDMI 396 239279385Simp#define CLK_MOUT_MIXER 397 240262569Simp 241271133Simp/* gate clocks - ppmu */ 242271133Simp#define CLK_PPMULEFT 400 243271133Simp#define CLK_PPMURIGHT 401 244271133Simp#define CLK_PPMUCAMIF 402 245271133Simp#define CLK_PPMUTV 403 246271133Simp#define CLK_PPMUMFC_L 404 247271133Simp#define CLK_PPMUMFC_R 405 248271133Simp#define CLK_PPMUG3D 406 249271133Simp#define CLK_PPMUIMAGE 407 250271133Simp#define CLK_PPMULCD0 408 251271133Simp#define CLK_PPMULCD1 409 /* Exynos4210 only */ 252271133Simp#define CLK_PPMUFILE 410 253271133Simp#define CLK_PPMUGPS 411 254271133Simp#define CLK_PPMUDMC0 412 255271133Simp#define CLK_PPMUDMC1 413 256271133Simp#define CLK_PPMUCPU 414 257271133Simp#define CLK_PPMUACP 415 258271133Simp 259262569Simp/* div clocks */ 260262569Simp#define CLK_DIV_ISP0 450 /* Exynos4x12 only */ 261262569Simp#define CLK_DIV_ISP1 451 /* Exynos4x12 only */ 262262569Simp#define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */ 263262569Simp#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */ 264262569Simp#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ 265262569Simp#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ 266279385Simp#define CLK_DIV_ACP 456 267279385Simp#define CLK_DIV_DMC 457 268279385Simp#define CLK_DIV_C2C 458 /* Exynos4x12 only */ 269279385Simp#define CLK_DIV_GDL 459 270279385Simp#define CLK_DIV_GDR 460 271262569Simp 272262569Simp/* must be greater than maximal clock id */ 273279385Simp#define CLK_NR_CLKS 461 274262569Simp 275262569Simp#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ 276