1279377Simp/* 2279377Simp * Copyright (C) 2012 Altera <www.altera.com> 3279377Simp * 4279377Simp * This program is free software; you can redistribute it and/or modify 5279377Simp * it under the terms of the GNU General Public License as published by 6279377Simp * the Free Software Foundation; either version 2 of the License, or 7279377Simp * (at your option) any later version. 8279377Simp * 9279377Simp * This program is distributed in the hope that it will be useful, 10279377Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 11279377Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12279377Simp * GNU General Public License for more details. 13279377Simp * 14279377Simp * You should have received a copy of the GNU General Public License 15279377Simp * along with this program. If not, see <http://www.gnu.org/licenses/>. 16279377Simp */ 17279377Simp 18279377Simp#include "skeleton.dtsi" 19279377Simp#include <dt-bindings/reset/altr,rst-mgr.h> 20279377Simp 21279377Simp/ { 22279377Simp #address-cells = <1>; 23279377Simp #size-cells = <1>; 24279377Simp 25279377Simp aliases { 26279377Simp ethernet0 = &gmac0; 27279377Simp ethernet1 = &gmac1; 28279377Simp serial0 = &uart0; 29279377Simp serial1 = &uart1; 30279377Simp timer0 = &timer0; 31279377Simp timer1 = &timer1; 32279377Simp timer2 = &timer2; 33279377Simp timer3 = &timer3; 34279377Simp }; 35279377Simp 36279377Simp cpus { 37279377Simp #address-cells = <1>; 38279377Simp #size-cells = <0>; 39295011Sandrew enable-method = "altr,socfpga-smp"; 40279377Simp 41279377Simp cpu@0 { 42279377Simp compatible = "arm,cortex-a9"; 43279377Simp device_type = "cpu"; 44279377Simp reg = <0>; 45279377Simp next-level-cache = <&L2>; 46279377Simp }; 47279377Simp cpu@1 { 48279377Simp compatible = "arm,cortex-a9"; 49279377Simp device_type = "cpu"; 50279377Simp reg = <1>; 51279377Simp next-level-cache = <&L2>; 52279377Simp }; 53279377Simp }; 54279377Simp 55279377Simp intc: intc@fffed000 { 56279377Simp compatible = "arm,cortex-a9-gic"; 57279377Simp #interrupt-cells = <3>; 58279377Simp interrupt-controller; 59279377Simp reg = <0xfffed000 0x1000>, 60279377Simp <0xfffec100 0x100>; 61279377Simp }; 62279377Simp 63279377Simp soc { 64279377Simp #address-cells = <1>; 65279377Simp #size-cells = <1>; 66279377Simp compatible = "simple-bus"; 67279377Simp device_type = "soc"; 68279377Simp interrupt-parent = <&intc>; 69279377Simp ranges; 70279377Simp 71279377Simp amba { 72279377Simp compatible = "arm,amba-bus"; 73279377Simp #address-cells = <1>; 74279377Simp #size-cells = <1>; 75279377Simp ranges; 76279377Simp 77279377Simp pdma: pdma@ffe01000 { 78279377Simp compatible = "arm,pl330", "arm,primecell"; 79279377Simp reg = <0xffe01000 0x1000>; 80279377Simp interrupts = <0 104 4>, 81279377Simp <0 105 4>, 82279377Simp <0 106 4>, 83279377Simp <0 107 4>, 84279377Simp <0 108 4>, 85279377Simp <0 109 4>, 86279377Simp <0 110 4>, 87279377Simp <0 111 4>; 88279377Simp #dma-cells = <1>; 89279377Simp #dma-channels = <8>; 90279377Simp #dma-requests = <32>; 91279377Simp clocks = <&l4_main_clk>; 92279377Simp clock-names = "apb_pclk"; 93279377Simp }; 94279377Simp }; 95279377Simp 96279377Simp can0: can@ffc00000 { 97279377Simp compatible = "bosch,d_can"; 98279377Simp reg = <0xffc00000 0x1000>; 99279377Simp interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; 100279377Simp clocks = <&can0_clk>; 101279377Simp status = "disabled"; 102279377Simp }; 103279377Simp 104279377Simp can1: can@ffc01000 { 105279377Simp compatible = "bosch,d_can"; 106279377Simp reg = <0xffc01000 0x1000>; 107279377Simp interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; 108279377Simp clocks = <&can1_clk>; 109279377Simp status = "disabled"; 110279377Simp }; 111279377Simp 112279377Simp clkmgr@ffd04000 { 113279377Simp compatible = "altr,clk-mgr"; 114279377Simp reg = <0xffd04000 0x1000>; 115279377Simp 116279377Simp clocks { 117279377Simp #address-cells = <1>; 118279377Simp #size-cells = <0>; 119279377Simp 120279377Simp osc1: osc1 { 121279377Simp #clock-cells = <0>; 122279377Simp compatible = "fixed-clock"; 123279377Simp }; 124279377Simp 125279377Simp osc2: osc2 { 126279377Simp #clock-cells = <0>; 127279377Simp compatible = "fixed-clock"; 128279377Simp }; 129279377Simp 130279377Simp f2s_periph_ref_clk: f2s_periph_ref_clk { 131279377Simp #clock-cells = <0>; 132279377Simp compatible = "fixed-clock"; 133279377Simp }; 134279377Simp 135279377Simp f2s_sdram_ref_clk: f2s_sdram_ref_clk { 136279377Simp #clock-cells = <0>; 137279377Simp compatible = "fixed-clock"; 138279377Simp }; 139279377Simp 140279377Simp main_pll: main_pll { 141279377Simp #address-cells = <1>; 142279377Simp #size-cells = <0>; 143279377Simp #clock-cells = <0>; 144279377Simp compatible = "altr,socfpga-pll-clock"; 145279377Simp clocks = <&osc1>; 146279377Simp reg = <0x40>; 147279377Simp 148279377Simp mpuclk: mpuclk { 149279377Simp #clock-cells = <0>; 150279377Simp compatible = "altr,socfpga-perip-clk"; 151279377Simp clocks = <&main_pll>; 152279377Simp div-reg = <0xe0 0 9>; 153279377Simp reg = <0x48>; 154279377Simp }; 155279377Simp 156279377Simp mainclk: mainclk { 157279377Simp #clock-cells = <0>; 158279377Simp compatible = "altr,socfpga-perip-clk"; 159279377Simp clocks = <&main_pll>; 160279377Simp div-reg = <0xe4 0 9>; 161279377Simp reg = <0x4C>; 162279377Simp }; 163279377Simp 164279377Simp dbg_base_clk: dbg_base_clk { 165279377Simp #clock-cells = <0>; 166279377Simp compatible = "altr,socfpga-perip-clk"; 167295011Sandrew clocks = <&main_pll>, <&osc1>; 168279377Simp div-reg = <0xe8 0 9>; 169279377Simp reg = <0x50>; 170279377Simp }; 171279377Simp 172279377Simp main_qspi_clk: main_qspi_clk { 173279377Simp #clock-cells = <0>; 174279377Simp compatible = "altr,socfpga-perip-clk"; 175279377Simp clocks = <&main_pll>; 176279377Simp reg = <0x54>; 177279377Simp }; 178279377Simp 179279377Simp main_nand_sdmmc_clk: main_nand_sdmmc_clk { 180279377Simp #clock-cells = <0>; 181279377Simp compatible = "altr,socfpga-perip-clk"; 182279377Simp clocks = <&main_pll>; 183279377Simp reg = <0x58>; 184279377Simp }; 185279377Simp 186279377Simp cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { 187279377Simp #clock-cells = <0>; 188279377Simp compatible = "altr,socfpga-perip-clk"; 189279377Simp clocks = <&main_pll>; 190279377Simp reg = <0x5C>; 191279377Simp }; 192279377Simp }; 193279377Simp 194279377Simp periph_pll: periph_pll { 195279377Simp #address-cells = <1>; 196279377Simp #size-cells = <0>; 197279377Simp #clock-cells = <0>; 198279377Simp compatible = "altr,socfpga-pll-clock"; 199279377Simp clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; 200279377Simp reg = <0x80>; 201279377Simp 202279377Simp emac0_clk: emac0_clk { 203279377Simp #clock-cells = <0>; 204279377Simp compatible = "altr,socfpga-perip-clk"; 205279377Simp clocks = <&periph_pll>; 206279377Simp reg = <0x88>; 207279377Simp }; 208279377Simp 209279377Simp emac1_clk: emac1_clk { 210279377Simp #clock-cells = <0>; 211279377Simp compatible = "altr,socfpga-perip-clk"; 212279377Simp clocks = <&periph_pll>; 213279377Simp reg = <0x8C>; 214279377Simp }; 215279377Simp 216279377Simp per_qspi_clk: per_qsi_clk { 217279377Simp #clock-cells = <0>; 218279377Simp compatible = "altr,socfpga-perip-clk"; 219279377Simp clocks = <&periph_pll>; 220279377Simp reg = <0x90>; 221279377Simp }; 222279377Simp 223279377Simp per_nand_mmc_clk: per_nand_mmc_clk { 224279377Simp #clock-cells = <0>; 225279377Simp compatible = "altr,socfpga-perip-clk"; 226279377Simp clocks = <&periph_pll>; 227279377Simp reg = <0x94>; 228279377Simp }; 229279377Simp 230279377Simp per_base_clk: per_base_clk { 231279377Simp #clock-cells = <0>; 232279377Simp compatible = "altr,socfpga-perip-clk"; 233279377Simp clocks = <&periph_pll>; 234279377Simp reg = <0x98>; 235279377Simp }; 236279377Simp 237279377Simp h2f_usr1_clk: h2f_usr1_clk { 238279377Simp #clock-cells = <0>; 239279377Simp compatible = "altr,socfpga-perip-clk"; 240279377Simp clocks = <&periph_pll>; 241279377Simp reg = <0x9C>; 242279377Simp }; 243279377Simp }; 244279377Simp 245279377Simp sdram_pll: sdram_pll { 246279377Simp #address-cells = <1>; 247279377Simp #size-cells = <0>; 248279377Simp #clock-cells = <0>; 249279377Simp compatible = "altr,socfpga-pll-clock"; 250279377Simp clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; 251279377Simp reg = <0xC0>; 252279377Simp 253279377Simp ddr_dqs_clk: ddr_dqs_clk { 254279377Simp #clock-cells = <0>; 255279377Simp compatible = "altr,socfpga-perip-clk"; 256279377Simp clocks = <&sdram_pll>; 257279377Simp reg = <0xC8>; 258279377Simp }; 259279377Simp 260279377Simp ddr_2x_dqs_clk: ddr_2x_dqs_clk { 261279377Simp #clock-cells = <0>; 262279377Simp compatible = "altr,socfpga-perip-clk"; 263279377Simp clocks = <&sdram_pll>; 264279377Simp reg = <0xCC>; 265279377Simp }; 266279377Simp 267279377Simp ddr_dq_clk: ddr_dq_clk { 268279377Simp #clock-cells = <0>; 269279377Simp compatible = "altr,socfpga-perip-clk"; 270279377Simp clocks = <&sdram_pll>; 271279377Simp reg = <0xD0>; 272279377Simp }; 273279377Simp 274279377Simp h2f_usr2_clk: h2f_usr2_clk { 275279377Simp #clock-cells = <0>; 276279377Simp compatible = "altr,socfpga-perip-clk"; 277279377Simp clocks = <&sdram_pll>; 278279377Simp reg = <0xD4>; 279279377Simp }; 280279377Simp }; 281279377Simp 282279377Simp mpu_periph_clk: mpu_periph_clk { 283279377Simp #clock-cells = <0>; 284279377Simp compatible = "altr,socfpga-perip-clk"; 285279377Simp clocks = <&mpuclk>; 286279377Simp fixed-divider = <4>; 287279377Simp }; 288279377Simp 289279377Simp mpu_l2_ram_clk: mpu_l2_ram_clk { 290279377Simp #clock-cells = <0>; 291279377Simp compatible = "altr,socfpga-perip-clk"; 292279377Simp clocks = <&mpuclk>; 293279377Simp fixed-divider = <2>; 294279377Simp }; 295279377Simp 296279377Simp l4_main_clk: l4_main_clk { 297279377Simp #clock-cells = <0>; 298279377Simp compatible = "altr,socfpga-gate-clk"; 299279377Simp clocks = <&mainclk>; 300279377Simp clk-gate = <0x60 0>; 301279377Simp }; 302279377Simp 303279377Simp l3_main_clk: l3_main_clk { 304279377Simp #clock-cells = <0>; 305279377Simp compatible = "altr,socfpga-perip-clk"; 306279377Simp clocks = <&mainclk>; 307279377Simp fixed-divider = <1>; 308279377Simp }; 309279377Simp 310279377Simp l3_mp_clk: l3_mp_clk { 311279377Simp #clock-cells = <0>; 312279377Simp compatible = "altr,socfpga-gate-clk"; 313279377Simp clocks = <&mainclk>; 314279377Simp div-reg = <0x64 0 2>; 315279377Simp clk-gate = <0x60 1>; 316279377Simp }; 317279377Simp 318279377Simp l3_sp_clk: l3_sp_clk { 319279377Simp #clock-cells = <0>; 320279377Simp compatible = "altr,socfpga-gate-clk"; 321295011Sandrew clocks = <&l3_mp_clk>; 322279377Simp div-reg = <0x64 2 2>; 323279377Simp }; 324279377Simp 325279377Simp l4_mp_clk: l4_mp_clk { 326279377Simp #clock-cells = <0>; 327279377Simp compatible = "altr,socfpga-gate-clk"; 328279377Simp clocks = <&mainclk>, <&per_base_clk>; 329279377Simp div-reg = <0x64 4 3>; 330279377Simp clk-gate = <0x60 2>; 331279377Simp }; 332279377Simp 333279377Simp l4_sp_clk: l4_sp_clk { 334279377Simp #clock-cells = <0>; 335279377Simp compatible = "altr,socfpga-gate-clk"; 336279377Simp clocks = <&mainclk>, <&per_base_clk>; 337279377Simp div-reg = <0x64 7 3>; 338279377Simp clk-gate = <0x60 3>; 339279377Simp }; 340279377Simp 341279377Simp dbg_at_clk: dbg_at_clk { 342279377Simp #clock-cells = <0>; 343279377Simp compatible = "altr,socfpga-gate-clk"; 344279377Simp clocks = <&dbg_base_clk>; 345279377Simp div-reg = <0x68 0 2>; 346279377Simp clk-gate = <0x60 4>; 347279377Simp }; 348279377Simp 349279377Simp dbg_clk: dbg_clk { 350279377Simp #clock-cells = <0>; 351279377Simp compatible = "altr,socfpga-gate-clk"; 352295011Sandrew clocks = <&dbg_at_clk>; 353279377Simp div-reg = <0x68 2 2>; 354279377Simp clk-gate = <0x60 5>; 355279377Simp }; 356279377Simp 357279377Simp dbg_trace_clk: dbg_trace_clk { 358279377Simp #clock-cells = <0>; 359279377Simp compatible = "altr,socfpga-gate-clk"; 360279377Simp clocks = <&dbg_base_clk>; 361279377Simp div-reg = <0x6C 0 3>; 362279377Simp clk-gate = <0x60 6>; 363279377Simp }; 364279377Simp 365279377Simp dbg_timer_clk: dbg_timer_clk { 366279377Simp #clock-cells = <0>; 367279377Simp compatible = "altr,socfpga-gate-clk"; 368279377Simp clocks = <&dbg_base_clk>; 369279377Simp clk-gate = <0x60 7>; 370279377Simp }; 371279377Simp 372279377Simp cfg_clk: cfg_clk { 373279377Simp #clock-cells = <0>; 374279377Simp compatible = "altr,socfpga-gate-clk"; 375279377Simp clocks = <&cfg_h2f_usr0_clk>; 376279377Simp clk-gate = <0x60 8>; 377279377Simp }; 378279377Simp 379279377Simp h2f_user0_clk: h2f_user0_clk { 380279377Simp #clock-cells = <0>; 381279377Simp compatible = "altr,socfpga-gate-clk"; 382279377Simp clocks = <&cfg_h2f_usr0_clk>; 383279377Simp clk-gate = <0x60 9>; 384279377Simp }; 385279377Simp 386279377Simp emac_0_clk: emac_0_clk { 387279377Simp #clock-cells = <0>; 388279377Simp compatible = "altr,socfpga-gate-clk"; 389279377Simp clocks = <&emac0_clk>; 390279377Simp clk-gate = <0xa0 0>; 391279377Simp }; 392279377Simp 393279377Simp emac_1_clk: emac_1_clk { 394279377Simp #clock-cells = <0>; 395279377Simp compatible = "altr,socfpga-gate-clk"; 396279377Simp clocks = <&emac1_clk>; 397279377Simp clk-gate = <0xa0 1>; 398279377Simp }; 399279377Simp 400279377Simp usb_mp_clk: usb_mp_clk { 401279377Simp #clock-cells = <0>; 402279377Simp compatible = "altr,socfpga-gate-clk"; 403279377Simp clocks = <&per_base_clk>; 404279377Simp clk-gate = <0xa0 2>; 405279377Simp div-reg = <0xa4 0 3>; 406279377Simp }; 407279377Simp 408279377Simp spi_m_clk: spi_m_clk { 409279377Simp #clock-cells = <0>; 410279377Simp compatible = "altr,socfpga-gate-clk"; 411279377Simp clocks = <&per_base_clk>; 412279377Simp clk-gate = <0xa0 3>; 413279377Simp div-reg = <0xa4 3 3>; 414279377Simp }; 415279377Simp 416279377Simp can0_clk: can0_clk { 417279377Simp #clock-cells = <0>; 418279377Simp compatible = "altr,socfpga-gate-clk"; 419279377Simp clocks = <&per_base_clk>; 420279377Simp clk-gate = <0xa0 4>; 421279377Simp div-reg = <0xa4 6 3>; 422279377Simp }; 423279377Simp 424279377Simp can1_clk: can1_clk { 425279377Simp #clock-cells = <0>; 426279377Simp compatible = "altr,socfpga-gate-clk"; 427279377Simp clocks = <&per_base_clk>; 428279377Simp clk-gate = <0xa0 5>; 429279377Simp div-reg = <0xa4 9 3>; 430279377Simp }; 431279377Simp 432279377Simp gpio_db_clk: gpio_db_clk { 433279377Simp #clock-cells = <0>; 434279377Simp compatible = "altr,socfpga-gate-clk"; 435279377Simp clocks = <&per_base_clk>; 436279377Simp clk-gate = <0xa0 6>; 437279377Simp div-reg = <0xa8 0 24>; 438279377Simp }; 439279377Simp 440279377Simp h2f_user1_clk: h2f_user1_clk { 441279377Simp #clock-cells = <0>; 442279377Simp compatible = "altr,socfpga-gate-clk"; 443279377Simp clocks = <&h2f_usr1_clk>; 444279377Simp clk-gate = <0xa0 7>; 445279377Simp }; 446279377Simp 447279377Simp sdmmc_clk: sdmmc_clk { 448279377Simp #clock-cells = <0>; 449279377Simp compatible = "altr,socfpga-gate-clk"; 450279377Simp clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 451279377Simp clk-gate = <0xa0 8>; 452279377Simp clk-phase = <0 135>; 453279377Simp }; 454279377Simp 455295011Sandrew sdmmc_clk_divided: sdmmc_clk_divided { 456295011Sandrew #clock-cells = <0>; 457295011Sandrew compatible = "altr,socfpga-gate-clk"; 458295011Sandrew clocks = <&sdmmc_clk>; 459295011Sandrew clk-gate = <0xa0 8>; 460295011Sandrew fixed-divider = <4>; 461295011Sandrew }; 462295011Sandrew 463279377Simp nand_x_clk: nand_x_clk { 464279377Simp #clock-cells = <0>; 465279377Simp compatible = "altr,socfpga-gate-clk"; 466279377Simp clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 467279377Simp clk-gate = <0xa0 9>; 468279377Simp }; 469279377Simp 470279377Simp nand_clk: nand_clk { 471279377Simp #clock-cells = <0>; 472279377Simp compatible = "altr,socfpga-gate-clk"; 473279377Simp clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 474279377Simp clk-gate = <0xa0 10>; 475279377Simp fixed-divider = <4>; 476279377Simp }; 477279377Simp 478279377Simp qspi_clk: qspi_clk { 479279377Simp #clock-cells = <0>; 480279377Simp compatible = "altr,socfpga-gate-clk"; 481279377Simp clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; 482279377Simp clk-gate = <0xa0 11>; 483279377Simp }; 484295011Sandrew 485295011Sandrew ddr_dqs_clk_gate: ddr_dqs_clk_gate { 486295011Sandrew #clock-cells = <0>; 487295011Sandrew compatible = "altr,socfpga-gate-clk"; 488295011Sandrew clocks = <&ddr_dqs_clk>; 489295011Sandrew clk-gate = <0xd8 0>; 490295011Sandrew }; 491295011Sandrew 492295011Sandrew ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { 493295011Sandrew #clock-cells = <0>; 494295011Sandrew compatible = "altr,socfpga-gate-clk"; 495295011Sandrew clocks = <&ddr_2x_dqs_clk>; 496295011Sandrew clk-gate = <0xd8 1>; 497295011Sandrew }; 498295011Sandrew 499295011Sandrew ddr_dq_clk_gate: ddr_dq_clk_gate { 500295011Sandrew #clock-cells = <0>; 501295011Sandrew compatible = "altr,socfpga-gate-clk"; 502295011Sandrew clocks = <&ddr_dq_clk>; 503295011Sandrew clk-gate = <0xd8 2>; 504295011Sandrew }; 505295011Sandrew 506295011Sandrew h2f_user2_clk: h2f_user2_clk { 507295011Sandrew #clock-cells = <0>; 508295011Sandrew compatible = "altr,socfpga-gate-clk"; 509295011Sandrew clocks = <&h2f_usr2_clk>; 510295011Sandrew clk-gate = <0xd8 3>; 511295011Sandrew }; 512295011Sandrew 513279377Simp }; 514295011Sandrew }; 515279377Simp 516295011Sandrew fpgamgr0: fpgamgr@ff706000 { 517295011Sandrew compatible = "altr,socfpga-fpga-mgr"; 518295011Sandrew reg = <0xff706000 0x1000 519295011Sandrew 0xffb90000 0x1000>; 520295011Sandrew interrupts = <0 175 4>; 521295011Sandrew }; 522295011Sandrew 523279377Simp gmac0: ethernet@ff700000 { 524279377Simp compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 525279377Simp altr,sysmgr-syscon = <&sysmgr 0x60 0>; 526279377Simp reg = <0xff700000 0x2000>; 527279377Simp interrupts = <0 115 4>; 528279377Simp interrupt-names = "macirq"; 529279377Simp mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 530279377Simp clocks = <&emac0_clk>; 531279377Simp clock-names = "stmmaceth"; 532279377Simp resets = <&rst EMAC0_RESET>; 533279377Simp reset-names = "stmmaceth"; 534279377Simp snps,multicast-filter-bins = <256>; 535279377Simp snps,perfect-filter-entries = <128>; 536295011Sandrew tx-fifo-depth = <4096>; 537295011Sandrew rx-fifo-depth = <4096>; 538279377Simp status = "disabled"; 539279377Simp }; 540279377Simp 541279377Simp gmac1: ethernet@ff702000 { 542279377Simp compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 543279377Simp altr,sysmgr-syscon = <&sysmgr 0x60 2>; 544279377Simp reg = <0xff702000 0x2000>; 545279377Simp interrupts = <0 120 4>; 546279377Simp interrupt-names = "macirq"; 547279377Simp mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 548279377Simp clocks = <&emac1_clk>; 549279377Simp clock-names = "stmmaceth"; 550279377Simp resets = <&rst EMAC1_RESET>; 551279377Simp reset-names = "stmmaceth"; 552279377Simp snps,multicast-filter-bins = <256>; 553279377Simp snps,perfect-filter-entries = <128>; 554295011Sandrew tx-fifo-depth = <4096>; 555295011Sandrew rx-fifo-depth = <4096>; 556279377Simp status = "disabled"; 557279377Simp }; 558279377Simp 559279377Simp gpio0: gpio@ff708000 { 560279377Simp #address-cells = <1>; 561279377Simp #size-cells = <0>; 562279377Simp compatible = "snps,dw-apb-gpio"; 563279377Simp reg = <0xff708000 0x1000>; 564295011Sandrew clocks = <&l4_mp_clk>; 565279377Simp status = "disabled"; 566279377Simp 567279377Simp porta: gpio-controller@0 { 568279377Simp compatible = "snps,dw-apb-gpio-port"; 569279377Simp gpio-controller; 570279377Simp #gpio-cells = <2>; 571279377Simp snps,nr-gpios = <29>; 572279377Simp reg = <0>; 573279377Simp interrupt-controller; 574279377Simp #interrupt-cells = <2>; 575279377Simp interrupts = <0 164 4>; 576279377Simp }; 577279377Simp }; 578279377Simp 579279377Simp gpio1: gpio@ff709000 { 580279377Simp #address-cells = <1>; 581279377Simp #size-cells = <0>; 582279377Simp compatible = "snps,dw-apb-gpio"; 583279377Simp reg = <0xff709000 0x1000>; 584295011Sandrew clocks = <&l4_mp_clk>; 585279377Simp status = "disabled"; 586279377Simp 587279377Simp portb: gpio-controller@0 { 588279377Simp compatible = "snps,dw-apb-gpio-port"; 589279377Simp gpio-controller; 590279377Simp #gpio-cells = <2>; 591279377Simp snps,nr-gpios = <29>; 592279377Simp reg = <0>; 593279377Simp interrupt-controller; 594279377Simp #interrupt-cells = <2>; 595279377Simp interrupts = <0 165 4>; 596279377Simp }; 597279377Simp }; 598279377Simp 599279377Simp gpio2: gpio@ff70a000 { 600279377Simp #address-cells = <1>; 601279377Simp #size-cells = <0>; 602279377Simp compatible = "snps,dw-apb-gpio"; 603279377Simp reg = <0xff70a000 0x1000>; 604295011Sandrew clocks = <&l4_mp_clk>; 605279377Simp status = "disabled"; 606279377Simp 607279377Simp portc: gpio-controller@0 { 608279377Simp compatible = "snps,dw-apb-gpio-port"; 609279377Simp gpio-controller; 610279377Simp #gpio-cells = <2>; 611279377Simp snps,nr-gpios = <27>; 612279377Simp reg = <0>; 613279377Simp interrupt-controller; 614279377Simp #interrupt-cells = <2>; 615279377Simp interrupts = <0 166 4>; 616279377Simp }; 617279377Simp }; 618279377Simp 619295011Sandrew i2c0: i2c@ffc04000 { 620295011Sandrew #address-cells = <1>; 621295011Sandrew #size-cells = <0>; 622295011Sandrew compatible = "snps,designware-i2c"; 623295011Sandrew reg = <0xffc04000 0x1000>; 624295011Sandrew clocks = <&l4_sp_clk>; 625295011Sandrew interrupts = <0 158 0x4>; 626295011Sandrew status = "disabled"; 627279377Simp }; 628279377Simp 629295011Sandrew i2c1: i2c@ffc05000 { 630295011Sandrew #address-cells = <1>; 631295011Sandrew #size-cells = <0>; 632295011Sandrew compatible = "snps,designware-i2c"; 633295011Sandrew reg = <0xffc05000 0x1000>; 634295011Sandrew clocks = <&l4_sp_clk>; 635295011Sandrew interrupts = <0 159 0x4>; 636295011Sandrew status = "disabled"; 637279377Simp }; 638279377Simp 639295011Sandrew i2c2: i2c@ffc06000 { 640295011Sandrew #address-cells = <1>; 641295011Sandrew #size-cells = <0>; 642295011Sandrew compatible = "snps,designware-i2c"; 643295011Sandrew reg = <0xffc06000 0x1000>; 644295011Sandrew clocks = <&l4_sp_clk>; 645295011Sandrew interrupts = <0 160 0x4>; 646295011Sandrew status = "disabled"; 647295011Sandrew }; 648295011Sandrew 649295011Sandrew i2c3: i2c@ffc07000 { 650295011Sandrew #address-cells = <1>; 651295011Sandrew #size-cells = <0>; 652295011Sandrew compatible = "snps,designware-i2c"; 653295011Sandrew reg = <0xffc07000 0x1000>; 654295011Sandrew clocks = <&l4_sp_clk>; 655295011Sandrew interrupts = <0 161 0x4>; 656295011Sandrew status = "disabled"; 657295011Sandrew }; 658295011Sandrew 659279377Simp L2: l2-cache@fffef000 { 660279377Simp compatible = "arm,pl310-cache"; 661279377Simp reg = <0xfffef000 0x1000>; 662279377Simp interrupts = <0 38 0x04>; 663279377Simp cache-unified; 664279377Simp cache-level = <2>; 665279377Simp arm,tag-latency = <1 1 1>; 666279377Simp arm,data-latency = <2 1 1>; 667295011Sandrew prefetch-data = <1>; 668295011Sandrew prefetch-instr = <1>; 669279377Simp }; 670279377Simp 671279377Simp mmc: dwmmc0@ff704000 { 672279377Simp compatible = "altr,socfpga-dw-mshc"; 673279377Simp reg = <0xff704000 0x1000>; 674279377Simp interrupts = <0 139 4>; 675279377Simp fifo-depth = <0x400>; 676279377Simp #address-cells = <1>; 677279377Simp #size-cells = <0>; 678295011Sandrew clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; 679279377Simp clock-names = "biu", "ciu"; 680295011Sandrew status = "disabled"; 681279377Simp }; 682279377Simp 683279377Simp ocram: sram@ffff0000 { 684279377Simp compatible = "mmio-sram"; 685279377Simp reg = <0xffff0000 0x10000>; 686279377Simp }; 687279377Simp 688295011Sandrew rst: rstmgr@ffd05000 { 689295011Sandrew #reset-cells = <1>; 690295011Sandrew compatible = "altr,rst-mgr"; 691295011Sandrew reg = <0xffd05000 0x1000>; 692295011Sandrew altr,modrst-offset = <0x10>; 693295011Sandrew }; 694295011Sandrew 695295011Sandrew scu: snoop-control-unit@fffec000 { 696295011Sandrew compatible = "arm,cortex-a9-scu"; 697295011Sandrew reg = <0xfffec000 0x100>; 698295011Sandrew }; 699295011Sandrew 700295011Sandrew sdr: sdr@ffc25000 { 701295011Sandrew compatible = "syscon"; 702295011Sandrew reg = <0xffc25000 0x1000>; 703295011Sandrew }; 704295011Sandrew 705295011Sandrew sdramedac { 706295011Sandrew compatible = "altr,sdram-edac"; 707295011Sandrew altr,sdr-syscon = <&sdr>; 708295011Sandrew interrupts = <0 39 4>; 709295011Sandrew }; 710295011Sandrew 711279377Simp spi0: spi@fff00000 { 712279377Simp compatible = "snps,dw-apb-ssi"; 713279377Simp #address-cells = <1>; 714279377Simp #size-cells = <0>; 715279377Simp reg = <0xfff00000 0x1000>; 716279377Simp interrupts = <0 154 4>; 717279377Simp num-cs = <4>; 718279377Simp clocks = <&spi_m_clk>; 719279377Simp status = "disabled"; 720279377Simp }; 721279377Simp 722279377Simp spi1: spi@fff01000 { 723279377Simp compatible = "snps,dw-apb-ssi"; 724279377Simp #address-cells = <1>; 725279377Simp #size-cells = <0>; 726279377Simp reg = <0xfff01000 0x1000>; 727295011Sandrew interrupts = <0 155 4>; 728279377Simp num-cs = <4>; 729279377Simp clocks = <&spi_m_clk>; 730279377Simp status = "disabled"; 731279377Simp }; 732279377Simp 733295011Sandrew sysmgr: sysmgr@ffd08000 { 734295011Sandrew compatible = "altr,sys-mgr", "syscon"; 735295011Sandrew reg = <0xffd08000 0x4000>; 736295011Sandrew }; 737295011Sandrew 738279377Simp /* Local timer */ 739279377Simp timer@fffec600 { 740279377Simp compatible = "arm,cortex-a9-twd-timer"; 741279377Simp reg = <0xfffec600 0x100>; 742279377Simp interrupts = <1 13 0xf04>; 743279377Simp clocks = <&mpu_periph_clk>; 744279377Simp }; 745279377Simp 746279377Simp timer0: timer0@ffc08000 { 747279377Simp compatible = "snps,dw-apb-timer"; 748279377Simp interrupts = <0 167 4>; 749279377Simp reg = <0xffc08000 0x1000>; 750279377Simp clocks = <&l4_sp_clk>; 751279377Simp clock-names = "timer"; 752279377Simp }; 753279377Simp 754279377Simp timer1: timer1@ffc09000 { 755279377Simp compatible = "snps,dw-apb-timer"; 756279377Simp interrupts = <0 168 4>; 757279377Simp reg = <0xffc09000 0x1000>; 758279377Simp clocks = <&l4_sp_clk>; 759279377Simp clock-names = "timer"; 760279377Simp }; 761279377Simp 762279377Simp timer2: timer2@ffd00000 { 763279377Simp compatible = "snps,dw-apb-timer"; 764279377Simp interrupts = <0 169 4>; 765279377Simp reg = <0xffd00000 0x1000>; 766279377Simp clocks = <&osc1>; 767279377Simp clock-names = "timer"; 768279377Simp }; 769279377Simp 770279377Simp timer3: timer3@ffd01000 { 771279377Simp compatible = "snps,dw-apb-timer"; 772279377Simp interrupts = <0 170 4>; 773279377Simp reg = <0xffd01000 0x1000>; 774279377Simp clocks = <&osc1>; 775279377Simp clock-names = "timer"; 776279377Simp }; 777279377Simp 778279377Simp uart0: serial0@ffc02000 { 779279377Simp compatible = "snps,dw-apb-uart"; 780279377Simp reg = <0xffc02000 0x1000>; 781279377Simp interrupts = <0 162 4>; 782279377Simp reg-shift = <2>; 783279377Simp reg-io-width = <4>; 784279377Simp clocks = <&l4_sp_clk>; 785295011Sandrew dmas = <&pdma 28>, 786295011Sandrew <&pdma 29>; 787295011Sandrew dma-names = "tx", "rx"; 788279377Simp }; 789279377Simp 790279377Simp uart1: serial1@ffc03000 { 791279377Simp compatible = "snps,dw-apb-uart"; 792279377Simp reg = <0xffc03000 0x1000>; 793279377Simp interrupts = <0 163 4>; 794279377Simp reg-shift = <2>; 795279377Simp reg-io-width = <4>; 796279377Simp clocks = <&l4_sp_clk>; 797295011Sandrew dmas = <&pdma 30>, 798295011Sandrew <&pdma 31>; 799295011Sandrew dma-names = "tx", "rx"; 800279377Simp }; 801279377Simp 802279377Simp usbphy0: usbphy@0 { 803279377Simp #phy-cells = <0>; 804279377Simp compatible = "usb-nop-xceiv"; 805279377Simp status = "okay"; 806279377Simp }; 807279377Simp 808279377Simp usb0: usb@ffb00000 { 809279377Simp compatible = "snps,dwc2"; 810279377Simp reg = <0xffb00000 0xffff>; 811279377Simp interrupts = <0 125 4>; 812279377Simp clocks = <&usb_mp_clk>; 813279377Simp clock-names = "otg"; 814279377Simp phys = <&usbphy0>; 815279377Simp phy-names = "usb2-phy"; 816279377Simp status = "disabled"; 817279377Simp }; 818279377Simp 819279377Simp usb1: usb@ffb40000 { 820279377Simp compatible = "snps,dwc2"; 821279377Simp reg = <0xffb40000 0xffff>; 822279377Simp interrupts = <0 128 4>; 823279377Simp clocks = <&usb_mp_clk>; 824279377Simp clock-names = "otg"; 825279377Simp phys = <&usbphy0>; 826279377Simp phy-names = "usb2-phy"; 827279377Simp status = "disabled"; 828279377Simp }; 829279377Simp 830279377Simp watchdog0: watchdog@ffd02000 { 831279377Simp compatible = "snps,dw-wdt"; 832279377Simp reg = <0xffd02000 0x1000>; 833279377Simp interrupts = <0 171 4>; 834279377Simp clocks = <&osc1>; 835279377Simp status = "disabled"; 836279377Simp }; 837279377Simp 838279377Simp watchdog1: watchdog@ffd03000 { 839279377Simp compatible = "snps,dw-wdt"; 840279377Simp reg = <0xffd03000 0x1000>; 841279377Simp interrupts = <0 172 4>; 842279377Simp clocks = <&osc1>; 843279377Simp status = "disabled"; 844279377Simp }; 845279377Simp }; 846279377Simp}; 847