1279377Simp/* 2279377Simp * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC 3279377Simp * 4279377Simp * Copyright (C) 2014 Atmel, 5279377Simp * 2014 Nicolas Ferre <nicolas.ferre@atmel.com> 6279377Simp * 7279377Simp * This file is dual-licensed: you can use it either under the terms 8279377Simp * of the GPL or the X11 license, at your option. Note that this dual 9279377Simp * licensing only applies to this file, and not this project as a 10279377Simp * whole. 11279377Simp * 12279377Simp * a) This file is free software; you can redistribute it and/or 13279377Simp * modify it under the terms of the GNU General Public License as 14279377Simp * published by the Free Software Foundation; either version 2 of the 15279377Simp * License, or (at your option) any later version. 16279377Simp * 17279377Simp * This file is distributed in the hope that it will be useful, 18279377Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 19279377Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20279377Simp * GNU General Public License for more details. 21279377Simp * 22279377Simp * Or, alternatively, 23279377Simp * 24279377Simp * b) Permission is hereby granted, free of charge, to any person 25279377Simp * obtaining a copy of this software and associated documentation 26279377Simp * files (the "Software"), to deal in the Software without 27279377Simp * restriction, including without limitation the rights to use, 28279377Simp * copy, modify, merge, publish, distribute, sublicense, and/or 29279377Simp * sell copies of the Software, and to permit persons to whom the 30279377Simp * Software is furnished to do so, subject to the following 31279377Simp * conditions: 32279377Simp * 33279377Simp * The above copyright notice and this permission notice shall be 34279377Simp * included in all copies or substantial portions of the Software. 35279377Simp * 36279377Simp * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 37279377Simp * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 38279377Simp * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 39279377Simp * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 40279377Simp * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 41279377Simp * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 42279377Simp * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 43279377Simp * OTHER DEALINGS IN THE SOFTWARE. 44279377Simp */ 45279377Simp 46279377Simp#include "skeleton.dtsi" 47279377Simp#include <dt-bindings/clock/at91.h> 48279377Simp#include <dt-bindings/dma/at91.h> 49279377Simp#include <dt-bindings/pinctrl/at91.h> 50279377Simp#include <dt-bindings/interrupt-controller/irq.h> 51279377Simp#include <dt-bindings/gpio/gpio.h> 52279377Simp 53279377Simp/ { 54279377Simp model = "Atmel SAMA5D4 family SoC"; 55279377Simp compatible = "atmel,sama5d4"; 56279377Simp interrupt-parent = <&aic>; 57279377Simp 58279377Simp aliases { 59279377Simp serial0 = &usart3; 60279377Simp serial1 = &usart4; 61279377Simp serial2 = &usart2; 62295436Sandrew serial3 = &usart0; 63295436Sandrew serial4 = &usart1; 64295436Sandrew serial5 = &uart0; 65295436Sandrew serial6 = &uart1; 66279377Simp gpio0 = &pioA; 67279377Simp gpio1 = &pioB; 68279377Simp gpio2 = &pioC; 69279377Simp gpio3 = &pioD; 70279377Simp gpio4 = &pioE; 71295436Sandrew pwm0 = &pwm0; 72295436Sandrew ssc0 = &ssc0; 73295436Sandrew ssc1 = &ssc1; 74279377Simp tcb0 = &tcb0; 75279377Simp tcb1 = &tcb1; 76295436Sandrew i2c0 = &i2c0; 77295436Sandrew i2c1 = &i2c1; 78279377Simp i2c2 = &i2c2; 79279377Simp }; 80279377Simp cpus { 81279377Simp #address-cells = <1>; 82279377Simp #size-cells = <0>; 83279377Simp 84279377Simp cpu@0 { 85279377Simp device_type = "cpu"; 86279377Simp compatible = "arm,cortex-a5"; 87279377Simp reg = <0>; 88279377Simp next-level-cache = <&L2>; 89279377Simp }; 90279377Simp }; 91279377Simp 92279377Simp memory { 93279377Simp reg = <0x20000000 0x20000000>; 94279377Simp }; 95279377Simp 96279377Simp clocks { 97279377Simp slow_xtal: slow_xtal { 98279377Simp compatible = "fixed-clock"; 99279377Simp #clock-cells = <0>; 100279377Simp clock-frequency = <0>; 101279377Simp }; 102279377Simp 103279377Simp main_xtal: main_xtal { 104279377Simp compatible = "fixed-clock"; 105279377Simp #clock-cells = <0>; 106279377Simp clock-frequency = <0>; 107279377Simp }; 108279377Simp 109279377Simp adc_op_clk: adc_op_clk{ 110279377Simp compatible = "fixed-clock"; 111279377Simp #clock-cells = <0>; 112279377Simp clock-frequency = <1000000>; 113279377Simp }; 114279377Simp }; 115279377Simp 116279377Simp ns_sram: sram@00210000 { 117279377Simp compatible = "mmio-sram"; 118279377Simp reg = <0x00210000 0x10000>; 119279377Simp }; 120279377Simp 121279377Simp ahb { 122279377Simp compatible = "simple-bus"; 123279377Simp #address-cells = <1>; 124279377Simp #size-cells = <1>; 125279377Simp ranges; 126279377Simp 127279377Simp usb0: gadget@00400000 { 128279377Simp #address-cells = <1>; 129279377Simp #size-cells = <0>; 130295436Sandrew compatible = "atmel,sama5d3-udc"; 131279377Simp reg = <0x00400000 0x100000 132279377Simp 0xfc02c000 0x4000>; 133279377Simp interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; 134279377Simp clocks = <&udphs_clk>, <&utmi>; 135279377Simp clock-names = "pclk", "hclk"; 136279377Simp status = "disabled"; 137279377Simp 138279377Simp ep0 { 139279377Simp reg = <0>; 140279377Simp atmel,fifo-size = <64>; 141279377Simp atmel,nb-banks = <1>; 142279377Simp }; 143279377Simp 144279377Simp ep1 { 145279377Simp reg = <1>; 146279377Simp atmel,fifo-size = <1024>; 147279377Simp atmel,nb-banks = <3>; 148279377Simp atmel,can-dma; 149279377Simp atmel,can-isoc; 150279377Simp }; 151279377Simp 152279377Simp ep2 { 153279377Simp reg = <2>; 154279377Simp atmel,fifo-size = <1024>; 155279377Simp atmel,nb-banks = <3>; 156279377Simp atmel,can-dma; 157279377Simp atmel,can-isoc; 158279377Simp }; 159279377Simp 160279377Simp ep3 { 161279377Simp reg = <3>; 162279377Simp atmel,fifo-size = <1024>; 163279377Simp atmel,nb-banks = <2>; 164279377Simp atmel,can-dma; 165279377Simp atmel,can-isoc; 166279377Simp }; 167279377Simp 168279377Simp ep4 { 169279377Simp reg = <4>; 170279377Simp atmel,fifo-size = <1024>; 171279377Simp atmel,nb-banks = <2>; 172279377Simp atmel,can-dma; 173279377Simp atmel,can-isoc; 174279377Simp }; 175279377Simp 176279377Simp ep5 { 177279377Simp reg = <5>; 178279377Simp atmel,fifo-size = <1024>; 179279377Simp atmel,nb-banks = <2>; 180279377Simp atmel,can-dma; 181279377Simp atmel,can-isoc; 182279377Simp }; 183279377Simp 184279377Simp ep6 { 185279377Simp reg = <6>; 186279377Simp atmel,fifo-size = <1024>; 187279377Simp atmel,nb-banks = <2>; 188279377Simp atmel,can-dma; 189279377Simp atmel,can-isoc; 190279377Simp }; 191279377Simp 192279377Simp ep7 { 193279377Simp reg = <7>; 194279377Simp atmel,fifo-size = <1024>; 195279377Simp atmel,nb-banks = <2>; 196279377Simp atmel,can-dma; 197279377Simp atmel,can-isoc; 198279377Simp }; 199279377Simp 200279377Simp ep8 { 201279377Simp reg = <8>; 202279377Simp atmel,fifo-size = <1024>; 203279377Simp atmel,nb-banks = <2>; 204279377Simp atmel,can-isoc; 205279377Simp }; 206279377Simp 207279377Simp ep9 { 208279377Simp reg = <9>; 209279377Simp atmel,fifo-size = <1024>; 210279377Simp atmel,nb-banks = <2>; 211279377Simp atmel,can-isoc; 212279377Simp }; 213279377Simp 214279377Simp ep10 { 215279377Simp reg = <10>; 216279377Simp atmel,fifo-size = <1024>; 217279377Simp atmel,nb-banks = <2>; 218279377Simp atmel,can-isoc; 219279377Simp }; 220279377Simp 221279377Simp ep11 { 222279377Simp reg = <11>; 223279377Simp atmel,fifo-size = <1024>; 224279377Simp atmel,nb-banks = <2>; 225279377Simp atmel,can-isoc; 226279377Simp }; 227279377Simp 228279377Simp ep12 { 229279377Simp reg = <12>; 230279377Simp atmel,fifo-size = <1024>; 231279377Simp atmel,nb-banks = <2>; 232279377Simp atmel,can-isoc; 233279377Simp }; 234279377Simp 235279377Simp ep13 { 236279377Simp reg = <13>; 237279377Simp atmel,fifo-size = <1024>; 238279377Simp atmel,nb-banks = <2>; 239279377Simp atmel,can-isoc; 240279377Simp }; 241279377Simp 242279377Simp ep14 { 243279377Simp reg = <14>; 244279377Simp atmel,fifo-size = <1024>; 245279377Simp atmel,nb-banks = <2>; 246279377Simp atmel,can-isoc; 247279377Simp }; 248279377Simp 249279377Simp ep15 { 250279377Simp reg = <15>; 251279377Simp atmel,fifo-size = <1024>; 252279377Simp atmel,nb-banks = <2>; 253279377Simp atmel,can-isoc; 254279377Simp }; 255279377Simp }; 256279377Simp 257279377Simp usb1: ohci@00500000 { 258279377Simp compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 259279377Simp reg = <0x00500000 0x100000>; 260279377Simp interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; 261295436Sandrew clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; 262295436Sandrew clock-names = "ohci_clk", "hclk", "uhpck"; 263279377Simp status = "disabled"; 264279377Simp }; 265279377Simp 266279377Simp usb2: ehci@00600000 { 267279377Simp compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 268279377Simp reg = <0x00600000 0x100000>; 269279377Simp interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; 270295436Sandrew clocks = <&utmi>, <&uhphs_clk>; 271295436Sandrew clock-names = "usb_clk", "ehci_clk"; 272279377Simp status = "disabled"; 273279377Simp }; 274279377Simp 275279377Simp L2: cache-controller@00a00000 { 276279377Simp compatible = "arm,pl310-cache"; 277279377Simp reg = <0x00a00000 0x1000>; 278279377Simp interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; 279279377Simp cache-unified; 280279377Simp cache-level = <2>; 281279377Simp }; 282279377Simp 283279377Simp nand0: nand@80000000 { 284279377Simp compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand"; 285279377Simp #address-cells = <1>; 286279377Simp #size-cells = <1>; 287279377Simp ranges; 288279377Simp reg = < 0x80000000 0x08000000 /* EBI CS3 */ 289279377Simp 0xfc05c070 0x00000490 /* SMC PMECC regs */ 290279377Simp 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */ 291279377Simp >; 292279377Simp interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; 293279377Simp atmel,nand-addr-offset = <21>; 294279377Simp atmel,nand-cmd-offset = <22>; 295279377Simp atmel,nand-has-dma; 296279377Simp pinctrl-names = "default"; 297279377Simp pinctrl-0 = <&pinctrl_nand>; 298279377Simp status = "disabled"; 299279377Simp 300279377Simp nfc@90000000 { 301279377Simp compatible = "atmel,sama5d3-nfc"; 302279377Simp #address-cells = <1>; 303279377Simp #size-cells = <1>; 304279377Simp reg = < 305295436Sandrew 0x90000000 0x08000000 /* NFC Command Registers */ 306279377Simp 0xfc05c000 0x00000070 /* NFC HSMC regs */ 307279377Simp 0x00100000 0x00100000 /* NFC SRAM banks */ 308279377Simp >; 309279377Simp clocks = <&hsmc_clk>; 310279377Simp atmel,write-by-sram; 311279377Simp }; 312279377Simp }; 313279377Simp 314279377Simp apb { 315279377Simp compatible = "simple-bus"; 316279377Simp #address-cells = <1>; 317279377Simp #size-cells = <1>; 318279377Simp ranges; 319279377Simp 320295436Sandrew hlcdc: hlcdc@f0000000 { 321295436Sandrew compatible = "atmel,sama5d4-hlcdc"; 322295436Sandrew reg = <0xf0000000 0x4000>; 323295436Sandrew interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; 324295436Sandrew clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; 325295436Sandrew clock-names = "periph_clk","sys_clk", "slow_clk"; 326295436Sandrew status = "disabled"; 327295436Sandrew 328295436Sandrew hlcdc-display-controller { 329295436Sandrew compatible = "atmel,hlcdc-display-controller"; 330295436Sandrew #address-cells = <1>; 331295436Sandrew #size-cells = <0>; 332295436Sandrew 333295436Sandrew port@0 { 334295436Sandrew #address-cells = <1>; 335295436Sandrew #size-cells = <0>; 336295436Sandrew reg = <0>; 337295436Sandrew }; 338295436Sandrew }; 339295436Sandrew 340295436Sandrew hlcdc_pwm: hlcdc-pwm { 341295436Sandrew compatible = "atmel,hlcdc-pwm"; 342295436Sandrew pinctrl-names = "default"; 343295436Sandrew pinctrl-0 = <&pinctrl_lcd_pwm>; 344295436Sandrew #pwm-cells = <3>; 345295436Sandrew }; 346295436Sandrew }; 347295436Sandrew 348279377Simp dma1: dma-controller@f0004000 { 349279377Simp compatible = "atmel,sama5d4-dma"; 350279377Simp reg = <0xf0004000 0x200>; 351279377Simp interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; 352279377Simp #dma-cells = <1>; 353279377Simp clocks = <&dma1_clk>; 354279377Simp clock-names = "dma_clk"; 355279377Simp }; 356279377Simp 357295436Sandrew isi: isi@f0008000 { 358295436Sandrew compatible = "atmel,at91sam9g45-isi"; 359295436Sandrew reg = <0xf0008000 0x4000>; 360295436Sandrew interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>; 361295436Sandrew pinctrl-names = "default"; 362295436Sandrew pinctrl-0 = <&pinctrl_isi_data_0_7>; 363295436Sandrew clocks = <&isi_clk>; 364295436Sandrew clock-names = "isi_clk"; 365295436Sandrew status = "disabled"; 366295436Sandrew port { 367295436Sandrew #address-cells = <1>; 368295436Sandrew #size-cells = <0>; 369295436Sandrew }; 370295436Sandrew }; 371295436Sandrew 372279377Simp ramc0: ramc@f0010000 { 373279377Simp compatible = "atmel,sama5d3-ddramc"; 374279377Simp reg = <0xf0010000 0x200>; 375279377Simp clocks = <&ddrck>, <&mpddr_clk>; 376279377Simp clock-names = "ddrck", "mpddr"; 377279377Simp }; 378279377Simp 379279377Simp dma0: dma-controller@f0014000 { 380279377Simp compatible = "atmel,sama5d4-dma"; 381279377Simp reg = <0xf0014000 0x200>; 382279377Simp interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; 383279377Simp #dma-cells = <1>; 384279377Simp clocks = <&dma0_clk>; 385279377Simp clock-names = "dma_clk"; 386279377Simp }; 387279377Simp 388279377Simp pmc: pmc@f0018000 { 389295436Sandrew compatible = "atmel,sama5d3-pmc", "syscon"; 390279377Simp reg = <0xf0018000 0x120>; 391279377Simp interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 392279377Simp interrupt-controller; 393279377Simp #address-cells = <1>; 394279377Simp #size-cells = <0>; 395279377Simp #interrupt-cells = <1>; 396279377Simp 397279377Simp main_rc_osc: main_rc_osc { 398279377Simp compatible = "atmel,at91sam9x5-clk-main-rc-osc"; 399279377Simp #clock-cells = <0>; 400279377Simp interrupt-parent = <&pmc>; 401279377Simp interrupts = <AT91_PMC_MOSCRCS>; 402279377Simp clock-frequency = <12000000>; 403279377Simp clock-accuracy = <100000000>; 404279377Simp }; 405279377Simp 406279377Simp main_osc: main_osc { 407279377Simp compatible = "atmel,at91rm9200-clk-main-osc"; 408279377Simp #clock-cells = <0>; 409279377Simp interrupt-parent = <&pmc>; 410279377Simp interrupts = <AT91_PMC_MOSCS>; 411279377Simp clocks = <&main_xtal>; 412279377Simp }; 413279377Simp 414279377Simp main: mainck { 415279377Simp compatible = "atmel,at91sam9x5-clk-main"; 416279377Simp #clock-cells = <0>; 417279377Simp interrupt-parent = <&pmc>; 418279377Simp interrupts = <AT91_PMC_MOSCSELS>; 419279377Simp clocks = <&main_rc_osc &main_osc>; 420279377Simp }; 421279377Simp 422279377Simp plla: pllack { 423279377Simp compatible = "atmel,sama5d3-clk-pll"; 424279377Simp #clock-cells = <0>; 425279377Simp interrupt-parent = <&pmc>; 426279377Simp interrupts = <AT91_PMC_LOCKA>; 427279377Simp clocks = <&main>; 428279377Simp reg = <0>; 429279377Simp atmel,clk-input-range = <12000000 12000000>; 430279377Simp #atmel,pll-clk-output-range-cells = <4>; 431279377Simp atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; 432279377Simp }; 433279377Simp 434279377Simp plladiv: plladivck { 435279377Simp compatible = "atmel,at91sam9x5-clk-plldiv"; 436279377Simp #clock-cells = <0>; 437279377Simp clocks = <&plla>; 438279377Simp }; 439279377Simp 440279377Simp utmi: utmick { 441279377Simp compatible = "atmel,at91sam9x5-clk-utmi"; 442279377Simp #clock-cells = <0>; 443279377Simp interrupt-parent = <&pmc>; 444279377Simp interrupts = <AT91_PMC_LOCKU>; 445279377Simp clocks = <&main>; 446279377Simp }; 447279377Simp 448279377Simp mck: masterck { 449279377Simp compatible = "atmel,at91sam9x5-clk-master"; 450279377Simp #clock-cells = <0>; 451279377Simp interrupt-parent = <&pmc>; 452279377Simp interrupts = <AT91_PMC_MCKRDY>; 453279377Simp clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; 454295436Sandrew atmel,clk-output-range = <125000000 200000000>; 455279377Simp atmel,clk-divisors = <1 2 4 3>; 456279377Simp }; 457279377Simp 458279377Simp h32ck: h32mxck { 459279377Simp #clock-cells = <0>; 460279377Simp compatible = "atmel,sama5d4-clk-h32mx"; 461279377Simp clocks = <&mck>; 462279377Simp }; 463279377Simp 464279377Simp usb: usbck { 465279377Simp compatible = "atmel,at91sam9x5-clk-usb"; 466279377Simp #clock-cells = <0>; 467279377Simp clocks = <&plladiv>, <&utmi>; 468279377Simp }; 469279377Simp 470279377Simp prog: progck { 471279377Simp compatible = "atmel,at91sam9x5-clk-programmable"; 472279377Simp #address-cells = <1>; 473279377Simp #size-cells = <0>; 474279377Simp interrupt-parent = <&pmc>; 475279377Simp clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; 476279377Simp 477279377Simp prog0: prog0 { 478279377Simp #clock-cells = <0>; 479279377Simp reg = <0>; 480279377Simp interrupts = <AT91_PMC_PCKRDY(0)>; 481279377Simp }; 482279377Simp 483279377Simp prog1: prog1 { 484279377Simp #clock-cells = <0>; 485279377Simp reg = <1>; 486279377Simp interrupts = <AT91_PMC_PCKRDY(1)>; 487279377Simp }; 488279377Simp 489279377Simp prog2: prog2 { 490279377Simp #clock-cells = <0>; 491279377Simp reg = <2>; 492279377Simp interrupts = <AT91_PMC_PCKRDY(2)>; 493279377Simp }; 494279377Simp }; 495279377Simp 496279377Simp smd: smdclk { 497279377Simp compatible = "atmel,at91sam9x5-clk-smd"; 498279377Simp #clock-cells = <0>; 499279377Simp clocks = <&plladiv>, <&utmi>; 500279377Simp }; 501279377Simp 502279377Simp systemck { 503279377Simp compatible = "atmel,at91rm9200-clk-system"; 504279377Simp #address-cells = <1>; 505279377Simp #size-cells = <0>; 506279377Simp 507279377Simp ddrck: ddrck { 508279377Simp #clock-cells = <0>; 509279377Simp reg = <2>; 510279377Simp clocks = <&mck>; 511279377Simp }; 512279377Simp 513279377Simp lcdck: lcdck { 514279377Simp #clock-cells = <0>; 515295436Sandrew reg = <3>; 516295436Sandrew clocks = <&mck>; 517279377Simp }; 518279377Simp 519279377Simp smdck: smdck { 520279377Simp #clock-cells = <0>; 521279377Simp reg = <4>; 522279377Simp clocks = <&smd>; 523279377Simp }; 524279377Simp 525279377Simp uhpck: uhpck { 526279377Simp #clock-cells = <0>; 527279377Simp reg = <6>; 528279377Simp clocks = <&usb>; 529279377Simp }; 530279377Simp 531279377Simp udpck: udpck { 532279377Simp #clock-cells = <0>; 533279377Simp reg = <7>; 534279377Simp clocks = <&usb>; 535279377Simp }; 536279377Simp 537279377Simp pck0: pck0 { 538279377Simp #clock-cells = <0>; 539279377Simp reg = <8>; 540279377Simp clocks = <&prog0>; 541279377Simp }; 542279377Simp 543279377Simp pck1: pck1 { 544279377Simp #clock-cells = <0>; 545279377Simp reg = <9>; 546279377Simp clocks = <&prog1>; 547279377Simp }; 548279377Simp 549279377Simp pck2: pck2 { 550279377Simp #clock-cells = <0>; 551279377Simp reg = <10>; 552279377Simp clocks = <&prog2>; 553279377Simp }; 554279377Simp }; 555279377Simp 556279377Simp periph32ck { 557279377Simp compatible = "atmel,at91sam9x5-clk-peripheral"; 558279377Simp #address-cells = <1>; 559279377Simp #size-cells = <0>; 560279377Simp clocks = <&h32ck>; 561279377Simp 562279377Simp pioD_clk: pioD_clk { 563279377Simp #clock-cells = <0>; 564279377Simp reg = <5>; 565279377Simp }; 566279377Simp 567279377Simp usart0_clk: usart0_clk { 568279377Simp #clock-cells = <0>; 569279377Simp reg = <6>; 570279377Simp }; 571279377Simp 572279377Simp usart1_clk: usart1_clk { 573279377Simp #clock-cells = <0>; 574279377Simp reg = <7>; 575279377Simp }; 576279377Simp 577279377Simp icm_clk: icm_clk { 578279377Simp #clock-cells = <0>; 579279377Simp reg = <9>; 580279377Simp }; 581279377Simp 582279377Simp aes_clk: aes_clk { 583279377Simp #clock-cells = <0>; 584279377Simp reg = <12>; 585279377Simp }; 586279377Simp 587279377Simp tdes_clk: tdes_clk { 588279377Simp #clock-cells = <0>; 589279377Simp reg = <14>; 590279377Simp }; 591279377Simp 592279377Simp sha_clk: sha_clk { 593279377Simp #clock-cells = <0>; 594279377Simp reg = <15>; 595279377Simp }; 596279377Simp 597279377Simp matrix1_clk: matrix1_clk { 598279377Simp #clock-cells = <0>; 599279377Simp reg = <17>; 600279377Simp }; 601279377Simp 602279377Simp hsmc_clk: hsmc_clk { 603279377Simp #clock-cells = <0>; 604279377Simp reg = <22>; 605279377Simp }; 606279377Simp 607279377Simp pioA_clk: pioA_clk { 608279377Simp #clock-cells = <0>; 609279377Simp reg = <23>; 610279377Simp }; 611279377Simp 612279377Simp pioB_clk: pioB_clk { 613279377Simp #clock-cells = <0>; 614279377Simp reg = <24>; 615279377Simp }; 616279377Simp 617279377Simp pioC_clk: pioC_clk { 618279377Simp #clock-cells = <0>; 619279377Simp reg = <25>; 620279377Simp }; 621279377Simp 622279377Simp pioE_clk: pioE_clk { 623279377Simp #clock-cells = <0>; 624279377Simp reg = <26>; 625279377Simp }; 626279377Simp 627279377Simp uart0_clk: uart0_clk { 628279377Simp #clock-cells = <0>; 629279377Simp reg = <27>; 630279377Simp }; 631279377Simp 632279377Simp uart1_clk: uart1_clk { 633279377Simp #clock-cells = <0>; 634279377Simp reg = <28>; 635279377Simp }; 636279377Simp 637279377Simp usart2_clk: usart2_clk { 638279377Simp #clock-cells = <0>; 639279377Simp reg = <29>; 640279377Simp }; 641279377Simp 642279377Simp usart3_clk: usart3_clk { 643279377Simp #clock-cells = <0>; 644279377Simp reg = <30>; 645279377Simp }; 646279377Simp 647279377Simp usart4_clk: usart4_clk { 648279377Simp #clock-cells = <0>; 649279377Simp reg = <31>; 650279377Simp }; 651279377Simp 652279377Simp twi0_clk: twi0_clk { 653279377Simp reg = <32>; 654279377Simp #clock-cells = <0>; 655279377Simp }; 656279377Simp 657279377Simp twi1_clk: twi1_clk { 658279377Simp #clock-cells = <0>; 659279377Simp reg = <33>; 660279377Simp }; 661279377Simp 662279377Simp twi2_clk: twi2_clk { 663279377Simp #clock-cells = <0>; 664279377Simp reg = <34>; 665279377Simp }; 666279377Simp 667279377Simp mci0_clk: mci0_clk { 668279377Simp #clock-cells = <0>; 669279377Simp reg = <35>; 670279377Simp }; 671279377Simp 672279377Simp mci1_clk: mci1_clk { 673279377Simp #clock-cells = <0>; 674279377Simp reg = <36>; 675279377Simp }; 676279377Simp 677279377Simp spi0_clk: spi0_clk { 678279377Simp #clock-cells = <0>; 679279377Simp reg = <37>; 680279377Simp }; 681279377Simp 682279377Simp spi1_clk: spi1_clk { 683279377Simp #clock-cells = <0>; 684279377Simp reg = <38>; 685279377Simp }; 686279377Simp 687279377Simp spi2_clk: spi2_clk { 688279377Simp #clock-cells = <0>; 689279377Simp reg = <39>; 690279377Simp }; 691279377Simp 692279377Simp tcb0_clk: tcb0_clk { 693279377Simp #clock-cells = <0>; 694279377Simp reg = <40>; 695279377Simp }; 696279377Simp 697279377Simp tcb1_clk: tcb1_clk { 698279377Simp #clock-cells = <0>; 699279377Simp reg = <41>; 700279377Simp }; 701279377Simp 702279377Simp tcb2_clk: tcb2_clk { 703279377Simp #clock-cells = <0>; 704279377Simp reg = <42>; 705279377Simp }; 706279377Simp 707279377Simp pwm_clk: pwm_clk { 708279377Simp #clock-cells = <0>; 709279377Simp reg = <43>; 710279377Simp }; 711279377Simp 712279377Simp adc_clk: adc_clk { 713279377Simp #clock-cells = <0>; 714279377Simp reg = <44>; 715279377Simp }; 716279377Simp 717279377Simp dbgu_clk: dbgu_clk { 718279377Simp #clock-cells = <0>; 719279377Simp reg = <45>; 720279377Simp }; 721279377Simp 722279377Simp uhphs_clk: uhphs_clk { 723279377Simp #clock-cells = <0>; 724279377Simp reg = <46>; 725279377Simp }; 726279377Simp 727279377Simp udphs_clk: udphs_clk { 728279377Simp #clock-cells = <0>; 729279377Simp reg = <47>; 730279377Simp }; 731279377Simp 732279377Simp ssc0_clk: ssc0_clk { 733279377Simp #clock-cells = <0>; 734279377Simp reg = <48>; 735279377Simp }; 736279377Simp 737279377Simp ssc1_clk: ssc1_clk { 738279377Simp #clock-cells = <0>; 739279377Simp reg = <49>; 740279377Simp }; 741279377Simp 742279377Simp trng_clk: trng_clk { 743279377Simp #clock-cells = <0>; 744279377Simp reg = <53>; 745279377Simp }; 746279377Simp 747279377Simp macb0_clk: macb0_clk { 748279377Simp #clock-cells = <0>; 749279377Simp reg = <54>; 750279377Simp }; 751279377Simp 752279377Simp macb1_clk: macb1_clk { 753279377Simp #clock-cells = <0>; 754279377Simp reg = <55>; 755279377Simp }; 756279377Simp 757279377Simp fuse_clk: fuse_clk { 758279377Simp #clock-cells = <0>; 759279377Simp reg = <57>; 760279377Simp }; 761279377Simp 762279377Simp securam_clk: securam_clk { 763279377Simp #clock-cells = <0>; 764279377Simp reg = <59>; 765279377Simp }; 766279377Simp 767279377Simp smd_clk: smd_clk { 768279377Simp #clock-cells = <0>; 769279377Simp reg = <61>; 770279377Simp }; 771279377Simp 772279377Simp twi3_clk: twi3_clk { 773279377Simp #clock-cells = <0>; 774279377Simp reg = <62>; 775279377Simp }; 776279377Simp 777279377Simp catb_clk: catb_clk { 778279377Simp #clock-cells = <0>; 779279377Simp reg = <63>; 780279377Simp }; 781279377Simp }; 782279377Simp 783279377Simp periph64ck { 784279377Simp compatible = "atmel,at91sam9x5-clk-peripheral"; 785279377Simp #address-cells = <1>; 786279377Simp #size-cells = <0>; 787279377Simp clocks = <&mck>; 788279377Simp 789279377Simp dma0_clk: dma0_clk { 790279377Simp #clock-cells = <0>; 791279377Simp reg = <8>; 792279377Simp }; 793279377Simp 794279377Simp cpkcc_clk: cpkcc_clk { 795279377Simp #clock-cells = <0>; 796279377Simp reg = <10>; 797279377Simp }; 798279377Simp 799279377Simp aesb_clk: aesb_clk { 800279377Simp #clock-cells = <0>; 801279377Simp reg = <13>; 802279377Simp }; 803279377Simp 804279377Simp mpddr_clk: mpddr_clk { 805279377Simp #clock-cells = <0>; 806279377Simp reg = <16>; 807279377Simp }; 808279377Simp 809279377Simp matrix0_clk: matrix0_clk { 810279377Simp #clock-cells = <0>; 811279377Simp reg = <18>; 812279377Simp }; 813279377Simp 814279377Simp vdec_clk: vdec_clk { 815279377Simp #clock-cells = <0>; 816279377Simp reg = <19>; 817279377Simp }; 818279377Simp 819279377Simp dma1_clk: dma1_clk { 820279377Simp #clock-cells = <0>; 821279377Simp reg = <50>; 822279377Simp }; 823279377Simp 824295436Sandrew lcdc_clk: lcdc_clk { 825279377Simp #clock-cells = <0>; 826279377Simp reg = <51>; 827279377Simp }; 828279377Simp 829279377Simp isi_clk: isi_clk { 830279377Simp #clock-cells = <0>; 831279377Simp reg = <52>; 832279377Simp }; 833279377Simp }; 834279377Simp }; 835279377Simp 836279377Simp mmc0: mmc@f8000000 { 837279377Simp compatible = "atmel,hsmci"; 838279377Simp reg = <0xf8000000 0x600>; 839279377Simp interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 840279377Simp dmas = <&dma1 841279377Simp (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 842279377Simp | AT91_XDMAC_DT_PERID(0))>; 843279377Simp dma-names = "rxtx"; 844279377Simp pinctrl-names = "default"; 845279377Simp pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; 846279377Simp status = "disabled"; 847279377Simp #address-cells = <1>; 848279377Simp #size-cells = <0>; 849279377Simp clocks = <&mci0_clk>; 850279377Simp clock-names = "mci_clk"; 851279377Simp }; 852279377Simp 853295436Sandrew uart0: serial@f8004000 { 854295436Sandrew compatible = "atmel,at91sam9260-usart"; 855295436Sandrew reg = <0xf8004000 0x100>; 856295436Sandrew interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>; 857295436Sandrew dmas = <&dma1 858295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 859295436Sandrew | AT91_XDMAC_DT_PERID(22))>, 860295436Sandrew <&dma1 861295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 862295436Sandrew | AT91_XDMAC_DT_PERID(23))>; 863295436Sandrew dma-names = "tx", "rx"; 864295436Sandrew pinctrl-names = "default"; 865295436Sandrew pinctrl-0 = <&pinctrl_uart0>; 866295436Sandrew clocks = <&uart0_clk>; 867295436Sandrew clock-names = "usart"; 868295436Sandrew status = "disabled"; 869295436Sandrew }; 870295436Sandrew 871295436Sandrew ssc0: ssc@f8008000 { 872295436Sandrew compatible = "atmel,at91sam9g45-ssc"; 873295436Sandrew reg = <0xf8008000 0x4000>; 874295436Sandrew interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; 875295436Sandrew pinctrl-names = "default"; 876295436Sandrew pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 877295436Sandrew dmas = <&dma1 878295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 879295436Sandrew | AT91_XDMAC_DT_PERID(26))>, 880295436Sandrew <&dma1 881295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 882295436Sandrew | AT91_XDMAC_DT_PERID(27))>; 883295436Sandrew dma-names = "tx", "rx"; 884295436Sandrew clocks = <&ssc0_clk>; 885295436Sandrew clock-names = "pclk"; 886295436Sandrew status = "disabled"; 887295436Sandrew }; 888295436Sandrew 889295436Sandrew pwm0: pwm@f800c000 { 890295436Sandrew compatible = "atmel,sama5d3-pwm"; 891295436Sandrew reg = <0xf800c000 0x300>; 892295436Sandrew interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 893295436Sandrew #pwm-cells = <3>; 894295436Sandrew clocks = <&pwm_clk>; 895295436Sandrew status = "disabled"; 896295436Sandrew }; 897295436Sandrew 898279377Simp spi0: spi@f8010000 { 899279377Simp #address-cells = <1>; 900279377Simp #size-cells = <0>; 901279377Simp compatible = "atmel,at91rm9200-spi"; 902279377Simp reg = <0xf8010000 0x100>; 903279377Simp interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; 904279377Simp dmas = <&dma1 905279377Simp (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 906279377Simp | AT91_XDMAC_DT_PERID(10))>, 907279377Simp <&dma1 908279377Simp (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 909279377Simp | AT91_XDMAC_DT_PERID(11))>; 910279377Simp dma-names = "tx", "rx"; 911279377Simp pinctrl-names = "default"; 912279377Simp pinctrl-0 = <&pinctrl_spi0>; 913279377Simp clocks = <&spi0_clk>; 914279377Simp clock-names = "spi_clk"; 915279377Simp status = "disabled"; 916279377Simp }; 917279377Simp 918279377Simp i2c0: i2c@f8014000 { 919295436Sandrew compatible = "atmel,sama5d4-i2c"; 920279377Simp reg = <0xf8014000 0x4000>; 921279377Simp interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; 922279377Simp dmas = <&dma1 923279377Simp (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 924279377Simp | AT91_XDMAC_DT_PERID(2))>, 925279377Simp <&dma1 926279377Simp (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 927279377Simp | AT91_XDMAC_DT_PERID(3))>; 928279377Simp dma-names = "tx", "rx"; 929279377Simp pinctrl-names = "default"; 930279377Simp pinctrl-0 = <&pinctrl_i2c0>; 931279377Simp #address-cells = <1>; 932279377Simp #size-cells = <0>; 933279377Simp clocks = <&twi0_clk>; 934279377Simp status = "disabled"; 935279377Simp }; 936279377Simp 937295436Sandrew i2c1: i2c@f8018000 { 938295436Sandrew compatible = "atmel,sama5d4-i2c"; 939295436Sandrew reg = <0xf8018000 0x4000>; 940295436Sandrew interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; 941295436Sandrew dmas = <&dma1 942295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 943295436Sandrew | AT91_XDMAC_DT_PERID(4))>, 944295436Sandrew <&dma1 945295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 946295436Sandrew | AT91_XDMAC_DT_PERID(5))>; 947295436Sandrew dma-names = "tx", "rx"; 948295436Sandrew pinctrl-names = "default"; 949295436Sandrew pinctrl-0 = <&pinctrl_i2c1>; 950295436Sandrew #address-cells = <1>; 951295436Sandrew #size-cells = <0>; 952295436Sandrew clocks = <&twi1_clk>; 953295436Sandrew status = "disabled"; 954295436Sandrew }; 955295436Sandrew 956279377Simp tcb0: timer@f801c000 { 957279377Simp compatible = "atmel,at91sam9x5-tcb"; 958279377Simp reg = <0xf801c000 0x100>; 959279377Simp interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; 960295436Sandrew clocks = <&tcb0_clk>, <&clk32k>; 961295436Sandrew clock-names = "t0_clk", "slow_clk"; 962279377Simp }; 963279377Simp 964279377Simp macb0: ethernet@f8020000 { 965279377Simp compatible = "atmel,sama5d4-gem"; 966279377Simp reg = <0xf8020000 0x100>; 967279377Simp interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; 968279377Simp pinctrl-names = "default"; 969279377Simp pinctrl-0 = <&pinctrl_macb0_rmii>; 970295436Sandrew #address-cells = <1>; 971295436Sandrew #size-cells = <0>; 972279377Simp clocks = <&macb0_clk>, <&macb0_clk>; 973279377Simp clock-names = "hclk", "pclk"; 974279377Simp status = "disabled"; 975279377Simp }; 976279377Simp 977279377Simp i2c2: i2c@f8024000 { 978295436Sandrew compatible = "atmel,sama5d4-i2c"; 979279377Simp reg = <0xf8024000 0x4000>; 980279377Simp interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; 981279377Simp dmas = <&dma1 982279377Simp (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 983279377Simp | AT91_XDMAC_DT_PERID(6))>, 984279377Simp <&dma1 985279377Simp (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 986279377Simp | AT91_XDMAC_DT_PERID(7))>; 987279377Simp dma-names = "tx", "rx"; 988279377Simp pinctrl-names = "default"; 989279377Simp pinctrl-0 = <&pinctrl_i2c2>; 990279377Simp #address-cells = <1>; 991279377Simp #size-cells = <0>; 992279377Simp clocks = <&twi2_clk>; 993279377Simp status = "disabled"; 994279377Simp }; 995279377Simp 996279377Simp sfr: sfr@f8028000 { 997279377Simp compatible = "atmel,sama5d4-sfr", "syscon"; 998279377Simp reg = <0xf8028000 0x60>; 999279377Simp }; 1000279377Simp 1001295436Sandrew usart0: serial@f802c000 { 1002295436Sandrew compatible = "atmel,at91sam9260-usart"; 1003295436Sandrew reg = <0xf802c000 0x100>; 1004295436Sandrew interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 1005295436Sandrew dmas = <&dma0 1006295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1007295436Sandrew | AT91_XDMAC_DT_PERID(36))>, 1008295436Sandrew <&dma0 1009295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1010295436Sandrew | AT91_XDMAC_DT_PERID(37))>; 1011295436Sandrew dma-names = "tx", "rx"; 1012295436Sandrew pinctrl-names = "default"; 1013295436Sandrew pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>; 1014295436Sandrew clocks = <&usart0_clk>; 1015295436Sandrew clock-names = "usart"; 1016295436Sandrew status = "disabled"; 1017295436Sandrew }; 1018295436Sandrew 1019295436Sandrew usart1: serial@f8030000 { 1020295436Sandrew compatible = "atmel,at91sam9260-usart"; 1021295436Sandrew reg = <0xf8030000 0x100>; 1022295436Sandrew interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 1023295436Sandrew dmas = <&dma0 1024295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1025295436Sandrew | AT91_XDMAC_DT_PERID(38))>, 1026295436Sandrew <&dma0 1027295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1028295436Sandrew | AT91_XDMAC_DT_PERID(39))>; 1029295436Sandrew dma-names = "tx", "rx"; 1030295436Sandrew pinctrl-names = "default"; 1031295436Sandrew pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>; 1032295436Sandrew clocks = <&usart1_clk>; 1033295436Sandrew clock-names = "usart"; 1034295436Sandrew status = "disabled"; 1035295436Sandrew }; 1036295436Sandrew 1037279377Simp mmc1: mmc@fc000000 { 1038279377Simp compatible = "atmel,hsmci"; 1039279377Simp reg = <0xfc000000 0x600>; 1040279377Simp interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 1041279377Simp dmas = <&dma1 1042279377Simp (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1043279377Simp | AT91_XDMAC_DT_PERID(1))>; 1044279377Simp dma-names = "rxtx"; 1045279377Simp pinctrl-names = "default"; 1046279377Simp pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; 1047279377Simp status = "disabled"; 1048279377Simp #address-cells = <1>; 1049279377Simp #size-cells = <0>; 1050279377Simp clocks = <&mci1_clk>; 1051279377Simp clock-names = "mci_clk"; 1052279377Simp }; 1053279377Simp 1054295436Sandrew uart1: serial@fc004000 { 1055295436Sandrew compatible = "atmel,at91sam9260-usart"; 1056295436Sandrew reg = <0xfc004000 0x100>; 1057295436Sandrew interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 1058295436Sandrew dmas = <&dma1 1059295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1060295436Sandrew | AT91_XDMAC_DT_PERID(24))>, 1061295436Sandrew <&dma1 1062295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1063295436Sandrew | AT91_XDMAC_DT_PERID(25))>; 1064295436Sandrew dma-names = "tx", "rx"; 1065295436Sandrew pinctrl-names = "default"; 1066295436Sandrew pinctrl-0 = <&pinctrl_uart1>; 1067295436Sandrew clocks = <&uart1_clk>; 1068295436Sandrew clock-names = "usart"; 1069295436Sandrew status = "disabled"; 1070295436Sandrew }; 1071295436Sandrew 1072279377Simp usart2: serial@fc008000 { 1073279377Simp compatible = "atmel,at91sam9260-usart"; 1074279377Simp reg = <0xfc008000 0x100>; 1075279377Simp interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; 1076279377Simp dmas = <&dma1 1077279377Simp (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1078279377Simp | AT91_XDMAC_DT_PERID(16))>, 1079279377Simp <&dma1 1080279377Simp (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1081279377Simp | AT91_XDMAC_DT_PERID(17))>; 1082279377Simp dma-names = "tx", "rx"; 1083279377Simp pinctrl-names = "default"; 1084279377Simp pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; 1085279377Simp clocks = <&usart2_clk>; 1086279377Simp clock-names = "usart"; 1087279377Simp status = "disabled"; 1088279377Simp }; 1089279377Simp 1090279377Simp usart3: serial@fc00c000 { 1091279377Simp compatible = "atmel,at91sam9260-usart"; 1092279377Simp reg = <0xfc00c000 0x100>; 1093279377Simp interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; 1094279377Simp dmas = <&dma1 1095279377Simp (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1096279377Simp | AT91_XDMAC_DT_PERID(18))>, 1097279377Simp <&dma1 1098279377Simp (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1099279377Simp | AT91_XDMAC_DT_PERID(19))>; 1100279377Simp dma-names = "tx", "rx"; 1101279377Simp pinctrl-names = "default"; 1102279377Simp pinctrl-0 = <&pinctrl_usart3>; 1103279377Simp clocks = <&usart3_clk>; 1104279377Simp clock-names = "usart"; 1105279377Simp status = "disabled"; 1106279377Simp }; 1107279377Simp 1108279377Simp usart4: serial@fc010000 { 1109279377Simp compatible = "atmel,at91sam9260-usart"; 1110279377Simp reg = <0xfc010000 0x100>; 1111279377Simp interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; 1112279377Simp dmas = <&dma1 1113279377Simp (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1114279377Simp | AT91_XDMAC_DT_PERID(20))>, 1115279377Simp <&dma1 1116279377Simp (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1117279377Simp | AT91_XDMAC_DT_PERID(21))>; 1118279377Simp dma-names = "tx", "rx"; 1119279377Simp pinctrl-names = "default"; 1120279377Simp pinctrl-0 = <&pinctrl_usart4>; 1121279377Simp clocks = <&usart4_clk>; 1122279377Simp clock-names = "usart"; 1123279377Simp status = "disabled"; 1124279377Simp }; 1125279377Simp 1126295436Sandrew ssc1: ssc@fc014000 { 1127295436Sandrew compatible = "atmel,at91sam9g45-ssc"; 1128295436Sandrew reg = <0xfc014000 0x4000>; 1129295436Sandrew interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; 1130295436Sandrew pinctrl-names = "default"; 1131295436Sandrew pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 1132295436Sandrew dmas = <&dma1 1133295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1134295436Sandrew | AT91_XDMAC_DT_PERID(28))>, 1135295436Sandrew <&dma1 1136295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1137295436Sandrew | AT91_XDMAC_DT_PERID(29))>; 1138295436Sandrew dma-names = "tx", "rx"; 1139295436Sandrew clocks = <&ssc1_clk>; 1140295436Sandrew clock-names = "pclk"; 1141295436Sandrew status = "disabled"; 1142295436Sandrew }; 1143295436Sandrew 1144295436Sandrew spi1: spi@fc018000 { 1145295436Sandrew #address-cells = <1>; 1146295436Sandrew #size-cells = <0>; 1147295436Sandrew compatible = "atmel,at91rm9200-spi"; 1148295436Sandrew reg = <0xfc018000 0x100>; 1149295436Sandrew interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>; 1150295436Sandrew dmas = <&dma1 1151295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1152295436Sandrew | AT91_XDMAC_DT_PERID(12))>, 1153295436Sandrew <&dma1 1154295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1155295436Sandrew | AT91_XDMAC_DT_PERID(13))>; 1156295436Sandrew dma-names = "tx", "rx"; 1157295436Sandrew pinctrl-names = "default"; 1158295436Sandrew pinctrl-0 = <&pinctrl_spi1>; 1159295436Sandrew clocks = <&spi1_clk>; 1160295436Sandrew clock-names = "spi_clk"; 1161295436Sandrew status = "disabled"; 1162295436Sandrew }; 1163295436Sandrew 1164295436Sandrew spi2: spi@fc01c000 { 1165295436Sandrew #address-cells = <1>; 1166295436Sandrew #size-cells = <0>; 1167295436Sandrew compatible = "atmel,at91rm9200-spi"; 1168295436Sandrew reg = <0xfc01c000 0x100>; 1169295436Sandrew interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>; 1170295436Sandrew dmas = <&dma1 1171295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1172295436Sandrew | AT91_XDMAC_DT_PERID(14))>, 1173295436Sandrew <&dma1 1174295436Sandrew (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1175295436Sandrew | AT91_XDMAC_DT_PERID(15))>; 1176295436Sandrew dma-names = "tx", "rx"; 1177295436Sandrew pinctrl-names = "default"; 1178295436Sandrew pinctrl-0 = <&pinctrl_spi2>; 1179295436Sandrew clocks = <&spi2_clk>; 1180295436Sandrew clock-names = "spi_clk"; 1181295436Sandrew status = "disabled"; 1182295436Sandrew }; 1183295436Sandrew 1184279377Simp tcb1: timer@fc020000 { 1185279377Simp compatible = "atmel,at91sam9x5-tcb"; 1186279377Simp reg = <0xfc020000 0x100>; 1187279377Simp interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; 1188295436Sandrew clocks = <&tcb1_clk>, <&clk32k>; 1189295436Sandrew clock-names = "t0_clk", "slow_clk"; 1190279377Simp }; 1191279377Simp 1192295436Sandrew macb1: ethernet@fc028000 { 1193295436Sandrew compatible = "atmel,sama5d4-gem"; 1194295436Sandrew reg = <0xfc028000 0x100>; 1195295436Sandrew interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>; 1196295436Sandrew pinctrl-names = "default"; 1197295436Sandrew pinctrl-0 = <&pinctrl_macb1_rmii>; 1198295436Sandrew #address-cells = <1>; 1199295436Sandrew #size-cells = <0>; 1200295436Sandrew clocks = <&macb1_clk>, <&macb1_clk>; 1201295436Sandrew clock-names = "hclk", "pclk"; 1202295436Sandrew status = "disabled"; 1203295436Sandrew }; 1204295436Sandrew 1205279377Simp adc0: adc@fc034000 { 1206279377Simp compatible = "atmel,at91sam9x5-adc"; 1207279377Simp reg = <0xfc034000 0x100>; 1208279377Simp interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; 1209279377Simp clocks = <&adc_clk>, 1210279377Simp <&adc_op_clk>; 1211279377Simp clock-names = "adc_clk", "adc_op_clk"; 1212279377Simp atmel,adc-channels-used = <0x01f>; 1213279377Simp atmel,adc-startup-time = <40>; 1214295436Sandrew atmel,adc-use-external-triggers; 1215279377Simp atmel,adc-vref = <3000>; 1216279377Simp atmel,adc-res = <8 10>; 1217279377Simp atmel,adc-sample-hold-time = <11>; 1218279377Simp atmel,adc-res-names = "lowres", "highres"; 1219279377Simp atmel,adc-ts-pressure-threshold = <10000>; 1220279377Simp status = "disabled"; 1221279377Simp 1222279377Simp trigger@0 { 1223279377Simp trigger-name = "external-rising"; 1224279377Simp trigger-value = <0x1>; 1225279377Simp trigger-external; 1226279377Simp }; 1227279377Simp trigger@1 { 1228279377Simp trigger-name = "external-falling"; 1229279377Simp trigger-value = <0x2>; 1230279377Simp trigger-external; 1231279377Simp }; 1232279377Simp trigger@2 { 1233279377Simp trigger-name = "external-any"; 1234279377Simp trigger-value = <0x3>; 1235279377Simp trigger-external; 1236279377Simp }; 1237279377Simp trigger@3 { 1238279377Simp trigger-name = "continuous"; 1239279377Simp trigger-value = <0x6>; 1240279377Simp }; 1241279377Simp }; 1242279377Simp 1243295436Sandrew aes@fc044000 { 1244295436Sandrew compatible = "atmel,at91sam9g46-aes"; 1245295436Sandrew reg = <0xfc044000 0x100>; 1246295436Sandrew interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 1247295436Sandrew dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1248295436Sandrew | AT91_XDMAC_DT_PERID(41))>, 1249295436Sandrew <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1250295436Sandrew | AT91_XDMAC_DT_PERID(40))>; 1251295436Sandrew dma-names = "tx", "rx"; 1252295436Sandrew clocks = <&aes_clk>; 1253295436Sandrew clock-names = "aes_clk"; 1254295436Sandrew status = "okay"; 1255295436Sandrew }; 1256295436Sandrew 1257295436Sandrew tdes@fc04c000 { 1258295436Sandrew compatible = "atmel,at91sam9g46-tdes"; 1259295436Sandrew reg = <0xfc04c000 0x100>; 1260295436Sandrew interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; 1261295436Sandrew dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1262295436Sandrew | AT91_XDMAC_DT_PERID(42))>, 1263295436Sandrew <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1264295436Sandrew | AT91_XDMAC_DT_PERID(43))>; 1265295436Sandrew dma-names = "tx", "rx"; 1266295436Sandrew clocks = <&tdes_clk>; 1267295436Sandrew clock-names = "tdes_clk"; 1268295436Sandrew status = "okay"; 1269295436Sandrew }; 1270295436Sandrew 1271295436Sandrew sha@fc050000 { 1272295436Sandrew compatible = "atmel,at91sam9g46-sha"; 1273295436Sandrew reg = <0xfc050000 0x100>; 1274295436Sandrew interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; 1275295436Sandrew dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 1276295436Sandrew | AT91_XDMAC_DT_PERID(44))>; 1277295436Sandrew dma-names = "tx"; 1278295436Sandrew clocks = <&sha_clk>; 1279295436Sandrew clock-names = "sha_clk"; 1280295436Sandrew status = "okay"; 1281295436Sandrew }; 1282295436Sandrew 1283279377Simp rstc@fc068600 { 1284295436Sandrew compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; 1285279377Simp reg = <0xfc068600 0x10>; 1286295436Sandrew clocks = <&clk32k>; 1287279377Simp }; 1288279377Simp 1289279377Simp shdwc@fc068610 { 1290279377Simp compatible = "atmel,at91sam9x5-shdwc"; 1291279377Simp reg = <0xfc068610 0x10>; 1292295436Sandrew clocks = <&clk32k>; 1293279377Simp }; 1294279377Simp 1295279377Simp pit: timer@fc068630 { 1296279377Simp compatible = "atmel,at91sam9260-pit"; 1297279377Simp reg = <0xfc068630 0x10>; 1298279377Simp interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 1299279377Simp clocks = <&h32ck>; 1300279377Simp }; 1301279377Simp 1302279377Simp watchdog@fc068640 { 1303295436Sandrew compatible = "atmel,sama5d4-wdt"; 1304279377Simp reg = <0xfc068640 0x10>; 1305295436Sandrew clocks = <&clk32k>; 1306279377Simp status = "disabled"; 1307279377Simp }; 1308279377Simp 1309279377Simp sckc@fc068650 { 1310279377Simp compatible = "atmel,at91sam9x5-sckc"; 1311279377Simp reg = <0xfc068650 0x4>; 1312279377Simp 1313279377Simp slow_rc_osc: slow_rc_osc { 1314279377Simp compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; 1315279377Simp #clock-cells = <0>; 1316279377Simp clock-frequency = <32768>; 1317279377Simp clock-accuracy = <250000000>; 1318279377Simp atmel,startup-time-usec = <75>; 1319279377Simp }; 1320279377Simp 1321279377Simp slow_osc: slow_osc { 1322279377Simp compatible = "atmel,at91sam9x5-clk-slow-osc"; 1323279377Simp #clock-cells = <0>; 1324279377Simp clocks = <&slow_xtal>; 1325279377Simp atmel,startup-time-usec = <1200000>; 1326279377Simp }; 1327279377Simp 1328279377Simp clk32k: slowck { 1329279377Simp compatible = "atmel,at91sam9x5-clk-slow"; 1330279377Simp #clock-cells = <0>; 1331279377Simp clocks = <&slow_rc_osc &slow_osc>; 1332279377Simp }; 1333279377Simp }; 1334279377Simp 1335279377Simp rtc@fc0686b0 { 1336279377Simp compatible = "atmel,at91rm9200-rtc"; 1337279377Simp reg = <0xfc0686b0 0x30>; 1338279377Simp interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1339295436Sandrew clocks = <&clk32k>; 1340279377Simp }; 1341279377Simp 1342279377Simp dbgu: serial@fc069000 { 1343295436Sandrew compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 1344279377Simp reg = <0xfc069000 0x200>; 1345279377Simp interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; 1346279377Simp pinctrl-names = "default"; 1347279377Simp pinctrl-0 = <&pinctrl_dbgu>; 1348279377Simp clocks = <&dbgu_clk>; 1349279377Simp clock-names = "usart"; 1350279377Simp status = "disabled"; 1351279377Simp }; 1352279377Simp 1353279377Simp 1354279377Simp pinctrl@fc06a000 { 1355279377Simp #address-cells = <1>; 1356279377Simp #size-cells = <1>; 1357279377Simp compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; 1358295436Sandrew ranges = <0xfc068000 0xfc068000 0x100 1359295436Sandrew 0xfc06a000 0xfc06a000 0x4000>; 1360279377Simp /* WARNING: revisit as pin spec has changed */ 1361279377Simp atmel,mux-mask = < 1362279377Simp /* A B C */ 1363279377Simp 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ 1364279377Simp 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ 1365279377Simp 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ 1366295436Sandrew 0x0003ff00 0x8002a800 0x00000000 /* pioD */ 1367279377Simp 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ 1368279377Simp >; 1369279377Simp 1370279377Simp pioA: gpio@fc06a000 { 1371279377Simp compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 1372279377Simp reg = <0xfc06a000 0x100>; 1373279377Simp interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; 1374279377Simp #gpio-cells = <2>; 1375279377Simp gpio-controller; 1376279377Simp interrupt-controller; 1377279377Simp #interrupt-cells = <2>; 1378279377Simp clocks = <&pioA_clk>; 1379279377Simp }; 1380279377Simp 1381279377Simp pioB: gpio@fc06b000 { 1382279377Simp compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 1383279377Simp reg = <0xfc06b000 0x100>; 1384279377Simp interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; 1385279377Simp #gpio-cells = <2>; 1386279377Simp gpio-controller; 1387279377Simp interrupt-controller; 1388279377Simp #interrupt-cells = <2>; 1389279377Simp clocks = <&pioB_clk>; 1390279377Simp }; 1391279377Simp 1392279377Simp pioC: gpio@fc06c000 { 1393279377Simp compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 1394279377Simp reg = <0xfc06c000 0x100>; 1395279377Simp interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; 1396279377Simp #gpio-cells = <2>; 1397279377Simp gpio-controller; 1398279377Simp interrupt-controller; 1399279377Simp #interrupt-cells = <2>; 1400279377Simp clocks = <&pioC_clk>; 1401279377Simp }; 1402279377Simp 1403279377Simp pioD: gpio@fc068000 { 1404279377Simp compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 1405279377Simp reg = <0xfc068000 0x100>; 1406279377Simp interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; 1407279377Simp #gpio-cells = <2>; 1408279377Simp gpio-controller; 1409279377Simp interrupt-controller; 1410279377Simp #interrupt-cells = <2>; 1411279377Simp clocks = <&pioD_clk>; 1412279377Simp }; 1413279377Simp 1414279377Simp pioE: gpio@fc06d000 { 1415279377Simp compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 1416279377Simp reg = <0xfc06d000 0x100>; 1417279377Simp interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; 1418279377Simp #gpio-cells = <2>; 1419279377Simp gpio-controller; 1420279377Simp interrupt-controller; 1421279377Simp #interrupt-cells = <2>; 1422279377Simp clocks = <&pioE_clk>; 1423279377Simp }; 1424279377Simp 1425279377Simp /* pinctrl pin settings */ 1426279377Simp adc0 { 1427279377Simp pinctrl_adc0_adtrg: adc0_adtrg { 1428279377Simp atmel,pins = 1429279377Simp <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */ 1430279377Simp }; 1431279377Simp pinctrl_adc0_ad0: adc0_ad0 { 1432279377Simp atmel,pins = 1433279377Simp <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1434279377Simp }; 1435279377Simp pinctrl_adc0_ad1: adc0_ad1 { 1436279377Simp atmel,pins = 1437279377Simp <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1438279377Simp }; 1439279377Simp pinctrl_adc0_ad2: adc0_ad2 { 1440279377Simp atmel,pins = 1441279377Simp <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1442279377Simp }; 1443279377Simp pinctrl_adc0_ad3: adc0_ad3 { 1444279377Simp atmel,pins = 1445279377Simp <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1446279377Simp }; 1447279377Simp pinctrl_adc0_ad4: adc0_ad4 { 1448279377Simp atmel,pins = 1449279377Simp <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1450279377Simp }; 1451279377Simp }; 1452279377Simp 1453279377Simp dbgu { 1454279377Simp pinctrl_dbgu: dbgu-0 { 1455279377Simp atmel,pins = 1456279377Simp <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */ 1457279377Simp <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */ 1458279377Simp }; 1459279377Simp }; 1460279377Simp 1461279377Simp i2c0 { 1462279377Simp pinctrl_i2c0: i2c0-0 { 1463279377Simp atmel,pins = 1464279377Simp <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE 1465279377Simp AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1466279377Simp }; 1467279377Simp }; 1468279377Simp 1469295436Sandrew i2c1 { 1470295436Sandrew pinctrl_i2c1: i2c1-0 { 1471295436Sandrew atmel,pins = 1472295436Sandrew <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */ 1473295436Sandrew AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */ 1474295436Sandrew }; 1475295436Sandrew }; 1476295436Sandrew 1477279377Simp i2c2 { 1478279377Simp pinctrl_i2c2: i2c2-0 { 1479279377Simp atmel,pins = 1480279377Simp <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */ 1481279377Simp AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */ 1482279377Simp }; 1483279377Simp }; 1484279377Simp 1485295436Sandrew isi { 1486295436Sandrew pinctrl_isi_data_0_7: isi-0-data-0-7 { 1487295436Sandrew atmel,pins = 1488295436Sandrew <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */ 1489295436Sandrew AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */ 1490295436Sandrew AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */ 1491295436Sandrew AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */ 1492295436Sandrew AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */ 1493295436Sandrew AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */ 1494295436Sandrew AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */ 1495295436Sandrew AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */ 1496295436Sandrew AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */ 1497295436Sandrew AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */ 1498295436Sandrew AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */ 1499295436Sandrew }; 1500295436Sandrew pinctrl_isi_data_8_9: isi-0-data-8-9 { 1501295436Sandrew atmel,pins = 1502295436Sandrew <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */ 1503295436Sandrew AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */ 1504295436Sandrew }; 1505295436Sandrew pinctrl_isi_data_10_11: isi-0-data-10-11 { 1506295436Sandrew atmel,pins = 1507295436Sandrew <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */ 1508295436Sandrew AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */ 1509295436Sandrew }; 1510295436Sandrew }; 1511295436Sandrew 1512295436Sandrew lcd { 1513295436Sandrew pinctrl_lcd_base: lcd-base-0 { 1514295436Sandrew atmel,pins = 1515295436Sandrew <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */ 1516295436Sandrew AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */ 1517295436Sandrew AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */ 1518295436Sandrew AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */ 1519295436Sandrew }; 1520295436Sandrew pinctrl_lcd_pwm: lcd-pwm-0 { 1521295436Sandrew atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */ 1522295436Sandrew }; 1523295436Sandrew pinctrl_lcd_rgb444: lcd-rgb-0 { 1524295436Sandrew atmel,pins = 1525295436Sandrew <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ 1526295436Sandrew AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1527295436Sandrew AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1528295436Sandrew AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1529295436Sandrew AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1530295436Sandrew AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1531295436Sandrew AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1532295436Sandrew AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1533295436Sandrew AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ 1534295436Sandrew AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1535295436Sandrew AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1536295436Sandrew AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */ 1537295436Sandrew }; 1538295436Sandrew pinctrl_lcd_rgb565: lcd-rgb-1 { 1539295436Sandrew atmel,pins = 1540295436Sandrew <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ 1541295436Sandrew AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1542295436Sandrew AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1543295436Sandrew AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1544295436Sandrew AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1545295436Sandrew AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1546295436Sandrew AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1547295436Sandrew AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1548295436Sandrew AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ 1549295436Sandrew AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1550295436Sandrew AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1551295436Sandrew AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1552295436Sandrew AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1553295436Sandrew AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1554295436Sandrew AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1555295436Sandrew AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */ 1556295436Sandrew }; 1557295436Sandrew pinctrl_lcd_rgb666: lcd-rgb-2 { 1558295436Sandrew atmel,pins = 1559295436Sandrew <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1560295436Sandrew AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1561295436Sandrew AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1562295436Sandrew AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1563295436Sandrew AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1564295436Sandrew AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1565295436Sandrew AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1566295436Sandrew AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1567295436Sandrew AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1568295436Sandrew AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1569295436Sandrew AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1570295436Sandrew AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ 1571295436Sandrew AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ 1572295436Sandrew AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ 1573295436Sandrew AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ 1574295436Sandrew AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ 1575295436Sandrew AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ 1576295436Sandrew AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ 1577295436Sandrew }; 1578295436Sandrew pinctrl_lcd_rgb777: lcd-rgb-3 { 1579295436Sandrew atmel,pins = 1580295436Sandrew /* LCDDAT0 conflicts with TMS */ 1581295436Sandrew <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1582295436Sandrew AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1583295436Sandrew AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1584295436Sandrew AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1585295436Sandrew AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1586295436Sandrew AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1587295436Sandrew AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1588295436Sandrew /* LCDDAT8 conflicts with TCK */ 1589295436Sandrew AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1590295436Sandrew AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1591295436Sandrew AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1592295436Sandrew AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1593295436Sandrew AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1594295436Sandrew AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1595295436Sandrew AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ 1596295436Sandrew /* LCDDAT16 conflicts with NTRST */ 1597295436Sandrew AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ 1598295436Sandrew AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ 1599295436Sandrew AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ 1600295436Sandrew AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ 1601295436Sandrew AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ 1602295436Sandrew AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ 1603295436Sandrew AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ 1604295436Sandrew }; 1605295436Sandrew pinctrl_lcd_rgb888: lcd-rgb-4 { 1606295436Sandrew atmel,pins = 1607295436Sandrew <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ 1608295436Sandrew AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1609295436Sandrew AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1610295436Sandrew AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1611295436Sandrew AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1612295436Sandrew AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1613295436Sandrew AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1614295436Sandrew AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1615295436Sandrew AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ 1616295436Sandrew AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1617295436Sandrew AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1618295436Sandrew AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1619295436Sandrew AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1620295436Sandrew AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1621295436Sandrew AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1622295436Sandrew AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ 1623295436Sandrew AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ 1624295436Sandrew AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ 1625295436Sandrew AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ 1626295436Sandrew AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ 1627295436Sandrew AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ 1628295436Sandrew AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ 1629295436Sandrew AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ 1630295436Sandrew AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ 1631295436Sandrew }; 1632295436Sandrew }; 1633295436Sandrew 1634279377Simp macb0 { 1635279377Simp pinctrl_macb0_rmii: macb0_rmii-0 { 1636279377Simp atmel,pins = 1637279377Simp <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */ 1638279377Simp AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */ 1639279377Simp AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */ 1640279377Simp AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */ 1641279377Simp AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */ 1642279377Simp AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */ 1643279377Simp AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */ 1644279377Simp AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */ 1645279377Simp AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */ 1646279377Simp AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */ 1647279377Simp >; 1648279377Simp }; 1649279377Simp }; 1650279377Simp 1651295436Sandrew macb1 { 1652295436Sandrew pinctrl_macb1_rmii: macb1_rmii-0 { 1653295436Sandrew atmel,pins = 1654295436Sandrew <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX0 */ 1655295436Sandrew AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX1 */ 1656295436Sandrew AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX0 */ 1657295436Sandrew AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX1 */ 1658295436Sandrew AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXDV */ 1659295436Sandrew AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXER */ 1660295436Sandrew AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXEN */ 1661295436Sandrew AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXCK */ 1662295436Sandrew AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDC */ 1663295436Sandrew AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDIO */ 1664295436Sandrew >; 1665295436Sandrew }; 1666295436Sandrew }; 1667295436Sandrew 1668279377Simp mmc0 { 1669279377Simp pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { 1670279377Simp atmel,pins = 1671279377Simp <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */ 1672295436Sandrew AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDA, conflict with NAND_D0 */ 1673295436Sandrew AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA0, conflict with NAND_D1 */ 1674279377Simp >; 1675279377Simp }; 1676279377Simp pinctrl_mmc0_dat1_3: mmc0_dat1_3 { 1677279377Simp atmel,pins = 1678295436Sandrew <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA1, conflict with NAND_D2 */ 1679295436Sandrew AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA2, conflict with NAND_D3 */ 1680295436Sandrew AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA3, conflict with NAND_D4 */ 1681279377Simp >; 1682279377Simp }; 1683295436Sandrew pinctrl_mmc0_dat4_7: mmc0_dat4_7 { 1684295436Sandrew atmel,pins = 1685295436Sandrew <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA4, conflict with NAND_D5 */ 1686295436Sandrew AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA5, conflict with NAND_D6 */ 1687295436Sandrew AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA6, conflict with NAND_D7 */ 1688295436Sandrew AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA7, conflict with NAND_OE */ 1689295436Sandrew >; 1690295436Sandrew }; 1691279377Simp }; 1692279377Simp 1693279377Simp mmc1 { 1694279377Simp pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { 1695279377Simp atmel,pins = 1696279377Simp <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */ 1697279377Simp AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */ 1698279377Simp AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */ 1699279377Simp >; 1700279377Simp }; 1701279377Simp pinctrl_mmc1_dat1_3: mmc1_dat1_3 { 1702279377Simp atmel,pins = 1703279377Simp <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */ 1704279377Simp AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */ 1705279377Simp AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */ 1706279377Simp >; 1707279377Simp }; 1708279377Simp }; 1709279377Simp 1710279377Simp nand0 { 1711279377Simp pinctrl_nand: nand-0 { 1712279377Simp atmel,pins = 1713279377Simp <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */ 1714279377Simp AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */ 1715279377Simp 1716279377Simp AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */ 1717279377Simp AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */ 1718279377Simp 1719279377Simp AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */ 1720279377Simp AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */ 1721279377Simp AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */ 1722279377Simp AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */ 1723279377Simp AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */ 1724279377Simp AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */ 1725279377Simp AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */ 1726279377Simp AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */ 1727279377Simp AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */ 1728279377Simp AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */ 1729279377Simp }; 1730279377Simp }; 1731279377Simp 1732279377Simp spi0 { 1733279377Simp pinctrl_spi0: spi0-0 { 1734279377Simp atmel,pins = 1735279377Simp <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */ 1736279377Simp AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */ 1737279377Simp AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */ 1738279377Simp >; 1739279377Simp }; 1740279377Simp }; 1741279377Simp 1742295436Sandrew ssc0 { 1743295436Sandrew pinctrl_ssc0_tx: ssc0_tx { 1744295436Sandrew atmel,pins = 1745295436Sandrew <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */ 1746295436Sandrew AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */ 1747295436Sandrew AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */ 1748295436Sandrew }; 1749295436Sandrew 1750295436Sandrew pinctrl_ssc0_rx: ssc0_rx { 1751295436Sandrew atmel,pins = 1752295436Sandrew <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */ 1753295436Sandrew AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */ 1754295436Sandrew AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */ 1755295436Sandrew }; 1756295436Sandrew }; 1757295436Sandrew 1758295436Sandrew ssc1 { 1759295436Sandrew pinctrl_ssc1_tx: ssc1_tx { 1760295436Sandrew atmel,pins = 1761295436Sandrew <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */ 1762295436Sandrew AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */ 1763295436Sandrew AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */ 1764295436Sandrew }; 1765295436Sandrew 1766295436Sandrew pinctrl_ssc1_rx: ssc1_rx { 1767295436Sandrew atmel,pins = 1768295436Sandrew <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */ 1769295436Sandrew AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */ 1770295436Sandrew AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */ 1771295436Sandrew }; 1772295436Sandrew }; 1773295436Sandrew 1774295436Sandrew spi1 { 1775295436Sandrew pinctrl_spi1: spi1-0 { 1776295436Sandrew atmel,pins = 1777295436Sandrew <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */ 1778295436Sandrew AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */ 1779295436Sandrew AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */ 1780295436Sandrew >; 1781295436Sandrew }; 1782295436Sandrew }; 1783295436Sandrew 1784295436Sandrew spi2 { 1785295436Sandrew pinctrl_spi2: spi2-0 { 1786295436Sandrew atmel,pins = 1787295436Sandrew <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */ 1788295436Sandrew AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */ 1789295436Sandrew AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */ 1790295436Sandrew >; 1791295436Sandrew }; 1792295436Sandrew }; 1793295436Sandrew 1794295436Sandrew uart0 { 1795295436Sandrew pinctrl_uart0: uart0-0 { 1796295436Sandrew atmel,pins = 1797295436Sandrew <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */ 1798295436Sandrew AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */ 1799295436Sandrew >; 1800295436Sandrew }; 1801295436Sandrew }; 1802295436Sandrew 1803295436Sandrew uart1 { 1804295436Sandrew pinctrl_uart1: uart1-0 { 1805295436Sandrew atmel,pins = 1806295436Sandrew <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_NONE /* RXD */ 1807295436Sandrew AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* TXD */ 1808295436Sandrew >; 1809295436Sandrew }; 1810295436Sandrew }; 1811295436Sandrew 1812295436Sandrew usart0 { 1813295436Sandrew pinctrl_usart0: usart0-0 { 1814295436Sandrew atmel,pins = 1815295436Sandrew <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */ 1816295436Sandrew AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */ 1817295436Sandrew >; 1818295436Sandrew }; 1819295436Sandrew pinctrl_usart0_rts: usart0_rts-0 { 1820295436Sandrew atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1821295436Sandrew }; 1822295436Sandrew pinctrl_usart0_cts: usart0_cts-0 { 1823295436Sandrew atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1824295436Sandrew }; 1825295436Sandrew }; 1826295436Sandrew 1827295436Sandrew usart1 { 1828295436Sandrew pinctrl_usart1: usart1-0 { 1829295436Sandrew atmel,pins = 1830295436Sandrew <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* RXD */ 1831295436Sandrew AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* TXD */ 1832295436Sandrew >; 1833295436Sandrew }; 1834295436Sandrew pinctrl_usart1_rts: usart1_rts-0 { 1835295436Sandrew atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1836295436Sandrew }; 1837295436Sandrew pinctrl_usart1_cts: usart1_cts-0 { 1838295436Sandrew atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1839295436Sandrew }; 1840295436Sandrew }; 1841295436Sandrew 1842279377Simp usart2 { 1843279377Simp pinctrl_usart2: usart2-0 { 1844279377Simp atmel,pins = 1845279377Simp <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */ 1846279377Simp AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */ 1847279377Simp >; 1848279377Simp }; 1849279377Simp pinctrl_usart2_rts: usart2_rts-0 { 1850279377Simp atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */ 1851279377Simp }; 1852279377Simp pinctrl_usart2_cts: usart2_cts-0 { 1853279377Simp atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */ 1854279377Simp }; 1855279377Simp }; 1856279377Simp 1857279377Simp usart3 { 1858279377Simp pinctrl_usart3: usart3-0 { 1859279377Simp atmel,pins = 1860279377Simp <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */ 1861279377Simp AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */ 1862279377Simp >; 1863279377Simp }; 1864279377Simp }; 1865279377Simp 1866279377Simp usart4 { 1867279377Simp pinctrl_usart4: usart4-0 { 1868279377Simp atmel,pins = 1869279377Simp <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */ 1870279377Simp AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */ 1871279377Simp >; 1872279377Simp }; 1873279377Simp pinctrl_usart4_rts: usart4_rts-0 { 1874279377Simp atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */ 1875279377Simp }; 1876279377Simp pinctrl_usart4_cts: usart4_cts-0 { 1877279377Simp atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */ 1878279377Simp }; 1879279377Simp }; 1880279377Simp }; 1881279377Simp 1882279377Simp aic: interrupt-controller@fc06e000 { 1883279377Simp #interrupt-cells = <3>; 1884279377Simp compatible = "atmel,sama5d4-aic"; 1885279377Simp interrupt-controller; 1886279377Simp reg = <0xfc06e000 0x200>; 1887279377Simp atmel,external-irqs = <56>; 1888279377Simp }; 1889279377Simp }; 1890279377Simp }; 1891279377Simp}; 1892