mt8127.dtsi revision 279377
1279377Simp/* 2279377Simp * Copyright (c) 2014 MediaTek Inc. 3279377Simp * Author: Joe.C <yingjoe.chen@mediatek.com> 4279377Simp * 5279377Simp * This program is free software; you can redistribute it and/or modify 6279377Simp * it under the terms of the GNU General Public License version 2 as 7279377Simp * published by the Free Software Foundation. 8279377Simp * 9279377Simp * This program is distributed in the hope that it will be useful, 10279377Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 11279377Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12279377Simp * GNU General Public License for more details. 13279377Simp */ 14279377Simp 15279377Simp#include <dt-bindings/interrupt-controller/irq.h> 16279377Simp#include <dt-bindings/interrupt-controller/arm-gic.h> 17279377Simp#include "skeleton64.dtsi" 18279377Simp 19279377Simp/ { 20279377Simp compatible = "mediatek,mt8127"; 21279377Simp interrupt-parent = <&sysirq>; 22279377Simp 23279377Simp cpus { 24279377Simp #address-cells = <1>; 25279377Simp #size-cells = <0>; 26279377Simp 27279377Simp cpu@0 { 28279377Simp device_type = "cpu"; 29279377Simp compatible = "arm,cortex-a7"; 30279377Simp reg = <0x0>; 31279377Simp }; 32279377Simp cpu@1 { 33279377Simp device_type = "cpu"; 34279377Simp compatible = "arm,cortex-a7"; 35279377Simp reg = <0x1>; 36279377Simp }; 37279377Simp cpu@2 { 38279377Simp device_type = "cpu"; 39279377Simp compatible = "arm,cortex-a7"; 40279377Simp reg = <0x2>; 41279377Simp }; 42279377Simp cpu@3 { 43279377Simp device_type = "cpu"; 44279377Simp compatible = "arm,cortex-a7"; 45279377Simp reg = <0x3>; 46279377Simp }; 47279377Simp 48279377Simp }; 49279377Simp 50279377Simp clocks { 51279377Simp #address-cells = <2>; 52279377Simp #size-cells = <2>; 53279377Simp compatible = "simple-bus"; 54279377Simp ranges; 55279377Simp 56279377Simp system_clk: dummy13m { 57279377Simp compatible = "fixed-clock"; 58279377Simp clock-frequency = <13000000>; 59279377Simp #clock-cells = <0>; 60279377Simp }; 61279377Simp 62279377Simp rtc_clk: dummy32k { 63279377Simp compatible = "fixed-clock"; 64279377Simp clock-frequency = <32000>; 65279377Simp #clock-cells = <0>; 66279377Simp }; 67279377Simp 68279377Simp uart_clk: dummy26m { 69279377Simp compatible = "fixed-clock"; 70279377Simp clock-frequency = <26000000>; 71279377Simp #clock-cells = <0>; 72279377Simp }; 73279377Simp }; 74279377Simp 75279377Simp soc { 76279377Simp #address-cells = <2>; 77279377Simp #size-cells = <2>; 78279377Simp compatible = "simple-bus"; 79279377Simp ranges; 80279377Simp 81279377Simp timer: timer@10008000 { 82279377Simp compatible = "mediatek,mt8127-timer", 83279377Simp "mediatek,mt6577-timer"; 84279377Simp reg = <0 0x10008000 0 0x80>; 85279377Simp interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; 86279377Simp clocks = <&system_clk>, <&rtc_clk>; 87279377Simp clock-names = "system-clk", "rtc-clk"; 88279377Simp }; 89279377Simp 90279377Simp sysirq: interrupt-controller@10200100 { 91279377Simp compatible = "mediatek,mt8127-sysirq", 92279377Simp "mediatek,mt6577-sysirq"; 93279377Simp interrupt-controller; 94279377Simp #interrupt-cells = <3>; 95279377Simp interrupt-parent = <&gic>; 96279377Simp reg = <0 0x10200100 0 0x1c>; 97279377Simp }; 98279377Simp 99279377Simp gic: interrupt-controller@10211000 { 100279377Simp compatible = "arm,cortex-a7-gic"; 101279377Simp interrupt-controller; 102279377Simp #interrupt-cells = <3>; 103279377Simp interrupt-parent = <&gic>; 104279377Simp reg = <0 0x10211000 0 0x1000>, 105279377Simp <0 0x10212000 0 0x1000>, 106279377Simp <0 0x10214000 0 0x2000>, 107279377Simp <0 0x10216000 0 0x2000>; 108279377Simp }; 109279377Simp 110279377Simp uart0: serial@11006000 { 111279377Simp compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 112279377Simp reg = <0 0x11002000 0 0x400>; 113279377Simp interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 114279377Simp clocks = <&uart_clk>; 115279377Simp status = "disabled"; 116279377Simp }; 117279377Simp 118279377Simp uart1: serial@11007000 { 119279377Simp compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 120279377Simp reg = <0 0x11003000 0 0x400>; 121279377Simp interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 122279377Simp clocks = <&uart_clk>; 123279377Simp status = "disabled"; 124279377Simp }; 125279377Simp 126279377Simp uart2: serial@11008000 { 127279377Simp compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 128279377Simp reg = <0 0x11004000 0 0x400>; 129279377Simp interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; 130279377Simp clocks = <&uart_clk>; 131279377Simp status = "disabled"; 132279377Simp }; 133279377Simp 134279377Simp uart3: serial@11009000 { 135279377Simp compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 136279377Simp reg = <0 0x11005000 0 0x400>; 137279377Simp interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; 138279377Simp clocks = <&uart_clk>; 139279377Simp status = "disabled"; 140279377Simp }; 141279377Simp }; 142279377Simp}; 143