1279377Simp/* 2279377Simp * Copyright (c) 2014 MediaTek Inc. 3279377Simp * Author: Joe.C <yingjoe.chen@mediatek.com> 4279377Simp * 5279377Simp * This program is free software; you can redistribute it and/or modify 6279377Simp * it under the terms of the GNU General Public License version 2 as 7279377Simp * published by the Free Software Foundation. 8279377Simp * 9279377Simp * This program is distributed in the hope that it will be useful, 10279377Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 11279377Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12279377Simp * GNU General Public License for more details. 13279377Simp */ 14279377Simp 15279377Simp#include <dt-bindings/interrupt-controller/irq.h> 16279377Simp#include <dt-bindings/interrupt-controller/arm-gic.h> 17279377Simp#include "skeleton64.dtsi" 18279377Simp 19279377Simp/ { 20279377Simp compatible = "mediatek,mt8127"; 21279377Simp interrupt-parent = <&sysirq>; 22279377Simp 23279377Simp cpus { 24279377Simp #address-cells = <1>; 25279377Simp #size-cells = <0>; 26295436Sandrew enable-method = "mediatek,mt81xx-tz-smp"; 27279377Simp 28279377Simp cpu@0 { 29279377Simp device_type = "cpu"; 30279377Simp compatible = "arm,cortex-a7"; 31279377Simp reg = <0x0>; 32279377Simp }; 33279377Simp cpu@1 { 34279377Simp device_type = "cpu"; 35279377Simp compatible = "arm,cortex-a7"; 36279377Simp reg = <0x1>; 37279377Simp }; 38279377Simp cpu@2 { 39279377Simp device_type = "cpu"; 40279377Simp compatible = "arm,cortex-a7"; 41279377Simp reg = <0x2>; 42279377Simp }; 43279377Simp cpu@3 { 44279377Simp device_type = "cpu"; 45279377Simp compatible = "arm,cortex-a7"; 46279377Simp reg = <0x3>; 47279377Simp }; 48279377Simp 49279377Simp }; 50279377Simp 51295436Sandrew reserved-memory { 52295436Sandrew #address-cells = <2>; 53295436Sandrew #size-cells = <2>; 54295436Sandrew ranges; 55295436Sandrew 56295436Sandrew trustzone-bootinfo@80002000 { 57295436Sandrew compatible = "mediatek,trustzone-bootinfo"; 58295436Sandrew reg = <0 0x80002000 0 0x1000>; 59295436Sandrew }; 60295436Sandrew }; 61295436Sandrew 62279377Simp clocks { 63279377Simp #address-cells = <2>; 64279377Simp #size-cells = <2>; 65279377Simp compatible = "simple-bus"; 66279377Simp ranges; 67279377Simp 68279377Simp system_clk: dummy13m { 69279377Simp compatible = "fixed-clock"; 70279377Simp clock-frequency = <13000000>; 71279377Simp #clock-cells = <0>; 72279377Simp }; 73279377Simp 74279377Simp rtc_clk: dummy32k { 75279377Simp compatible = "fixed-clock"; 76279377Simp clock-frequency = <32000>; 77279377Simp #clock-cells = <0>; 78279377Simp }; 79279377Simp 80279377Simp uart_clk: dummy26m { 81279377Simp compatible = "fixed-clock"; 82279377Simp clock-frequency = <26000000>; 83279377Simp #clock-cells = <0>; 84279377Simp }; 85279377Simp }; 86279377Simp 87295436Sandrew timer { 88295436Sandrew compatible = "arm,armv7-timer"; 89295436Sandrew interrupt-parent = <&gic>; 90295436Sandrew interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 91295436Sandrew IRQ_TYPE_LEVEL_LOW)>, 92295436Sandrew <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 93295436Sandrew IRQ_TYPE_LEVEL_LOW)>, 94295436Sandrew <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 95295436Sandrew IRQ_TYPE_LEVEL_LOW)>, 96295436Sandrew <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 97295436Sandrew IRQ_TYPE_LEVEL_LOW)>; 98295436Sandrew clock-frequency = <13000000>; 99295436Sandrew arm,cpu-registers-not-fw-configured; 100295436Sandrew }; 101295436Sandrew 102279377Simp soc { 103279377Simp #address-cells = <2>; 104279377Simp #size-cells = <2>; 105279377Simp compatible = "simple-bus"; 106279377Simp ranges; 107279377Simp 108279377Simp timer: timer@10008000 { 109279377Simp compatible = "mediatek,mt8127-timer", 110279377Simp "mediatek,mt6577-timer"; 111279377Simp reg = <0 0x10008000 0 0x80>; 112279377Simp interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; 113279377Simp clocks = <&system_clk>, <&rtc_clk>; 114279377Simp clock-names = "system-clk", "rtc-clk"; 115279377Simp }; 116279377Simp 117279377Simp sysirq: interrupt-controller@10200100 { 118279377Simp compatible = "mediatek,mt8127-sysirq", 119279377Simp "mediatek,mt6577-sysirq"; 120279377Simp interrupt-controller; 121279377Simp #interrupt-cells = <3>; 122279377Simp interrupt-parent = <&gic>; 123279377Simp reg = <0 0x10200100 0 0x1c>; 124279377Simp }; 125279377Simp 126279377Simp gic: interrupt-controller@10211000 { 127279377Simp compatible = "arm,cortex-a7-gic"; 128279377Simp interrupt-controller; 129279377Simp #interrupt-cells = <3>; 130279377Simp interrupt-parent = <&gic>; 131279377Simp reg = <0 0x10211000 0 0x1000>, 132279377Simp <0 0x10212000 0 0x1000>, 133279377Simp <0 0x10214000 0 0x2000>, 134279377Simp <0 0x10216000 0 0x2000>; 135279377Simp }; 136279377Simp 137295436Sandrew uart0: serial@11002000 { 138279377Simp compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 139279377Simp reg = <0 0x11002000 0 0x400>; 140279377Simp interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 141279377Simp clocks = <&uart_clk>; 142279377Simp status = "disabled"; 143279377Simp }; 144279377Simp 145295436Sandrew uart1: serial@11003000 { 146279377Simp compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 147279377Simp reg = <0 0x11003000 0 0x400>; 148279377Simp interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 149279377Simp clocks = <&uart_clk>; 150279377Simp status = "disabled"; 151279377Simp }; 152279377Simp 153295436Sandrew uart2: serial@11004000 { 154279377Simp compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 155279377Simp reg = <0 0x11004000 0 0x400>; 156279377Simp interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; 157279377Simp clocks = <&uart_clk>; 158279377Simp status = "disabled"; 159279377Simp }; 160279377Simp 161295436Sandrew uart3: serial@11005000 { 162279377Simp compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart"; 163279377Simp reg = <0 0x11005000 0 0x400>; 164279377Simp interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; 165279377Simp clocks = <&uart_clk>; 166279377Simp status = "disabled"; 167279377Simp }; 168279377Simp }; 169279377Simp}; 170