1295011Sandrew/* 2295011Sandrew * Copyright (c) 2015 MediaTek Inc. 3295011Sandrew * Author: Erin.Lo <erin.lo@mediatek.com> 4295011Sandrew * 5295011Sandrew * This program is free software; you can redistribute it and/or modify 6295011Sandrew * it under the terms of the GNU General Public License version 2 as 7295011Sandrew * published by the Free Software Foundation. 8295011Sandrew * 9295011Sandrew * This program is distributed in the hope that it will be useful, 10295011Sandrew * but WITHOUT ANY WARRANTY; without even the implied warranty of 11295011Sandrew * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12295011Sandrew * GNU General Public License for more details. 13295011Sandrew */ 14295011Sandrew 15295011Sandrew#include <dt-bindings/interrupt-controller/irq.h> 16295011Sandrew#include <dt-bindings/interrupt-controller/arm-gic.h> 17295011Sandrew#include "skeleton64.dtsi" 18295011Sandrew 19295011Sandrew/ { 20295011Sandrew compatible = "mediatek,mt2701"; 21295011Sandrew interrupt-parent = <&sysirq>; 22295011Sandrew 23295011Sandrew cpus { 24295011Sandrew #address-cells = <1>; 25295011Sandrew #size-cells = <0>; 26295011Sandrew 27295011Sandrew cpu@0 { 28295011Sandrew device_type = "cpu"; 29295011Sandrew compatible = "arm,cortex-a7"; 30295011Sandrew reg = <0x0>; 31295011Sandrew }; 32295011Sandrew cpu@1 { 33295011Sandrew device_type = "cpu"; 34295011Sandrew compatible = "arm,cortex-a7"; 35295011Sandrew reg = <0x1>; 36295011Sandrew }; 37295011Sandrew cpu@2 { 38295011Sandrew device_type = "cpu"; 39295011Sandrew compatible = "arm,cortex-a7"; 40295011Sandrew reg = <0x2>; 41295011Sandrew }; 42295011Sandrew cpu@3 { 43295011Sandrew device_type = "cpu"; 44295011Sandrew compatible = "arm,cortex-a7"; 45295011Sandrew reg = <0x3>; 46295011Sandrew }; 47295011Sandrew }; 48295011Sandrew 49295011Sandrew system_clk: dummy13m { 50295011Sandrew compatible = "fixed-clock"; 51295011Sandrew clock-frequency = <13000000>; 52295011Sandrew #clock-cells = <0>; 53295011Sandrew }; 54295011Sandrew 55295011Sandrew rtc_clk: dummy32k { 56295011Sandrew compatible = "fixed-clock"; 57295011Sandrew clock-frequency = <32000>; 58295011Sandrew #clock-cells = <0>; 59295011Sandrew }; 60295011Sandrew 61295011Sandrew uart_clk: dummy26m { 62295011Sandrew compatible = "fixed-clock"; 63295011Sandrew clock-frequency = <26000000>; 64295011Sandrew #clock-cells = <0>; 65295011Sandrew }; 66295011Sandrew 67295011Sandrew timer { 68295011Sandrew compatible = "arm,armv7-timer"; 69295011Sandrew interrupt-parent = <&gic>; 70295011Sandrew interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 71295011Sandrew <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 72295011Sandrew <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 73295011Sandrew <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 74295011Sandrew }; 75295011Sandrew 76295011Sandrew watchdog: watchdog@10007000 { 77295011Sandrew compatible = "mediatek,mt2701-wdt", 78295011Sandrew "mediatek,mt6589-wdt"; 79295011Sandrew reg = <0 0x10007000 0 0x100>; 80295011Sandrew }; 81295011Sandrew 82295011Sandrew timer: timer@10008000 { 83295011Sandrew compatible = "mediatek,mt2701-timer", 84295011Sandrew "mediatek,mt6577-timer"; 85295011Sandrew reg = <0 0x10008000 0 0x80>; 86295011Sandrew interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; 87295011Sandrew clocks = <&system_clk>, <&rtc_clk>; 88295011Sandrew clock-names = "system-clk", "rtc-clk"; 89295011Sandrew }; 90295011Sandrew 91295011Sandrew sysirq: interrupt-controller@10200100 { 92295011Sandrew compatible = "mediatek,mt2701-sysirq", 93295011Sandrew "mediatek,mt6577-sysirq"; 94295011Sandrew interrupt-controller; 95295011Sandrew #interrupt-cells = <3>; 96295011Sandrew interrupt-parent = <&gic>; 97295011Sandrew reg = <0 0x10200100 0 0x1c>; 98295011Sandrew }; 99295011Sandrew 100295011Sandrew gic: interrupt-controller@10211000 { 101295011Sandrew compatible = "arm,cortex-a7-gic"; 102295011Sandrew interrupt-controller; 103295011Sandrew #interrupt-cells = <3>; 104295011Sandrew interrupt-parent = <&gic>; 105295011Sandrew reg = <0 0x10211000 0 0x1000>, 106295011Sandrew <0 0x10212000 0 0x1000>, 107295011Sandrew <0 0x10214000 0 0x2000>, 108295011Sandrew <0 0x10216000 0 0x2000>; 109295011Sandrew }; 110295011Sandrew 111295011Sandrew uart0: serial@11002000 { 112295011Sandrew compatible = "mediatek,mt2701-uart", 113295011Sandrew "mediatek,mt6577-uart"; 114295011Sandrew reg = <0 0x11002000 0 0x400>; 115295011Sandrew interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 116295011Sandrew clocks = <&uart_clk>; 117295011Sandrew status = "disabled"; 118295011Sandrew }; 119295011Sandrew 120295011Sandrew uart1: serial@11003000 { 121295011Sandrew compatible = "mediatek,mt2701-uart", 122295011Sandrew "mediatek,mt6577-uart"; 123295011Sandrew reg = <0 0x11003000 0 0x400>; 124295011Sandrew interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 125295011Sandrew clocks = <&uart_clk>; 126295011Sandrew status = "disabled"; 127295011Sandrew }; 128295011Sandrew 129295011Sandrew uart2: serial@11004000 { 130295011Sandrew compatible = "mediatek,mt2701-uart", 131295011Sandrew "mediatek,mt6577-uart"; 132295011Sandrew reg = <0 0x11004000 0 0x400>; 133295011Sandrew interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; 134295011Sandrew clocks = <&uart_clk>; 135295011Sandrew status = "disabled"; 136295011Sandrew }; 137295011Sandrew 138295011Sandrew uart3: serial@11005000 { 139295011Sandrew compatible = "mediatek,mt2701-uart", 140295011Sandrew "mediatek,mt6577-uart"; 141295011Sandrew reg = <0 0x11005000 0 0x400>; 142295011Sandrew interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; 143295011Sandrew clocks = <&uart_clk>; 144295011Sandrew status = "disabled"; 145295011Sandrew }; 146295011Sandrew}; 147