1279377Simp/* 2279377Simp * Copyright (C) 2012 Marvell Technology Group Ltd. 3279377Simp * Author: Haojian Zhuang <haojian.zhuang@marvell.com> 4279377Simp * 5279377Simp * This program is free software; you can redistribute it and/or modify 6279377Simp * it under the terms of the GNU General Public License version 2 as 7279377Simp * publishhed by the Free Software Foundation. 8279377Simp */ 9279377Simp 10279377Simp#include "skeleton.dtsi" 11279377Simp#include <dt-bindings/clock/marvell,mmp2.h> 12279377Simp 13279377Simp/ { 14279377Simp aliases { 15279377Simp serial0 = &uart1; 16279377Simp serial1 = &uart2; 17279377Simp serial2 = &uart3; 18279377Simp serial3 = &uart4; 19279377Simp i2c0 = &twsi1; 20279377Simp i2c1 = &twsi2; 21279377Simp }; 22279377Simp 23279377Simp soc { 24279377Simp #address-cells = <1>; 25279377Simp #size-cells = <1>; 26279377Simp compatible = "simple-bus"; 27279377Simp interrupt-parent = <&intc>; 28279377Simp ranges; 29279377Simp 30279377Simp L2: l2-cache { 31279377Simp compatible = "marvell,tauros2-cache"; 32279377Simp marvell,tauros2-cache-features = <0x3>; 33279377Simp }; 34279377Simp 35279377Simp axi@d4200000 { /* AXI */ 36279377Simp compatible = "mrvl,axi-bus", "simple-bus"; 37279377Simp #address-cells = <1>; 38279377Simp #size-cells = <1>; 39279377Simp reg = <0xd4200000 0x00200000>; 40279377Simp ranges; 41279377Simp 42279377Simp intc: interrupt-controller@d4282000 { 43279377Simp compatible = "mrvl,mmp2-intc"; 44279377Simp interrupt-controller; 45279377Simp #interrupt-cells = <1>; 46279377Simp reg = <0xd4282000 0x1000>; 47279377Simp mrvl,intc-nr-irqs = <64>; 48279377Simp }; 49279377Simp 50279377Simp intcmux4: interrupt-controller@d4282150 { 51279377Simp compatible = "mrvl,mmp2-mux-intc"; 52279377Simp interrupts = <4>; 53279377Simp interrupt-controller; 54279377Simp #interrupt-cells = <1>; 55279377Simp reg = <0x150 0x4>, <0x168 0x4>; 56279377Simp reg-names = "mux status", "mux mask"; 57279377Simp mrvl,intc-nr-irqs = <2>; 58279377Simp }; 59279377Simp 60279377Simp intcmux5: interrupt-controller@d4282154 { 61279377Simp compatible = "mrvl,mmp2-mux-intc"; 62279377Simp interrupts = <5>; 63279377Simp interrupt-controller; 64279377Simp #interrupt-cells = <1>; 65279377Simp reg = <0x154 0x4>, <0x16c 0x4>; 66279377Simp reg-names = "mux status", "mux mask"; 67279377Simp mrvl,intc-nr-irqs = <2>; 68279377Simp mrvl,clr-mfp-irq = <1>; 69279377Simp }; 70279377Simp 71279377Simp intcmux9: interrupt-controller@d4282180 { 72279377Simp compatible = "mrvl,mmp2-mux-intc"; 73279377Simp interrupts = <9>; 74279377Simp interrupt-controller; 75279377Simp #interrupt-cells = <1>; 76279377Simp reg = <0x180 0x4>, <0x17c 0x4>; 77279377Simp reg-names = "mux status", "mux mask"; 78279377Simp mrvl,intc-nr-irqs = <3>; 79279377Simp }; 80279377Simp 81279377Simp intcmux17: interrupt-controller@d4282158 { 82279377Simp compatible = "mrvl,mmp2-mux-intc"; 83279377Simp interrupts = <17>; 84279377Simp interrupt-controller; 85279377Simp #interrupt-cells = <1>; 86279377Simp reg = <0x158 0x4>, <0x170 0x4>; 87279377Simp reg-names = "mux status", "mux mask"; 88279377Simp mrvl,intc-nr-irqs = <5>; 89279377Simp }; 90279377Simp 91279377Simp intcmux35: interrupt-controller@d428215c { 92279377Simp compatible = "mrvl,mmp2-mux-intc"; 93279377Simp interrupts = <35>; 94279377Simp interrupt-controller; 95279377Simp #interrupt-cells = <1>; 96279377Simp reg = <0x15c 0x4>, <0x174 0x4>; 97279377Simp reg-names = "mux status", "mux mask"; 98279377Simp mrvl,intc-nr-irqs = <15>; 99279377Simp }; 100279377Simp 101279377Simp intcmux51: interrupt-controller@d4282160 { 102279377Simp compatible = "mrvl,mmp2-mux-intc"; 103279377Simp interrupts = <51>; 104279377Simp interrupt-controller; 105279377Simp #interrupt-cells = <1>; 106279377Simp reg = <0x160 0x4>, <0x178 0x4>; 107279377Simp reg-names = "mux status", "mux mask"; 108279377Simp mrvl,intc-nr-irqs = <2>; 109279377Simp }; 110279377Simp 111279377Simp intcmux55: interrupt-controller@d4282188 { 112279377Simp compatible = "mrvl,mmp2-mux-intc"; 113279377Simp interrupts = <55>; 114279377Simp interrupt-controller; 115279377Simp #interrupt-cells = <1>; 116279377Simp reg = <0x188 0x4>, <0x184 0x4>; 117279377Simp reg-names = "mux status", "mux mask"; 118279377Simp mrvl,intc-nr-irqs = <2>; 119279377Simp }; 120279377Simp }; 121279377Simp 122279377Simp apb@d4000000 { /* APB */ 123279377Simp compatible = "mrvl,apb-bus", "simple-bus"; 124279377Simp #address-cells = <1>; 125279377Simp #size-cells = <1>; 126279377Simp reg = <0xd4000000 0x00200000>; 127279377Simp ranges; 128279377Simp 129279377Simp timer0: timer@d4014000 { 130279377Simp compatible = "mrvl,mmp-timer"; 131279377Simp reg = <0xd4014000 0x100>; 132279377Simp interrupts = <13>; 133279377Simp }; 134279377Simp 135279377Simp uart1: uart@d4030000 { 136279377Simp compatible = "mrvl,mmp-uart"; 137279377Simp reg = <0xd4030000 0x1000>; 138279377Simp interrupts = <27>; 139279377Simp clocks = <&soc_clocks MMP2_CLK_UART0>; 140279377Simp resets = <&soc_clocks MMP2_CLK_UART0>; 141279377Simp status = "disabled"; 142279377Simp }; 143279377Simp 144279377Simp uart2: uart@d4017000 { 145279377Simp compatible = "mrvl,mmp-uart"; 146279377Simp reg = <0xd4017000 0x1000>; 147279377Simp interrupts = <28>; 148279377Simp clocks = <&soc_clocks MMP2_CLK_UART1>; 149279377Simp resets = <&soc_clocks MMP2_CLK_UART1>; 150279377Simp status = "disabled"; 151279377Simp }; 152279377Simp 153279377Simp uart3: uart@d4018000 { 154279377Simp compatible = "mrvl,mmp-uart"; 155279377Simp reg = <0xd4018000 0x1000>; 156279377Simp interrupts = <24>; 157279377Simp clocks = <&soc_clocks MMP2_CLK_UART2>; 158279377Simp resets = <&soc_clocks MMP2_CLK_UART2>; 159279377Simp status = "disabled"; 160279377Simp }; 161279377Simp 162279377Simp uart4: uart@d4016000 { 163279377Simp compatible = "mrvl,mmp-uart"; 164279377Simp reg = <0xd4016000 0x1000>; 165279377Simp interrupts = <46>; 166279377Simp clocks = <&soc_clocks MMP2_CLK_UART3>; 167279377Simp resets = <&soc_clocks MMP2_CLK_UART3>; 168279377Simp status = "disabled"; 169279377Simp }; 170279377Simp 171279377Simp gpio@d4019000 { 172279377Simp compatible = "marvell,mmp2-gpio"; 173279377Simp #address-cells = <1>; 174279377Simp #size-cells = <1>; 175279377Simp reg = <0xd4019000 0x1000>; 176279377Simp gpio-controller; 177279377Simp #gpio-cells = <2>; 178279377Simp interrupts = <49>; 179279377Simp interrupt-names = "gpio_mux"; 180279377Simp clocks = <&soc_clocks MMP2_CLK_GPIO>; 181279377Simp resets = <&soc_clocks MMP2_CLK_GPIO>; 182279377Simp interrupt-controller; 183279377Simp #interrupt-cells = <1>; 184279377Simp ranges; 185279377Simp 186279377Simp gcb0: gpio@d4019000 { 187279377Simp reg = <0xd4019000 0x4>; 188279377Simp }; 189279377Simp 190279377Simp gcb1: gpio@d4019004 { 191279377Simp reg = <0xd4019004 0x4>; 192279377Simp }; 193279377Simp 194279377Simp gcb2: gpio@d4019008 { 195279377Simp reg = <0xd4019008 0x4>; 196279377Simp }; 197279377Simp 198279377Simp gcb3: gpio@d4019100 { 199279377Simp reg = <0xd4019100 0x4>; 200279377Simp }; 201279377Simp 202279377Simp gcb4: gpio@d4019104 { 203279377Simp reg = <0xd4019104 0x4>; 204279377Simp }; 205279377Simp 206279377Simp gcb5: gpio@d4019108 { 207279377Simp reg = <0xd4019108 0x4>; 208279377Simp }; 209279377Simp }; 210279377Simp 211279377Simp twsi1: i2c@d4011000 { 212279377Simp compatible = "mrvl,mmp-twsi"; 213279377Simp reg = <0xd4011000 0x1000>; 214279377Simp interrupts = <7>; 215279377Simp clocks = <&soc_clocks MMP2_CLK_TWSI0>; 216279377Simp resets = <&soc_clocks MMP2_CLK_TWSI0>; 217279377Simp #address-cells = <1>; 218279377Simp #size-cells = <0>; 219279377Simp mrvl,i2c-fast-mode; 220279377Simp status = "disabled"; 221279377Simp }; 222279377Simp 223279377Simp twsi2: i2c@d4025000 { 224279377Simp compatible = "mrvl,mmp-twsi"; 225279377Simp reg = <0xd4025000 0x1000>; 226279377Simp interrupts = <58>; 227279377Simp clocks = <&soc_clocks MMP2_CLK_TWSI1>; 228279377Simp resets = <&soc_clocks MMP2_CLK_TWSI1>; 229279377Simp status = "disabled"; 230279377Simp }; 231279377Simp 232279377Simp rtc: rtc@d4010000 { 233279377Simp compatible = "mrvl,mmp-rtc"; 234279377Simp reg = <0xd4010000 0x1000>; 235279377Simp interrupts = <1 0>; 236279377Simp interrupt-names = "rtc 1Hz", "rtc alarm"; 237279377Simp interrupt-parent = <&intcmux5>; 238279377Simp clocks = <&soc_clocks MMP2_CLK_RTC>; 239279377Simp resets = <&soc_clocks MMP2_CLK_RTC>; 240279377Simp status = "disabled"; 241279377Simp }; 242279377Simp }; 243279377Simp 244279377Simp soc_clocks: clocks{ 245279377Simp compatible = "marvell,mmp2-clock"; 246279377Simp reg = <0xd4050000 0x1000>, 247279377Simp <0xd4282800 0x400>, 248279377Simp <0xd4015000 0x1000>; 249279377Simp reg-names = "mpmu", "apmu", "apbc"; 250279377Simp #clock-cells = <1>; 251279377Simp #reset-cells = <1>; 252279377Simp }; 253279377Simp }; 254279377Simp}; 255