1295011Sandrew/* 2295011Sandrew * NXP LPC4350 and LPC4330 SoC 3295011Sandrew * 4295011Sandrew * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com> 5295011Sandrew * 6295011Sandrew * This code is released using a dual license strategy: BSD/GPL 7295011Sandrew * You can choose the licence that better fits your requirements. 8295011Sandrew * 9295011Sandrew * Released under the terms of 3-clause BSD License 10295011Sandrew * Released under the terms of GNU General Public License Version 2.0 11295011Sandrew * 12295011Sandrew */ 13295011Sandrew 14295011Sandrew/ { 15295011Sandrew compatible = "nxp,lpc4350", "nxp,lpc4330"; 16295011Sandrew 17295011Sandrew cpus { 18295011Sandrew cpu@0 { 19295011Sandrew compatible = "arm,cortex-m4"; 20295011Sandrew }; 21295011Sandrew }; 22295011Sandrew 23295011Sandrew soc { 24295011Sandrew sram0: sram@10000000 { 25295011Sandrew compatible = "mmio-sram"; 26295011Sandrew reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ 27295011Sandrew }; 28295011Sandrew 29295011Sandrew sram1: sram@10080000 { 30295011Sandrew compatible = "mmio-sram"; 31295011Sandrew reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ 32295011Sandrew }; 33295011Sandrew 34295011Sandrew sram2: sram@20000000 { 35295011Sandrew compatible = "mmio-sram"; 36295011Sandrew reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ 37295011Sandrew }; 38295011Sandrew }; 39295011Sandrew}; 40