1295011Sandrew/*
2295011Sandrew * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar)
3295011Sandrew *
4295011Sandrew * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
5295011Sandrew *
6295011Sandrew * This code is released using a dual license strategy: BSD/GPL
7295011Sandrew * You can choose the licence that better fits your requirements.
8295011Sandrew *
9295011Sandrew * Released under the terms of 3-clause BSD License
10295011Sandrew * Released under the terms of GNU General Public License Version 2.0
11295011Sandrew */
12295011Sandrew/dts-v1/;
13295011Sandrew
14295011Sandrew#include "lpc18xx.dtsi"
15295011Sandrew#include "lpc4357.dtsi"
16295011Sandrew
17295011Sandrew#include "dt-bindings/gpio/gpio.h"
18295011Sandrew
19295011Sandrew/ {
20295011Sandrew	model = "CIAA NXP LPC4337";
21295011Sandrew	compatible = "ciaa,lpc4337", "nxp,lpc4337", "nxp,lpc4350";
22295011Sandrew
23295011Sandrew	aliases {
24295011Sandrew		serial0 = &uart2;
25295011Sandrew		serial1 = &uart3;
26295011Sandrew	};
27295011Sandrew
28295011Sandrew	chosen {
29295011Sandrew		bootargs = "console=ttyS0,115200 earlyprintk";
30295011Sandrew		stdout-path = &uart2;
31295011Sandrew	};
32295011Sandrew
33295011Sandrew	memory {
34295011Sandrew		device_type = "memory";
35295011Sandrew		reg = <0x28000000 0x0800000>; /* 8 MB */
36295011Sandrew	};
37295011Sandrew};
38295011Sandrew
39295011Sandrew&pinctrl {
40295011Sandrew	enet_rmii_pins: enet-rmii-pins {
41295011Sandrew		enet_rmii_rxd_cfg {
42295011Sandrew			pins = "p1_15", "p0_0";
43295011Sandrew			function = "enet";
44295011Sandrew			slew-rate = <1>;
45295011Sandrew			bias-disable;
46295011Sandrew			input-enable;
47295011Sandrew			input-schmitt-disable;
48295011Sandrew		};
49295011Sandrew
50295011Sandrew		enet_rmii_txd_cfg {
51295011Sandrew			pins = "p1_18", "p1_20";
52295011Sandrew			function = "enet";
53295011Sandrew			slew-rate = <1>;
54295011Sandrew			bias-disable;
55295011Sandrew			input-enable;
56295011Sandrew			input-schmitt-disable;
57295011Sandrew		};
58295011Sandrew
59295011Sandrew		enet_rmii_rx_dv_cfg {
60295011Sandrew			pins = "p1_16";
61295011Sandrew			function = "enet";
62295011Sandrew			bias-disable;
63295011Sandrew			input-enable;
64295011Sandrew			input-schmitt-disable;
65295011Sandrew		};
66295011Sandrew
67295011Sandrew		enet_rmii_tx_en_cfg {
68295011Sandrew			pins = "p0_1";
69295011Sandrew			function = "enet";
70295011Sandrew			bias-disable;
71295011Sandrew			input-enable;
72295011Sandrew			input-schmitt-disable;
73295011Sandrew		};
74295011Sandrew
75295011Sandrew		enet_ref_clk_cfg {
76295011Sandrew			pins = "p1_19";
77295011Sandrew			function = "enet";
78295011Sandrew			slew-rate = <1>;
79295011Sandrew			bias-disable;
80295011Sandrew			input-enable;
81295011Sandrew			input-schmitt-disable;
82295011Sandrew		};
83295011Sandrew
84295011Sandrew		enet_mdio_cfg {
85295011Sandrew			pins = "p1_17";
86295011Sandrew			function = "enet";
87295011Sandrew			bias-disable;
88295011Sandrew			input-enable;
89295011Sandrew			input-schmitt-disable;
90295011Sandrew		};
91295011Sandrew
92295011Sandrew		enet_mdc_cfg {
93295011Sandrew			pins = "p7_7";
94295011Sandrew			function = "enet";
95295011Sandrew			slew-rate = <1>;
96295011Sandrew			bias-disable;
97295011Sandrew			input-enable;
98295011Sandrew			input-schmitt-disable;
99295011Sandrew		};
100295011Sandrew	};
101295011Sandrew
102295011Sandrew	i2c0_pins: i2c0-pins {
103295011Sandrew		i2c0_pins_cfg {
104295011Sandrew			pins = "i2c0_scl", "i2c0_sda";
105295011Sandrew			function = "i2c0";
106295011Sandrew			input-enable;
107295011Sandrew		};
108295011Sandrew	};
109295011Sandrew
110295011Sandrew	ssp_pins: ssp-pins {
111295011Sandrew		ssp1_cs {
112295011Sandrew			pins = "p6_7";
113295011Sandrew			function = "gpio";
114295011Sandrew			bias-pull-up;
115295011Sandrew			bias-disable;
116295011Sandrew		};
117295011Sandrew
118295011Sandrew		ssp1_miso_mosi {
119295011Sandrew			pins = "p1_3", "p1_4";
120295011Sandrew			function = "ssp1";
121295011Sandrew			slew-rate = <1>;
122295011Sandrew			bias-pull-down;
123295011Sandrew			input-enable;
124295011Sandrew			input-schmitt-disable;
125295011Sandrew		};
126295011Sandrew
127295011Sandrew		ssp1_sck {
128295011Sandrew			pins = "pf_4";
129295011Sandrew			function = "ssp1";
130295011Sandrew			slew-rate = <1>;
131295011Sandrew			bias-disable;
132295011Sandrew		};
133295011Sandrew	};
134295011Sandrew
135295011Sandrew	uart2_pins: uart2-pins {
136295011Sandrew		uart2_rx_cfg {
137295011Sandrew			pins = "p7_2";
138295011Sandrew			function = "uart2";
139295011Sandrew			bias-disable;
140295011Sandrew			input-enable;
141295011Sandrew		};
142295011Sandrew
143295011Sandrew		uart2_tx_cfg {
144295011Sandrew			pins = "p7_1";
145295011Sandrew			function = "uart2";
146295011Sandrew			bias-disable;
147295011Sandrew		};
148295011Sandrew	};
149295011Sandrew
150295011Sandrew	uart3_pins: uart3-pins {
151295011Sandrew		uart3_rx_cfg {
152295011Sandrew			pins = "p2_4";
153295011Sandrew			function = "uart3";
154295011Sandrew			bias-disable;
155295011Sandrew			input-enable;
156295011Sandrew		};
157295011Sandrew
158295011Sandrew		uart3_tx_cfg {
159295011Sandrew			pins = "p2_3";
160295011Sandrew			function = "uart3";
161295011Sandrew			bias-disable;
162295011Sandrew		};
163295011Sandrew	};
164295011Sandrew};
165295011Sandrew
166295011Sandrew&enet_tx_clk {
167295011Sandrew	clock-frequency = <50000000>;
168295011Sandrew};
169295011Sandrew
170295011Sandrew&i2c0 {
171295011Sandrew	status = "okay";
172295011Sandrew	pinctrl-names = "default";
173295011Sandrew	pinctrl-0 = <&i2c0_pins>;
174295011Sandrew	clock-frequency = <400000>;
175295011Sandrew
176295011Sandrew	eeprom@50 {
177295011Sandrew		compatible = "microchip,24c512";
178295011Sandrew		reg = <0x50>;
179295011Sandrew	};
180295011Sandrew
181295011Sandrew	eeprom@51 {
182295011Sandrew		compatible = "microchip,24c02";
183295011Sandrew		reg = <0x51>;
184295011Sandrew	};
185295011Sandrew
186295011Sandrew	eeprom@54 {
187295011Sandrew		compatible = "microchip,24c512";
188295011Sandrew		reg = <0x54>;
189295011Sandrew	};
190295011Sandrew};
191295011Sandrew
192295011Sandrew&mac {
193295011Sandrew	status = "okay";
194295011Sandrew	phy-mode = "rmii";
195295011Sandrew	pinctrl-names = "default";
196295011Sandrew	pinctrl-0 = <&enet_rmii_pins>;
197295011Sandrew};
198295011Sandrew
199295011Sandrew&sct_pwm {
200295011Sandrew	status = "okay";
201295011Sandrew};
202295011Sandrew
203295011Sandrew&ssp1 {
204295011Sandrew	status = "okay";
205295011Sandrew	pinctrl-names = "default";
206295011Sandrew	pinctrl-0 = <&ssp_pins>;
207295011Sandrew	cs-gpios = <&gpio LPC_GPIO(5,15) GPIO_ACTIVE_HIGH>;
208295011Sandrew	num-cs = <1>;
209295011Sandrew};
210295011Sandrew
211295011Sandrew&uart2 {
212295011Sandrew	status = "okay";
213295011Sandrew	pinctrl-names = "default";
214295011Sandrew	pinctrl-0 = <&uart2_pins>;
215295011Sandrew};
216295011Sandrew
217295011Sandrew&uart3 {
218295011Sandrew	status = "okay";
219295011Sandrew	pinctrl-names = "default";
220295011Sandrew	pinctrl-0 = <&uart3_pins>;
221295011Sandrew};
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