imx51-ts4800.dts revision 295011
1295011Sandrew/* 2295011Sandrew * Copyright 2015 Savoir-faire Linux 3295011Sandrew * 4295011Sandrew * This device tree is based on imx51-babbage.dts 5295011Sandrew * 6295011Sandrew * Licensed under the X11 license or the GPL v2 (or later) 7295011Sandrew */ 8295011Sandrew 9295011Sandrew/dts-v1/; 10295011Sandrew#include "imx51.dtsi" 11295011Sandrew 12295011Sandrew/ { 13295011Sandrew model = "Technologic Systems TS-4800"; 14295011Sandrew compatible = "technologic,imx51-ts4800", "fsl,imx51"; 15295011Sandrew 16295011Sandrew chosen { 17295011Sandrew stdout-path = &uart1; 18295011Sandrew }; 19295011Sandrew 20295011Sandrew memory { 21295011Sandrew reg = <0x90000000 0x10000000>; 22295011Sandrew }; 23295011Sandrew 24295011Sandrew clocks { 25295011Sandrew ckih1 { 26295011Sandrew clock-frequency = <22579200>; 27295011Sandrew }; 28295011Sandrew 29295011Sandrew ckih2 { 30295011Sandrew clock-frequency = <24576000>; 31295011Sandrew }; 32295011Sandrew }; 33295011Sandrew 34295011Sandrew backlight_reg: regulator-backlight { 35295011Sandrew compatible = "regulator-fixed"; 36295011Sandrew pinctrl-names = "default"; 37295011Sandrew pinctrl-0 = <&pinctrl_enable_lcd>; 38295011Sandrew regulator-name = "enable_lcd_reg"; 39295011Sandrew regulator-min-microvolt = <3300000>; 40295011Sandrew regulator-max-microvolt = <3300000>; 41295011Sandrew gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>; 42295011Sandrew enable-active-high; 43295011Sandrew }; 44295011Sandrew 45295011Sandrew backlight: backlight { 46295011Sandrew compatible = "pwm-backlight"; 47295011Sandrew pwms = <&pwm1 0 78770>; 48295011Sandrew brightness-levels = <0 150 200 255>; 49295011Sandrew default-brightness-level = <1>; 50295011Sandrew power-supply = <&backlight_reg>; 51295011Sandrew }; 52295011Sandrew 53295011Sandrew display0: display@di0 { 54295011Sandrew compatible = "fsl,imx-parallel-display"; 55295011Sandrew interface-pix-fmt = "rgb24"; 56295011Sandrew pinctrl-names = "default"; 57295011Sandrew pinctrl-0 = <&pinctrl_lcd>; 58295011Sandrew 59295011Sandrew display-timings { 60295011Sandrew 800x480p60 { 61295011Sandrew native-mode; 62295011Sandrew clock-frequency = <30066000>; 63295011Sandrew hactive = <800>; 64295011Sandrew vactive = <480>; 65295011Sandrew hfront-porch = <50>; 66295011Sandrew hback-porch = <70>; 67295011Sandrew hsync-len = <50>; 68295011Sandrew vback-porch = <0>; 69295011Sandrew vfront-porch = <0>; 70295011Sandrew vsync-len = <50>; 71295011Sandrew }; 72295011Sandrew }; 73295011Sandrew 74295011Sandrew port@0 { 75295011Sandrew display0_in: endpoint { 76295011Sandrew remote-endpoint = <&ipu_di0_disp0>; 77295011Sandrew }; 78295011Sandrew }; 79295011Sandrew }; 80295011Sandrew}; 81295011Sandrew 82295011Sandrew&esdhc1 { 83295011Sandrew pinctrl-names = "default"; 84295011Sandrew pinctrl-0 = <&pinctrl_esdhc1>; 85295011Sandrew cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; 86295011Sandrew wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 87295011Sandrew status = "okay"; 88295011Sandrew}; 89295011Sandrew 90295011Sandrew&fec { 91295011Sandrew pinctrl-names = "default"; 92295011Sandrew pinctrl-0 = <&pinctrl_fec>; 93295011Sandrew phy-mode = "mii"; 94295011Sandrew phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; 95295011Sandrew phy-reset-duration = <1>; 96295011Sandrew status = "okay"; 97295011Sandrew}; 98295011Sandrew 99295011Sandrew&i2c2 { 100295011Sandrew pinctrl-names = "default"; 101295011Sandrew pinctrl-0 = <&pinctrl_i2c2>; 102295011Sandrew status = "okay"; 103295011Sandrew 104295011Sandrew rtc: m41t00@68 { 105295011Sandrew compatible = "stm,m41t00"; 106295011Sandrew reg = <0x68>; 107295011Sandrew }; 108295011Sandrew}; 109295011Sandrew 110295011Sandrew&ipu_di0_disp0 { 111295011Sandrew remote-endpoint = <&display0_in>; 112295011Sandrew}; 113295011Sandrew 114295011Sandrew&pwm1 { 115295011Sandrew pinctrl-names = "default"; 116295011Sandrew pinctrl-0 = <&pinctrl_pwm_backlight>; 117295011Sandrew status = "okay"; 118295011Sandrew}; 119295011Sandrew 120295011Sandrew&uart1 { 121295011Sandrew pinctrl-names = "default"; 122295011Sandrew pinctrl-0 = <&pinctrl_uart1>; 123295011Sandrew status = "okay"; 124295011Sandrew}; 125295011Sandrew 126295011Sandrew&uart2 { 127295011Sandrew pinctrl-names = "default"; 128295011Sandrew pinctrl-0 = <&pinctrl_uart2>; 129295011Sandrew status = "okay"; 130295011Sandrew}; 131295011Sandrew 132295011Sandrew&uart3 { 133295011Sandrew pinctrl-names = "default"; 134295011Sandrew pinctrl-0 = <&pinctrl_uart3>; 135295011Sandrew status = "okay"; 136295011Sandrew}; 137295011Sandrew 138295011Sandrew&weim { 139295011Sandrew pinctrl-names = "default"; 140295011Sandrew pinctrl-0 = <&pinctrl_weim>; 141295011Sandrew status = "okay"; 142295011Sandrew 143295011Sandrew fpga@0 { 144295011Sandrew compatible = "simple-bus"; 145295011Sandrew fsl,weim-cs-timing = <0x0061008F 0x00000002 0x1c022000 146295011Sandrew 0x00000000 0x1c092480 0x00000000>; 147295011Sandrew reg = <0 0x0000000 0x1d000>; 148295011Sandrew #address-cells = <1>; 149295011Sandrew #size-cells = <1>; 150295011Sandrew ranges = <0 0 0 0x1d000>; 151295011Sandrew 152295011Sandrew syscon: syscon@b0010000 { 153295011Sandrew compatible = "syscon", "simple-mfd"; 154295011Sandrew reg = <0x10000 0x3d>; 155295011Sandrew reg-io-width = <2>; 156295011Sandrew 157295011Sandrew wdt@e { 158295011Sandrew compatible = "technologic,ts4800-wdt"; 159295011Sandrew syscon = <&syscon 0xe>; 160295011Sandrew }; 161295011Sandrew }; 162295011Sandrew 163295011Sandrew touchscreen { 164295011Sandrew compatible = "technologic,ts4800-ts"; 165295011Sandrew reg = <0x12000 0x1000>; 166295011Sandrew syscon = <&syscon 0x10 6>; 167295011Sandrew }; 168295011Sandrew }; 169295011Sandrew}; 170295011Sandrew 171295011Sandrew&iomuxc { 172295011Sandrew pinctrl_ecspi1: ecspi1grp { 173295011Sandrew fsl,pins = < 174295011Sandrew MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 175295011Sandrew MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 176295011Sandrew MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 177295011Sandrew MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */ 178295011Sandrew >; 179295011Sandrew }; 180295011Sandrew 181295011Sandrew pinctrl_enable_lcd: enablelcdgrp { 182295011Sandrew fsl,pins = < 183295011Sandrew MX51_PAD_CSI2_D12__GPIO4_9 0x1c5 184295011Sandrew >; 185295011Sandrew }; 186295011Sandrew 187295011Sandrew pinctrl_esdhc1: esdhc1grp { 188295011Sandrew fsl,pins = < 189295011Sandrew MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 190295011Sandrew MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 191295011Sandrew MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 192295011Sandrew MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 193295011Sandrew MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 194295011Sandrew MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 195295011Sandrew MX51_PAD_GPIO1_0__GPIO1_0 0x100 196295011Sandrew MX51_PAD_GPIO1_1__GPIO1_1 0x100 197295011Sandrew >; 198295011Sandrew }; 199295011Sandrew 200295011Sandrew pinctrl_fec: fecgrp { 201295011Sandrew fsl,pins = < 202295011Sandrew MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5 203295011Sandrew MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085 204295011Sandrew MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085 205295011Sandrew MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085 206295011Sandrew MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180 207295011Sandrew MX51_PAD_EIM_CS5__FEC_CRS 0x00000180 208295011Sandrew MX51_PAD_DISP2_DAT10__FEC_COL 0x00000180 209295011Sandrew MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x00000180 210295011Sandrew MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x00002180 211295011Sandrew MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x00002004 212295011Sandrew MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004 213295011Sandrew MX51_PAD_DI2_PIN2__FEC_MDC 0x00002004 214295011Sandrew MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x00002004 215295011Sandrew MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x00002004 216295011Sandrew MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x00002004 217295011Sandrew MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x00002004 218295011Sandrew MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x00002180 219295011Sandrew MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x000020a4 220295011Sandrew MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */ 221295011Sandrew >; 222295011Sandrew }; 223295011Sandrew 224295011Sandrew pinctrl_i2c2: i2c2grp { 225295011Sandrew fsl,pins = < 226295011Sandrew MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed 227295011Sandrew MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed 228295011Sandrew >; 229295011Sandrew }; 230295011Sandrew 231295011Sandrew pinctrl_lcd: lcdgrp { 232295011Sandrew fsl,pins = < 233295011Sandrew MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5 234295011Sandrew MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5 235295011Sandrew MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5 236295011Sandrew MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5 237295011Sandrew MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5 238295011Sandrew MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5 239295011Sandrew MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5 240295011Sandrew MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5 241295011Sandrew MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5 242295011Sandrew MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5 243295011Sandrew MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5 244295011Sandrew MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5 245295011Sandrew MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5 246295011Sandrew MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5 247295011Sandrew MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5 248295011Sandrew MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5 249295011Sandrew MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5 250295011Sandrew MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5 251295011Sandrew MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5 252295011Sandrew MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5 253295011Sandrew MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5 254295011Sandrew MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5 255295011Sandrew MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5 256295011Sandrew MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5 257295011Sandrew MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 258295011Sandrew MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 259295011Sandrew MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 260295011Sandrew MX51_PAD_DI_GP4__DI2_PIN15 0x5 261295011Sandrew >; 262295011Sandrew }; 263295011Sandrew 264295011Sandrew pinctrl_pwm_backlight: backlightgrp { 265295011Sandrew fsl,pins = < 266295011Sandrew MX51_PAD_GPIO1_2__PWM1_PWMO 0x80000000 267295011Sandrew >; 268295011Sandrew }; 269295011Sandrew 270295011Sandrew pinctrl_uart1: uart1grp { 271295011Sandrew fsl,pins = < 272295011Sandrew MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 273295011Sandrew MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 274295011Sandrew >; 275295011Sandrew }; 276295011Sandrew 277295011Sandrew pinctrl_uart2: uart2grp { 278295011Sandrew fsl,pins = < 279295011Sandrew MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 280295011Sandrew MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 281295011Sandrew >; 282295011Sandrew }; 283295011Sandrew 284295011Sandrew pinctrl_uart3: uart3grp { 285295011Sandrew fsl,pins = < 286295011Sandrew MX51_PAD_EIM_D25__UART3_RXD 0x1c5 287295011Sandrew MX51_PAD_EIM_D26__UART3_TXD 0x1c5 288295011Sandrew >; 289295011Sandrew }; 290295011Sandrew 291295011Sandrew pinctrl_weim: weimgrp { 292295011Sandrew fsl,pins = < 293295011Sandrew MX51_PAD_EIM_DTACK__EIM_DTACK 0x85 294295011Sandrew MX51_PAD_EIM_CS0__EIM_CS0 0x0 295295011Sandrew MX51_PAD_EIM_CS1__EIM_CS1 0x0 296295011Sandrew MX51_PAD_EIM_EB0__EIM_EB0 0x85 297295011Sandrew MX51_PAD_EIM_EB1__EIM_EB1 0x85 298295011Sandrew MX51_PAD_EIM_OE__EIM_OE 0x85 299295011Sandrew MX51_PAD_EIM_LBA__EIM_LBA 0x85 300295011Sandrew >; 301295011Sandrew }; 302295011Sandrew}; 303