1279377Simp/* 2279377Simp * Copyright 2013 Freescale Semiconductor, Inc. 3279377Simp * 4279377Simp * The code contained herein is licensed under the GNU General Public 5279377Simp * License. You may obtain a copy of the GNU General Public License 6279377Simp * Version 2 or later at the following locations: 7279377Simp * 8279377Simp * http://www.opensource.org/licenses/gpl-license.html 9279377Simp * http://www.gnu.org/copyleft/gpl.html 10279377Simp */ 11279377Simp 12279377Simp/dts-v1/; 13295436Sandrew#include <dt-bindings/gpio/gpio.h> 14279377Simp#include <dt-bindings/input/input.h> 15279377Simp#include "imx25.dtsi" 16279377Simp 17279377Simp/ { 18279377Simp model = "Freescale i.MX25 Product Development Kit"; 19279377Simp compatible = "fsl,imx25-pdk", "fsl,imx25"; 20279377Simp 21279377Simp memory { 22279377Simp reg = <0x80000000 0x4000000>; 23279377Simp }; 24279377Simp 25279377Simp regulators { 26279377Simp compatible = "simple-bus"; 27279377Simp #address-cells = <1>; 28279377Simp #size-cells = <0>; 29279377Simp 30279377Simp reg_fec_3v3: regulator@0 { 31279377Simp compatible = "regulator-fixed"; 32279377Simp reg = <0>; 33279377Simp regulator-name = "fec-3v3"; 34279377Simp regulator-min-microvolt = <3300000>; 35279377Simp regulator-max-microvolt = <3300000>; 36279377Simp gpio = <&gpio2 3 0>; 37279377Simp enable-active-high; 38279377Simp }; 39279377Simp 40279377Simp reg_2p5v: regulator@1 { 41279377Simp compatible = "regulator-fixed"; 42279377Simp reg = <1>; 43279377Simp regulator-name = "2P5V"; 44279377Simp regulator-min-microvolt = <2500000>; 45279377Simp regulator-max-microvolt = <2500000>; 46279377Simp }; 47279377Simp 48279377Simp reg_3p3v: regulator@2 { 49279377Simp compatible = "regulator-fixed"; 50279377Simp reg = <2>; 51279377Simp regulator-name = "3P3V"; 52279377Simp regulator-min-microvolt = <3300000>; 53279377Simp regulator-max-microvolt = <3300000>; 54279377Simp }; 55279377Simp 56279377Simp reg_can_3v3: regulator@3 { 57279377Simp compatible = "regulator-fixed"; 58279377Simp reg = <3>; 59279377Simp regulator-name = "can-3v3"; 60279377Simp regulator-min-microvolt = <3300000>; 61279377Simp regulator-max-microvolt = <3300000>; 62279377Simp gpio = <&gpio4 6 0>; 63279377Simp }; 64279377Simp }; 65279377Simp 66279377Simp sound { 67279377Simp compatible = "fsl,imx25-pdk-sgtl5000", 68279377Simp "fsl,imx-audio-sgtl5000"; 69279377Simp model = "imx25-pdk-sgtl5000"; 70279377Simp ssi-controller = <&ssi1>; 71279377Simp audio-codec = <&codec>; 72279377Simp audio-routing = 73279377Simp "MIC_IN", "Mic Jack", 74279377Simp "Mic Jack", "Mic Bias", 75279377Simp "Headphone Jack", "HP_OUT"; 76279377Simp mux-int-port = <1>; 77279377Simp mux-ext-port = <4>; 78279377Simp }; 79295436Sandrew 80295436Sandrew wvga: display { 81295436Sandrew model = "CLAA057VC01CW"; 82295436Sandrew bits-per-pixel = <16>; 83295436Sandrew fsl,pcr = <0xfa208b80>; 84295436Sandrew bus-width = <18>; 85295436Sandrew native-mode = <&wvga_timings>; 86295436Sandrew display-timings { 87295436Sandrew wvga_timings: 640x480 { 88295436Sandrew hactive = <640>; 89295436Sandrew vactive = <480>; 90295436Sandrew hback-porch = <45>; 91295436Sandrew hfront-porch = <114>; 92295436Sandrew hsync-len = <1>; 93295436Sandrew vback-porch = <33>; 94295436Sandrew vfront-porch = <11>; 95295436Sandrew vsync-len = <1>; 96295436Sandrew clock-frequency = <25200000>; 97295436Sandrew }; 98295436Sandrew }; 99295436Sandrew }; 100279377Simp}; 101279377Simp 102279377Simp&audmux { 103279377Simp pinctrl-names = "default"; 104279377Simp pinctrl-0 = <&pinctrl_audmux>; 105279377Simp status = "okay"; 106279377Simp}; 107279377Simp 108279377Simp&can1 { 109279377Simp pinctrl-names = "default"; 110279377Simp pinctrl-0 = <&pinctrl_can1>; 111279377Simp xceiver-supply = <®_can_3v3>; 112279377Simp status = "okay"; 113279377Simp}; 114279377Simp 115279377Simp&esdhc1 { 116279377Simp pinctrl-names = "default"; 117279377Simp pinctrl-0 = <&pinctrl_esdhc1>; 118295436Sandrew cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 119295436Sandrew wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; 120279377Simp status = "okay"; 121279377Simp}; 122279377Simp 123279377Simp&fec { 124279377Simp phy-mode = "rmii"; 125279377Simp pinctrl-names = "default"; 126279377Simp pinctrl-0 = <&pinctrl_fec>; 127279377Simp phy-supply = <®_fec_3v3>; 128279377Simp phy-reset-gpios = <&gpio4 8 0>; 129279377Simp status = "okay"; 130279377Simp}; 131279377Simp 132279377Simp&i2c1 { 133279377Simp clock-frequency = <100000>; 134279377Simp pinctrl-names = "default"; 135279377Simp pinctrl-0 = <&pinctrl_i2c1>; 136279377Simp status = "okay"; 137279377Simp 138279377Simp codec: sgtl5000@0a { 139279377Simp compatible = "fsl,sgtl5000"; 140279377Simp reg = <0x0a>; 141279377Simp clocks = <&clks 129>; 142279377Simp VDDA-supply = <®_2p5v>; 143279377Simp VDDIO-supply = <®_3p3v>; 144279377Simp }; 145279377Simp}; 146279377Simp 147279377Simp&iomuxc { 148279377Simp imx25-pdk { 149279377Simp pinctrl_audmux: audmuxgrp { 150279377Simp fsl,pins = < 151279377Simp MX25_PAD_RW__AUD4_TXFS 0xe0 152279377Simp MX25_PAD_OE__AUD4_TXC 0xe0 153279377Simp MX25_PAD_EB0__AUD4_TXD 0xe0 154279377Simp MX25_PAD_EB1__AUD4_RXD 0xe0 155279377Simp >; 156279377Simp }; 157279377Simp 158279377Simp pinctrl_can1: can1grp { 159279377Simp fsl,pins = < 160279377Simp MX25_PAD_GPIO_A__CAN1_TX 0x0 161279377Simp MX25_PAD_GPIO_B__CAN1_RX 0x0 162279377Simp MX25_PAD_D14__GPIO_4_6 0x80000000 163279377Simp >; 164279377Simp }; 165279377Simp 166279377Simp pinctrl_esdhc1: esdhc1grp { 167279377Simp fsl,pins = < 168279377Simp MX25_PAD_SD1_CMD__SD1_CMD 0x80000000 169279377Simp MX25_PAD_SD1_CLK__SD1_CLK 0x80000000 170279377Simp MX25_PAD_SD1_DATA0__SD1_DATA0 0x80000000 171279377Simp MX25_PAD_SD1_DATA1__SD1_DATA1 0x80000000 172279377Simp MX25_PAD_SD1_DATA2__SD1_DATA2 0x80000000 173279377Simp MX25_PAD_SD1_DATA3__SD1_DATA3 0x80000000 174279377Simp MX25_PAD_A14__GPIO_2_0 0x80000000 175279377Simp MX25_PAD_A15__GPIO_2_1 0x80000000 176279377Simp >; 177279377Simp }; 178279377Simp 179279377Simp pinctrl_fec: fecgrp { 180279377Simp fsl,pins = < 181279377Simp MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 182279377Simp MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 183279377Simp MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 184279377Simp MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 185279377Simp MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 186279377Simp MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 187279377Simp MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 188279377Simp MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 189279377Simp MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 190279377Simp MX25_PAD_A17__GPIO_2_3 0x80000000 191279377Simp MX25_PAD_D12__GPIO_4_8 0x80000000 192279377Simp >; 193279377Simp }; 194279377Simp 195279377Simp pinctrl_i2c1: i2c1grp { 196279377Simp fsl,pins = < 197279377Simp MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 198279377Simp MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 199279377Simp >; 200279377Simp }; 201279377Simp 202279377Simp pinctrl_kpp: kppgrp { 203279377Simp fsl,pins = < 204279377Simp MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000 205279377Simp MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000 206279377Simp MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000 207279377Simp MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000 208279377Simp MX25_PAD_KPP_COL0__KPP_COL0 0x80000000 209279377Simp MX25_PAD_KPP_COL1__KPP_COL1 0x80000000 210279377Simp MX25_PAD_KPP_COL2__KPP_COL2 0x80000000 211279377Simp MX25_PAD_KPP_COL3__KPP_COL3 0x80000000 212279377Simp >; 213279377Simp }; 214279377Simp 215295436Sandrew pinctrl_lcd: lcdgrp { 216295436Sandrew fsl,pins = < 217295436Sandrew MX25_PAD_LD0__LD0 0xe0 218295436Sandrew MX25_PAD_LD1__LD1 0xe0 219295436Sandrew MX25_PAD_LD2__LD2 0xe0 220295436Sandrew MX25_PAD_LD3__LD3 0xe0 221295436Sandrew MX25_PAD_LD4__LD4 0xe0 222295436Sandrew MX25_PAD_LD5__LD5 0xe0 223295436Sandrew MX25_PAD_LD6__LD6 0xe0 224295436Sandrew MX25_PAD_LD7__LD7 0xe0 225295436Sandrew MX25_PAD_LD8__LD8 0xe0 226295436Sandrew MX25_PAD_LD9__LD9 0xe0 227295436Sandrew MX25_PAD_LD10__LD10 0xe0 228295436Sandrew MX25_PAD_LD11__LD11 0xe0 229295436Sandrew MX25_PAD_LD12__LD12 0xe0 230295436Sandrew MX25_PAD_LD13__LD13 0xe0 231295436Sandrew MX25_PAD_LD14__LD14 0xe0 232295436Sandrew MX25_PAD_LD15__LD15 0xe0 233295436Sandrew MX25_PAD_GPIO_E__LD16 0xe0 234295436Sandrew MX25_PAD_GPIO_F__LD17 0xe0 235295436Sandrew MX25_PAD_HSYNC__HSYNC 0xe0 236295436Sandrew MX25_PAD_VSYNC__VSYNC 0xe0 237295436Sandrew MX25_PAD_LSCLK__LSCLK 0xe0 238295436Sandrew MX25_PAD_OE_ACD__OE_ACD 0xe0 239295436Sandrew MX25_PAD_CONTRAST__CONTRAST 0xe0 240295436Sandrew >; 241295436Sandrew }; 242279377Simp 243279377Simp pinctrl_uart1: uart1grp { 244279377Simp fsl,pins = < 245279377Simp MX25_PAD_UART1_RTS__UART1_RTS 0xe0 246279377Simp MX25_PAD_UART1_CTS__UART1_CTS 0xe0 247279377Simp MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 248279377Simp MX25_PAD_UART1_RXD__UART1_RXD 0xc0 249279377Simp >; 250279377Simp }; 251279377Simp }; 252279377Simp}; 253279377Simp 254295436Sandrew&lcdc { 255295436Sandrew display = <&wvga>; 256295436Sandrew fsl,lpccr = <0x00a903ff>; 257295436Sandrew fsl,lscr1 = <0x00120300>; 258295436Sandrew fsl,dmacr = <0x00020010>; 259295436Sandrew pinctrl-names = "default"; 260295436Sandrew pinctrl-0 = <&pinctrl_lcd>; 261295436Sandrew status = "okay"; 262295436Sandrew}; 263295436Sandrew 264279377Simp&nfc { 265279377Simp nand-on-flash-bbt; 266279377Simp status = "okay"; 267279377Simp}; 268279377Simp 269279377Simp&kpp { 270279377Simp pinctrl-names = "default"; 271279377Simp pinctrl-0 = <&pinctrl_kpp>; 272279377Simp linux,keymap = < 273279377Simp MATRIX_KEY(0x0, 0x0, KEY_UP) 274279377Simp MATRIX_KEY(0x0, 0x1, KEY_DOWN) 275279377Simp MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN) 276279377Simp MATRIX_KEY(0x0, 0x3, KEY_HOME) 277279377Simp MATRIX_KEY(0x1, 0x0, KEY_RIGHT) 278279377Simp MATRIX_KEY(0x1, 0x1, KEY_LEFT) 279279377Simp MATRIX_KEY(0x1, 0x2, KEY_ENTER) 280279377Simp MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP) 281279377Simp MATRIX_KEY(0x2, 0x0, KEY_F6) 282279377Simp MATRIX_KEY(0x2, 0x1, KEY_F8) 283279377Simp MATRIX_KEY(0x2, 0x2, KEY_F9) 284279377Simp MATRIX_KEY(0x2, 0x3, KEY_F10) 285279377Simp MATRIX_KEY(0x3, 0x0, KEY_F1) 286279377Simp MATRIX_KEY(0x3, 0x1, KEY_F2) 287279377Simp MATRIX_KEY(0x3, 0x2, KEY_F3) 288279377Simp MATRIX_KEY(0x3, 0x2, KEY_POWER) 289279377Simp >; 290279377Simp status = "okay"; 291279377Simp}; 292279377Simp 293279377Simp&ssi1 { 294279377Simp codec-handle = <&codec>; 295279377Simp status = "okay"; 296279377Simp}; 297279377Simp 298279377Simp&uart1 { 299279377Simp pinctrl-names = "default"; 300279377Simp pinctrl-0 = <&pinctrl_uart1>; 301279377Simp fsl,uart-has-rtscts; 302279377Simp status = "okay"; 303279377Simp}; 304279377Simp 305279377Simp&usbhost1 { 306279377Simp phy_type = "serial"; 307279377Simp dr_mode = "host"; 308279377Simp status = "okay"; 309279377Simp}; 310279377Simp 311279377Simp&usbotg { 312279377Simp phy_type = "utmi"; 313279377Simp dr_mode = "otg"; 314279377Simp external-vbus-divider; 315279377Simp status = "okay"; 316279377Simp}; 317