1279377Simp/* 2279377Simp * Copyright (c) 2013-2014 Linaro Ltd. 3279377Simp * Copyright (c) 2013-2014 Hisilicon Limited. 4279377Simp * 5279377Simp * This program is free software; you can redistribute it and/or modify 6279377Simp * it under the terms of the GNU General Public License version 2 as 7279377Simp * publishhed by the Free Software Foundation. 8279377Simp */ 9279377Simp 10279377Simp#include "skeleton.dtsi" 11279377Simp#include <dt-bindings/clock/hix5hd2-clock.h> 12279377Simp 13279377Simp/ { 14279377Simp aliases { 15279377Simp serial0 = &uart0; 16279377Simp }; 17279377Simp 18279377Simp gic: interrupt-controller@f8a01000 { 19279377Simp compatible = "arm,cortex-a9-gic"; 20279377Simp #interrupt-cells = <3>; 21279377Simp #address-cells = <0>; 22279377Simp interrupt-controller; 23279377Simp /* gic dist base, gic cpu base */ 24279377Simp reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>; 25279377Simp }; 26279377Simp 27279377Simp soc { 28279377Simp #address-cells = <1>; 29279377Simp #size-cells = <1>; 30279377Simp compatible = "simple-bus"; 31279377Simp interrupt-parent = <&gic>; 32279377Simp ranges = <0 0xf8000000 0x8000000>; 33279377Simp 34279377Simp amba { 35279377Simp #address-cells = <1>; 36279377Simp #size-cells = <1>; 37279377Simp compatible = "arm,amba-bus"; 38279377Simp ranges; 39279377Simp 40279377Simp timer0: timer@00002000 { 41279377Simp compatible = "arm,sp804", "arm,primecell"; 42279377Simp reg = <0x00002000 0x1000>; 43279377Simp /* timer00 & timer01 */ 44279377Simp interrupts = <0 24 4>; 45279377Simp clocks = <&clock HIX5HD2_FIXED_24M>; 46279377Simp status = "disabled"; 47279377Simp }; 48279377Simp 49279377Simp timer1: timer@00a29000 { 50279377Simp /* 51279377Simp * Only used in NORMAL state, not available ins 52279377Simp * SLOW or DOZE state. 53279377Simp * The rate is fixed in 24MHz. 54279377Simp */ 55279377Simp compatible = "arm,sp804", "arm,primecell"; 56279377Simp reg = <0x00a29000 0x1000>; 57279377Simp /* timer10 & timer11 */ 58279377Simp interrupts = <0 25 4>; 59279377Simp clocks = <&clock HIX5HD2_FIXED_24M>; 60279377Simp status = "disabled"; 61279377Simp }; 62279377Simp 63279377Simp timer2: timer@00a2a000 { 64279377Simp compatible = "arm,sp804", "arm,primecell"; 65279377Simp reg = <0x00a2a000 0x1000>; 66279377Simp /* timer20 & timer21 */ 67279377Simp interrupts = <0 26 4>; 68279377Simp clocks = <&clock HIX5HD2_FIXED_24M>; 69279377Simp status = "disabled"; 70279377Simp }; 71279377Simp 72279377Simp timer3: timer@00a2b000 { 73279377Simp compatible = "arm,sp804", "arm,primecell"; 74279377Simp reg = <0x00a2b000 0x1000>; 75279377Simp /* timer30 & timer31 */ 76279377Simp interrupts = <0 27 4>; 77279377Simp clocks = <&clock HIX5HD2_FIXED_24M>; 78279377Simp status = "disabled"; 79279377Simp }; 80279377Simp 81279377Simp timer4: timer@00a81000 { 82279377Simp compatible = "arm,sp804", "arm,primecell"; 83279377Simp reg = <0x00a81000 0x1000>; 84279377Simp /* timer30 & timer31 */ 85279377Simp interrupts = <0 28 4>; 86279377Simp clocks = <&clock HIX5HD2_FIXED_24M>; 87279377Simp status = "disabled"; 88279377Simp }; 89279377Simp 90279377Simp uart0: uart@00b00000 { 91279377Simp compatible = "arm,pl011", "arm,primecell"; 92279377Simp reg = <0x00b00000 0x1000>; 93279377Simp interrupts = <0 49 4>; 94279377Simp clocks = <&clock HIX5HD2_FIXED_83M>; 95279377Simp clock-names = "apb_pclk"; 96279377Simp status = "disabled"; 97279377Simp }; 98279377Simp 99279377Simp uart1: uart@00006000 { 100279377Simp compatible = "arm,pl011", "arm,primecell"; 101279377Simp reg = <0x00006000 0x1000>; 102279377Simp interrupts = <0 50 4>; 103279377Simp clocks = <&clock HIX5HD2_FIXED_83M>; 104279377Simp clock-names = "apb_pclk"; 105279377Simp status = "disabled"; 106279377Simp }; 107279377Simp 108279377Simp uart2: uart@00b02000 { 109279377Simp compatible = "arm,pl011", "arm,primecell"; 110279377Simp reg = <0x00b02000 0x1000>; 111279377Simp interrupts = <0 51 4>; 112279377Simp clocks = <&clock HIX5HD2_FIXED_83M>; 113279377Simp clock-names = "apb_pclk"; 114279377Simp status = "disabled"; 115279377Simp }; 116279377Simp 117279377Simp uart3: uart@00b03000 { 118279377Simp compatible = "arm,pl011", "arm,primecell"; 119279377Simp reg = <0x00b03000 0x1000>; 120279377Simp interrupts = <0 52 4>; 121279377Simp clocks = <&clock HIX5HD2_FIXED_83M>; 122279377Simp clock-names = "apb_pclk"; 123279377Simp status = "disabled"; 124279377Simp }; 125279377Simp 126279377Simp uart4: uart@00b04000 { 127279377Simp compatible = "arm,pl011", "arm,primecell"; 128279377Simp reg = <0xb04000 0x1000>; 129279377Simp interrupts = <0 53 4>; 130279377Simp clocks = <&clock HIX5HD2_FIXED_83M>; 131279377Simp clock-names = "apb_pclk"; 132279377Simp status = "disabled"; 133279377Simp }; 134279377Simp 135279377Simp gpio0: gpio@b20000 { 136279377Simp compatible = "arm,pl061", "arm,primecell"; 137279377Simp reg = <0xb20000 0x1000>; 138279377Simp interrupts = <0 108 0x4>; 139279377Simp gpio-controller; 140279377Simp #gpio-cells = <2>; 141279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 142279377Simp clock-names = "apb_pclk"; 143279377Simp interrupt-controller; 144279377Simp #interrupt-cells = <2>; 145279377Simp status = "disabled"; 146279377Simp }; 147279377Simp 148279377Simp gpio1: gpio@b21000 { 149279377Simp compatible = "arm,pl061", "arm,primecell"; 150279377Simp reg = <0xb21000 0x1000>; 151279377Simp interrupts = <0 109 0x4>; 152279377Simp gpio-controller; 153279377Simp #gpio-cells = <2>; 154279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 155279377Simp clock-names = "apb_pclk"; 156279377Simp interrupt-controller; 157279377Simp #interrupt-cells = <2>; 158279377Simp status = "disabled"; 159279377Simp }; 160279377Simp 161279377Simp gpio2: gpio@b22000 { 162279377Simp compatible = "arm,pl061", "arm,primecell"; 163279377Simp reg = <0xb22000 0x1000>; 164279377Simp interrupts = <0 110 0x4>; 165279377Simp gpio-controller; 166279377Simp #gpio-cells = <2>; 167279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 168279377Simp clock-names = "apb_pclk"; 169279377Simp interrupt-controller; 170279377Simp #interrupt-cells = <2>; 171279377Simp status = "disabled"; 172279377Simp }; 173279377Simp 174279377Simp gpio3: gpio@b23000 { 175279377Simp compatible = "arm,pl061", "arm,primecell"; 176279377Simp reg = <0xb23000 0x1000>; 177279377Simp interrupts = <0 111 0x4>; 178279377Simp gpio-controller; 179279377Simp #gpio-cells = <2>; 180279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 181279377Simp clock-names = "apb_pclk"; 182279377Simp interrupt-controller; 183279377Simp #interrupt-cells = <2>; 184279377Simp status = "disabled"; 185279377Simp }; 186279377Simp 187279377Simp gpio4: gpio@b24000 { 188279377Simp compatible = "arm,pl061", "arm,primecell"; 189279377Simp reg = <0xb24000 0x1000>; 190279377Simp interrupts = <0 112 0x4>; 191279377Simp gpio-controller; 192279377Simp #gpio-cells = <2>; 193279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 194279377Simp clock-names = "apb_pclk"; 195279377Simp interrupt-controller; 196279377Simp #interrupt-cells = <2>; 197279377Simp status = "disabled"; 198279377Simp }; 199279377Simp 200279377Simp gpio5: gpio@004000 { 201279377Simp compatible = "arm,pl061", "arm,primecell"; 202279377Simp reg = <0x004000 0x1000>; 203279377Simp interrupts = <0 113 0x4>; 204279377Simp gpio-controller; 205279377Simp #gpio-cells = <2>; 206279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 207279377Simp clock-names = "apb_pclk"; 208279377Simp interrupt-controller; 209279377Simp #interrupt-cells = <2>; 210279377Simp status = "disabled"; 211279377Simp }; 212279377Simp 213279377Simp gpio6: gpio@b26000 { 214279377Simp compatible = "arm,pl061", "arm,primecell"; 215279377Simp reg = <0xb26000 0x1000>; 216279377Simp interrupts = <0 114 0x4>; 217279377Simp gpio-controller; 218279377Simp #gpio-cells = <2>; 219279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 220279377Simp clock-names = "apb_pclk"; 221279377Simp interrupt-controller; 222279377Simp #interrupt-cells = <2>; 223279377Simp status = "disabled"; 224279377Simp }; 225279377Simp 226279377Simp gpio7: gpio@b27000 { 227279377Simp compatible = "arm,pl061", "arm,primecell"; 228279377Simp reg = <0xb27000 0x1000>; 229279377Simp interrupts = <0 115 0x4>; 230279377Simp gpio-controller; 231279377Simp #gpio-cells = <2>; 232279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 233279377Simp clock-names = "apb_pclk"; 234279377Simp interrupt-controller; 235279377Simp #interrupt-cells = <2>; 236279377Simp status = "disabled"; 237279377Simp }; 238279377Simp 239279377Simp gpio8: gpio@b28000 { 240279377Simp compatible = "arm,pl061", "arm,primecell"; 241279377Simp reg = <0xb28000 0x1000>; 242279377Simp interrupts = <0 116 0x4>; 243279377Simp gpio-controller; 244279377Simp #gpio-cells = <2>; 245279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 246279377Simp clock-names = "apb_pclk"; 247279377Simp interrupt-controller; 248279377Simp #interrupt-cells = <2>; 249279377Simp status = "disabled"; 250279377Simp }; 251279377Simp 252279377Simp gpio9: gpio@b29000 { 253279377Simp compatible = "arm,pl061", "arm,primecell"; 254279377Simp reg = <0xb29000 0x1000>; 255279377Simp interrupts = <0 117 0x4>; 256279377Simp gpio-controller; 257279377Simp #gpio-cells = <2>; 258279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 259279377Simp clock-names = "apb_pclk"; 260279377Simp interrupt-controller; 261279377Simp #interrupt-cells = <2>; 262279377Simp status = "disabled"; 263279377Simp }; 264279377Simp 265279377Simp gpio10: gpio@b2a000 { 266279377Simp compatible = "arm,pl061", "arm,primecell"; 267279377Simp reg = <0xb2a000 0x1000>; 268279377Simp interrupts = <0 118 0x4>; 269279377Simp gpio-controller; 270279377Simp #gpio-cells = <2>; 271279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 272279377Simp clock-names = "apb_pclk"; 273279377Simp interrupt-controller; 274279377Simp #interrupt-cells = <2>; 275279377Simp status = "disabled"; 276279377Simp }; 277279377Simp 278279377Simp gpio11: gpio@b2b000 { 279279377Simp compatible = "arm,pl061", "arm,primecell"; 280279377Simp reg = <0xb2b000 0x1000>; 281279377Simp interrupts = <0 119 0x4>; 282279377Simp gpio-controller; 283279377Simp #gpio-cells = <2>; 284279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 285279377Simp clock-names = "apb_pclk"; 286279377Simp interrupt-controller; 287279377Simp #interrupt-cells = <2>; 288279377Simp status = "disabled"; 289279377Simp }; 290279377Simp 291279377Simp gpio12: gpio@b2c000 { 292279377Simp compatible = "arm,pl061", "arm,primecell"; 293279377Simp reg = <0xb2c000 0x1000>; 294279377Simp interrupts = <0 120 0x4>; 295279377Simp gpio-controller; 296279377Simp #gpio-cells = <2>; 297279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 298279377Simp clock-names = "apb_pclk"; 299279377Simp interrupt-controller; 300279377Simp #interrupt-cells = <2>; 301279377Simp status = "disabled"; 302279377Simp }; 303279377Simp 304279377Simp gpio13: gpio@b2d000 { 305279377Simp compatible = "arm,pl061", "arm,primecell"; 306279377Simp reg = <0xb2d000 0x1000>; 307279377Simp interrupts = <0 121 0x4>; 308279377Simp gpio-controller; 309279377Simp #gpio-cells = <2>; 310279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 311279377Simp clock-names = "apb_pclk"; 312279377Simp interrupt-controller; 313279377Simp #interrupt-cells = <2>; 314279377Simp status = "disabled"; 315279377Simp }; 316279377Simp 317279377Simp gpio14: gpio@b2e000 { 318279377Simp compatible = "arm,pl061", "arm,primecell"; 319279377Simp reg = <0xb2e000 0x1000>; 320279377Simp interrupts = <0 122 0x4>; 321279377Simp gpio-controller; 322279377Simp #gpio-cells = <2>; 323279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 324279377Simp clock-names = "apb_pclk"; 325279377Simp interrupt-controller; 326279377Simp #interrupt-cells = <2>; 327279377Simp status = "disabled"; 328279377Simp }; 329279377Simp 330279377Simp gpio15: gpio@b2f000 { 331279377Simp compatible = "arm,pl061", "arm,primecell"; 332279377Simp reg = <0xb2f000 0x1000>; 333279377Simp interrupts = <0 123 0x4>; 334279377Simp gpio-controller; 335279377Simp #gpio-cells = <2>; 336279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 337279377Simp clock-names = "apb_pclk"; 338279377Simp interrupt-controller; 339279377Simp #interrupt-cells = <2>; 340279377Simp status = "disabled"; 341279377Simp }; 342279377Simp 343279377Simp gpio16: gpio@b30000 { 344279377Simp compatible = "arm,pl061", "arm,primecell"; 345279377Simp reg = <0xb30000 0x1000>; 346279377Simp interrupts = <0 124 0x4>; 347279377Simp gpio-controller; 348279377Simp #gpio-cells = <2>; 349279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 350279377Simp clock-names = "apb_pclk"; 351279377Simp interrupt-controller; 352279377Simp #interrupt-cells = <2>; 353279377Simp status = "disabled"; 354279377Simp }; 355279377Simp 356279377Simp gpio17: gpio@b31000 { 357279377Simp compatible = "arm,pl061", "arm,primecell"; 358279377Simp reg = <0xb31000 0x1000>; 359279377Simp interrupts = <0 125 0x4>; 360279377Simp gpio-controller; 361279377Simp #gpio-cells = <2>; 362279377Simp clocks = <&clock HIX5HD2_FIXED_100M>; 363279377Simp clock-names = "apb_pclk"; 364279377Simp interrupt-controller; 365279377Simp #interrupt-cells = <2>; 366279377Simp status = "disabled"; 367279377Simp }; 368279377Simp 369279377Simp wdt0: watchdog@a2c000 { 370279377Simp compatible = "arm,sp805", "arm,primecell"; 371279377Simp arm,primecell-periphid = <0x00141805>; 372279377Simp reg = <0xa2c000 0x1000>; 373279377Simp interrupts = <0 29 4>; 374279377Simp clocks = <&clock HIX5HD2_WDG0_RST>; 375279377Simp clock-names = "apb_pclk"; 376279377Simp }; 377279377Simp }; 378279377Simp 379279377Simp local_timer@00a00600 { 380279377Simp compatible = "arm,cortex-a9-twd-timer"; 381279377Simp reg = <0x00a00600 0x20>; 382279377Simp interrupts = <1 13 0xf01>; 383279377Simp }; 384279377Simp 385279377Simp l2: l2-cache { 386279377Simp compatible = "arm,pl310-cache"; 387279377Simp reg = <0x00a10000 0x100000>; 388279377Simp interrupts = <0 15 4>; 389279377Simp cache-unified; 390279377Simp cache-level = <2>; 391279377Simp }; 392279377Simp 393279377Simp sysctrl: system-controller@00000000 { 394279377Simp compatible = "hisilicon,sysctrl", "syscon"; 395279377Simp reg = <0x00000000 0x1000>; 396279377Simp }; 397279377Simp 398279377Simp reboot { 399279377Simp compatible = "syscon-reboot"; 400279377Simp regmap = <&sysctrl>; 401279377Simp offset = <0x4>; 402279377Simp mask = <0xdeadbeef>; 403279377Simp }; 404279377Simp 405279377Simp cpuctrl@00a22000 { 406279377Simp compatible = "hisilicon,cpuctrl"; 407279377Simp #address-cells = <1>; 408279377Simp #size-cells = <1>; 409279377Simp reg = <0x00a22000 0x2000>; 410279377Simp ranges = <0 0x00a22000 0x2000>; 411279377Simp 412279377Simp clock: clock@0 { 413279377Simp compatible = "hisilicon,hix5hd2-clock"; 414279377Simp reg = <0 0x2000>; 415279377Simp #clock-cells = <1>; 416279377Simp }; 417279377Simp }; 418279377Simp 419279377Simp /* unremovable emmc as mmcblk0 */ 420279377Simp mmc: mmc@1830000 { 421279377Simp compatible = "snps,dw-mshc"; 422279377Simp reg = <0x1830000 0x1000>; 423279377Simp interrupts = <0 35 4>; 424279377Simp clocks = <&clock HIX5HD2_MMC_CIU_RST>, 425279377Simp <&clock HIX5HD2_MMC_BIU_CLK>; 426279377Simp clock-names = "ciu", "biu"; 427279377Simp }; 428279377Simp 429279377Simp sd: mmc@1820000 { 430279377Simp compatible = "snps,dw-mshc"; 431279377Simp reg = <0x1820000 0x1000>; 432279377Simp interrupts = <0 34 4>; 433279377Simp clocks = <&clock HIX5HD2_SD_CIU_RST>, 434279377Simp <&clock HIX5HD2_SD_BIU_CLK>; 435279377Simp clock-names = "ciu","biu"; 436279377Simp }; 437279377Simp 438279377Simp gmac0: ethernet@1840000 { 439279377Simp compatible = "hisilicon,hix5hd2-gmac"; 440279377Simp reg = <0x1840000 0x1000>,<0x184300c 0x4>; 441279377Simp interrupts = <0 71 4>; 442279377Simp clocks = <&clock HIX5HD2_MAC0_CLK>; 443279377Simp status = "disabled"; 444279377Simp }; 445279377Simp 446279377Simp gmac1: ethernet@1841000 { 447279377Simp compatible = "hisilicon,hix5hd2-gmac"; 448279377Simp reg = <0x1841000 0x1000>,<0x1843010 0x4>; 449279377Simp interrupts = <0 72 4>; 450279377Simp clocks = <&clock HIX5HD2_MAC1_CLK>; 451279377Simp status = "disabled"; 452279377Simp }; 453279377Simp 454279377Simp usb0: ehci@1890000 { 455279377Simp compatible = "generic-ehci"; 456279377Simp reg = <0x1890000 0x1000>; 457279377Simp interrupts = <0 66 4>; 458279377Simp clocks = <&clock HIX5HD2_USB_CLK>; 459279377Simp }; 460279377Simp 461279377Simp usb1: ohci@1880000 { 462279377Simp compatible = "generic-ohci"; 463279377Simp reg = <0x1880000 0x1000>; 464279377Simp interrupts = <0 67 4>; 465279377Simp clocks = <&clock HIX5HD2_USB_CLK>; 466279377Simp }; 467279377Simp 468279377Simp peripheral_ctrl: syscon@a20000 { 469279377Simp compatible = "syscon"; 470279377Simp reg = <0xa20000 0x1000>; 471279377Simp }; 472279377Simp 473279377Simp sata_phy: phy@1900000 { 474279377Simp compatible = "hisilicon,hix5hd2-sata-phy"; 475279377Simp reg = <0x1900000 0x10000>; 476279377Simp #phy-cells = <0>; 477279377Simp hisilicon,peripheral-syscon = <&peripheral_ctrl>; 478279377Simp hisilicon,power-reg = <0x8 10>; 479279377Simp }; 480279377Simp 481279377Simp ahci: sata@1900000 { 482279377Simp compatible = "hisilicon,hisi-ahci"; 483279377Simp reg = <0x1900000 0x10000>; 484279377Simp interrupts = <0 70 4>; 485279377Simp clocks = <&clock HIX5HD2_SATA_CLK>; 486279377Simp }; 487279377Simp 488279377Simp ir: ir@001000 { 489279377Simp compatible = "hisilicon,hix5hd2-ir"; 490279377Simp reg = <0x001000 0x1000>; 491279377Simp interrupts = <0 47 4>; 492279377Simp clocks = <&clock HIX5HD2_FIXED_24M>; 493279377Simp hisilicon,power-syscon = <&sysctrl>; 494279377Simp }; 495279377Simp 496279377Simp i2c0: i2c@b10000 { 497279377Simp compatible = "hisilicon,hix5hd2-i2c"; 498279377Simp reg = <0xb10000 0x1000>; 499279377Simp interrupts = <0 38 4>; 500279377Simp clocks = <&clock HIX5HD2_I2C0_RST>; 501279377Simp #address-cells = <1>; 502279377Simp #size-cells = <0>; 503279377Simp status = "disabled"; 504279377Simp }; 505279377Simp 506279377Simp i2c1: i2c@b11000 { 507279377Simp compatible = "hisilicon,hix5hd2-i2c"; 508279377Simp reg = <0xb11000 0x1000>; 509279377Simp interrupts = <0 39 4>; 510279377Simp clocks = <&clock HIX5HD2_I2C1_RST>; 511279377Simp #address-cells = <1>; 512279377Simp #size-cells = <0>; 513279377Simp status = "disabled"; 514279377Simp }; 515279377Simp 516279377Simp i2c2: i2c@b12000 { 517279377Simp compatible = "hisilicon,hix5hd2-i2c"; 518279377Simp reg = <0xb12000 0x1000>; 519279377Simp interrupts = <0 40 4>; 520279377Simp clocks = <&clock HIX5HD2_I2C2_RST>; 521279377Simp #address-cells = <1>; 522279377Simp #size-cells = <0>; 523279377Simp status = "disabled"; 524279377Simp }; 525279377Simp 526279377Simp i2c3: i2c@b13000 { 527279377Simp compatible = "hisilicon,hix5hd2-i2c"; 528279377Simp reg = <0xb13000 0x1000>; 529279377Simp interrupts = <0 41 4>; 530279377Simp clocks = <&clock HIX5HD2_I2C3_RST>; 531279377Simp #address-cells = <1>; 532279377Simp #size-cells = <0>; 533279377Simp status = "disabled"; 534279377Simp }; 535279377Simp 536279377Simp i2c4: i2c@b16000 { 537279377Simp compatible = "hisilicon,hix5hd2-i2c"; 538279377Simp reg = <0xb16000 0x1000>; 539279377Simp interrupts = <0 43 4>; 540279377Simp clocks = <&clock HIX5HD2_I2C4_RST>; 541279377Simp #address-cells = <1>; 542279377Simp #size-cells = <0>; 543279377Simp status = "disabled"; 544279377Simp }; 545279377Simp 546279377Simp i2c5: i2c@b17000 { 547279377Simp compatible = "hisilicon,hix5hd2-i2c"; 548279377Simp reg = <0xb17000 0x1000>; 549279377Simp interrupts = <0 44 4>; 550279377Simp clocks = <&clock HIX5HD2_I2C5_RST>; 551279377Simp #address-cells = <1>; 552279377Simp #size-cells = <0>; 553279377Simp status = "disabled"; 554279377Simp }; 555279377Simp }; 556279377Simp}; 557