hip04.dtsi revision 279377
1279377Simp/* 2279377Simp * Hisilicon Ltd. HiP04 SoC 3279377Simp * 4279377Simp * Copyright (C) 2013-2014 Hisilicon Ltd. 5279377Simp * Copyright (C) 2013-2014 Linaro Ltd. 6279377Simp * 7279377Simp * Author: Haojian Zhuang <haojian.zhuang@linaro.org> 8279377Simp * 9279377Simp * This program is free software; you can redistribute it and/or modify 10279377Simp * it under the terms of the GNU General Public License version 2 as 11279377Simp * published by the Free Software Foundation. 12279377Simp */ 13279377Simp 14279377Simp/ { 15279377Simp /* memory bus is 64-bit */ 16279377Simp #address-cells = <2>; 17279377Simp #size-cells = <2>; 18279377Simp 19279377Simp aliases { 20279377Simp serial0 = &uart0; 21279377Simp }; 22279377Simp 23279377Simp bootwrapper { 24279377Simp compatible = "hisilicon,hip04-bootwrapper"; 25279377Simp boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>; 26279377Simp }; 27279377Simp 28279377Simp cpus { 29279377Simp #address-cells = <1>; 30279377Simp #size-cells = <0>; 31279377Simp 32279377Simp cpu-map { 33279377Simp cluster0 { 34279377Simp core0 { 35279377Simp cpu = <&CPU0>; 36279377Simp }; 37279377Simp core1 { 38279377Simp cpu = <&CPU1>; 39279377Simp }; 40279377Simp core2 { 41279377Simp cpu = <&CPU2>; 42279377Simp }; 43279377Simp core3 { 44279377Simp cpu = <&CPU3>; 45279377Simp }; 46279377Simp }; 47279377Simp cluster1 { 48279377Simp core0 { 49279377Simp cpu = <&CPU4>; 50279377Simp }; 51279377Simp core1 { 52279377Simp cpu = <&CPU5>; 53279377Simp }; 54279377Simp core2 { 55279377Simp cpu = <&CPU6>; 56279377Simp }; 57279377Simp core3 { 58279377Simp cpu = <&CPU7>; 59279377Simp }; 60279377Simp }; 61279377Simp cluster2 { 62279377Simp core0 { 63279377Simp cpu = <&CPU8>; 64279377Simp }; 65279377Simp core1 { 66279377Simp cpu = <&CPU9>; 67279377Simp }; 68279377Simp core2 { 69279377Simp cpu = <&CPU10>; 70279377Simp }; 71279377Simp core3 { 72279377Simp cpu = <&CPU11>; 73279377Simp }; 74279377Simp }; 75279377Simp cluster3 { 76279377Simp core0 { 77279377Simp cpu = <&CPU12>; 78279377Simp }; 79279377Simp core1 { 80279377Simp cpu = <&CPU13>; 81279377Simp }; 82279377Simp core2 { 83279377Simp cpu = <&CPU14>; 84279377Simp }; 85279377Simp core3 { 86279377Simp cpu = <&CPU15>; 87279377Simp }; 88279377Simp }; 89279377Simp }; 90279377Simp CPU0: cpu@0 { 91279377Simp device_type = "cpu"; 92279377Simp compatible = "arm,cortex-a15"; 93279377Simp reg = <0>; 94279377Simp }; 95279377Simp CPU1: cpu@1 { 96279377Simp device_type = "cpu"; 97279377Simp compatible = "arm,cortex-a15"; 98279377Simp reg = <1>; 99279377Simp }; 100279377Simp CPU2: cpu@2 { 101279377Simp device_type = "cpu"; 102279377Simp compatible = "arm,cortex-a15"; 103279377Simp reg = <2>; 104279377Simp }; 105279377Simp CPU3: cpu@3 { 106279377Simp device_type = "cpu"; 107279377Simp compatible = "arm,cortex-a15"; 108279377Simp reg = <3>; 109279377Simp }; 110279377Simp CPU4: cpu@100 { 111279377Simp device_type = "cpu"; 112279377Simp compatible = "arm,cortex-a15"; 113279377Simp reg = <0x100>; 114279377Simp }; 115279377Simp CPU5: cpu@101 { 116279377Simp device_type = "cpu"; 117279377Simp compatible = "arm,cortex-a15"; 118279377Simp reg = <0x101>; 119279377Simp }; 120279377Simp CPU6: cpu@102 { 121279377Simp device_type = "cpu"; 122279377Simp compatible = "arm,cortex-a15"; 123279377Simp reg = <0x102>; 124279377Simp }; 125279377Simp CPU7: cpu@103 { 126279377Simp device_type = "cpu"; 127279377Simp compatible = "arm,cortex-a15"; 128279377Simp reg = <0x103>; 129279377Simp }; 130279377Simp CPU8: cpu@200 { 131279377Simp device_type = "cpu"; 132279377Simp compatible = "arm,cortex-a15"; 133279377Simp reg = <0x200>; 134279377Simp }; 135279377Simp CPU9: cpu@201 { 136279377Simp device_type = "cpu"; 137279377Simp compatible = "arm,cortex-a15"; 138279377Simp reg = <0x201>; 139279377Simp }; 140279377Simp CPU10: cpu@202 { 141279377Simp device_type = "cpu"; 142279377Simp compatible = "arm,cortex-a15"; 143279377Simp reg = <0x202>; 144279377Simp }; 145279377Simp CPU11: cpu@203 { 146279377Simp device_type = "cpu"; 147279377Simp compatible = "arm,cortex-a15"; 148279377Simp reg = <0x203>; 149279377Simp }; 150279377Simp CPU12: cpu@300 { 151279377Simp device_type = "cpu"; 152279377Simp compatible = "arm,cortex-a15"; 153279377Simp reg = <0x300>; 154279377Simp }; 155279377Simp CPU13: cpu@301 { 156279377Simp device_type = "cpu"; 157279377Simp compatible = "arm,cortex-a15"; 158279377Simp reg = <0x301>; 159279377Simp }; 160279377Simp CPU14: cpu@302 { 161279377Simp device_type = "cpu"; 162279377Simp compatible = "arm,cortex-a15"; 163279377Simp reg = <0x302>; 164279377Simp }; 165279377Simp CPU15: cpu@303 { 166279377Simp device_type = "cpu"; 167279377Simp compatible = "arm,cortex-a15"; 168279377Simp reg = <0x303>; 169279377Simp }; 170279377Simp }; 171279377Simp 172279377Simp timer { 173279377Simp compatible = "arm,armv7-timer"; 174279377Simp interrupt-parent = <&gic>; 175279377Simp interrupts = <1 13 0xf08>, 176279377Simp <1 14 0xf08>, 177279377Simp <1 11 0xf08>, 178279377Simp <1 10 0xf08>; 179279377Simp }; 180279377Simp 181279377Simp clk_50m: clk_50m { 182279377Simp #clock-cells = <0>; 183279377Simp compatible = "fixed-clock"; 184279377Simp clock-frequency = <50000000>; 185279377Simp }; 186279377Simp 187279377Simp clk_168m: clk_168m { 188279377Simp #clock-cells = <0>; 189279377Simp compatible = "fixed-clock"; 190279377Simp clock-frequency = <168000000>; 191279377Simp }; 192279377Simp 193279377Simp clk_375m: clk_375m { 194279377Simp #clock-cells = <0>; 195279377Simp compatible = "fixed-clock"; 196279377Simp clock-frequency = <375000000>; 197279377Simp }; 198279377Simp 199279377Simp soc { 200279377Simp /* It's a 32-bit SoC. */ 201279377Simp #address-cells = <1>; 202279377Simp #size-cells = <1>; 203279377Simp compatible = "simple-bus"; 204279377Simp interrupt-parent = <&gic>; 205279377Simp ranges = <0 0 0xe0000000 0x10000000>; 206279377Simp 207279377Simp gic: interrupt-controller@c01000 { 208279377Simp compatible = "hisilicon,hip04-intc"; 209279377Simp #interrupt-cells = <3>; 210279377Simp #address-cells = <0>; 211279377Simp interrupt-controller; 212279377Simp interrupts = <1 9 0xf04>; 213279377Simp 214279377Simp reg = <0xc01000 0x1000>, <0xc02000 0x1000>, 215279377Simp <0xc04000 0x2000>, <0xc06000 0x2000>; 216279377Simp }; 217279377Simp 218279377Simp sysctrl: sysctrl { 219279377Simp compatible = "hisilicon,sysctrl"; 220279377Simp reg = <0x3e00000 0x00100000>; 221279377Simp }; 222279377Simp 223279377Simp fabric: fabric { 224279377Simp compatible = "hisilicon,hip04-fabric"; 225279377Simp reg = <0x302a000 0x1000>; 226279377Simp }; 227279377Simp 228279377Simp dual_timer0: dual_timer@3000000 { 229279377Simp compatible = "arm,sp804", "arm,primecell"; 230279377Simp reg = <0x3000000 0x1000>; 231279377Simp interrupts = <0 224 4>; 232279377Simp clocks = <&clk_50m>, <&clk_50m>; 233279377Simp clock-names = "apb_pclk"; 234279377Simp }; 235279377Simp 236279377Simp arm-pmu { 237279377Simp compatible = "arm,cortex-a15-pmu"; 238279377Simp interrupts = <0 64 4>, 239279377Simp <0 65 4>, 240279377Simp <0 66 4>, 241279377Simp <0 67 4>, 242279377Simp <0 68 4>, 243279377Simp <0 69 4>, 244279377Simp <0 70 4>, 245279377Simp <0 71 4>, 246279377Simp <0 72 4>, 247279377Simp <0 73 4>, 248279377Simp <0 74 4>, 249279377Simp <0 75 4>, 250279377Simp <0 76 4>, 251279377Simp <0 77 4>, 252279377Simp <0 78 4>, 253279377Simp <0 79 4>; 254279377Simp }; 255279377Simp 256279377Simp uart0: uart@4007000 { 257279377Simp compatible = "snps,dw-apb-uart"; 258279377Simp reg = <0x4007000 0x1000>; 259279377Simp interrupts = <0 381 4>; 260279377Simp clocks = <&clk_168m>; 261279377Simp clock-names = "uartclk"; 262279377Simp reg-shift = <2>; 263279377Simp status = "disabled"; 264279377Simp }; 265279377Simp 266279377Simp sata0: sata@a000000 { 267279377Simp compatible = "hisilicon,hisi-ahci"; 268279377Simp reg = <0xa000000 0x1000000>; 269279377Simp interrupts = <0 372 4>; 270279377Simp }; 271279377Simp 272279377Simp }; 273279377Simp 274279377Simp etb@0,e3c42000 { 275279377Simp compatible = "arm,coresight-etb10", "arm,primecell"; 276279377Simp reg = <0 0xe3c42000 0 0x1000>; 277279377Simp 278279377Simp coresight-default-sink; 279279377Simp clocks = <&clk_375m>; 280279377Simp clock-names = "apb_pclk"; 281279377Simp port { 282279377Simp etb0_in_port: endpoint@0 { 283279377Simp slave-mode; 284279377Simp remote-endpoint = <&replicator0_out_port0>; 285279377Simp }; 286279377Simp }; 287279377Simp }; 288279377Simp 289279377Simp etb@0,e3c82000 { 290279377Simp compatible = "arm,coresight-etb10", "arm,primecell"; 291279377Simp reg = <0 0xe3c82000 0 0x1000>; 292279377Simp 293279377Simp clocks = <&clk_375m>; 294279377Simp clock-names = "apb_pclk"; 295279377Simp port { 296279377Simp etb1_in_port: endpoint@0 { 297279377Simp slave-mode; 298279377Simp remote-endpoint = <&replicator1_out_port0>; 299279377Simp }; 300279377Simp }; 301279377Simp }; 302279377Simp 303279377Simp etb@0,e3cc2000 { 304279377Simp compatible = "arm,coresight-etb10", "arm,primecell"; 305279377Simp reg = <0 0xe3cc2000 0 0x1000>; 306279377Simp 307279377Simp clocks = <&clk_375m>; 308279377Simp clock-names = "apb_pclk"; 309279377Simp port { 310279377Simp etb2_in_port: endpoint@0 { 311279377Simp slave-mode; 312279377Simp remote-endpoint = <&replicator2_out_port0>; 313279377Simp }; 314279377Simp }; 315279377Simp }; 316279377Simp 317279377Simp etb@0,e3d02000 { 318279377Simp compatible = "arm,coresight-etb10", "arm,primecell"; 319279377Simp reg = <0 0xe3d02000 0 0x1000>; 320279377Simp 321279377Simp clocks = <&clk_375m>; 322279377Simp clock-names = "apb_pclk"; 323279377Simp port { 324279377Simp etb3_in_port: endpoint@0 { 325279377Simp slave-mode; 326279377Simp remote-endpoint = <&replicator3_out_port0>; 327279377Simp }; 328279377Simp }; 329279377Simp }; 330279377Simp 331279377Simp tpiu@0,e3c05000 { 332279377Simp compatible = "arm,coresight-tpiu", "arm,primecell"; 333279377Simp reg = <0 0xe3c05000 0 0x1000>; 334279377Simp 335279377Simp clocks = <&clk_375m>; 336279377Simp clock-names = "apb_pclk"; 337279377Simp port { 338279377Simp tpiu_in_port: endpoint@0 { 339279377Simp slave-mode; 340279377Simp remote-endpoint = <&funnel4_out_port0>; 341279377Simp }; 342279377Simp }; 343279377Simp }; 344279377Simp 345279377Simp replicator0 { 346279377Simp /* non-configurable replicators don't show up on the 347279377Simp * AMBA bus. As such no need to add "arm,primecell". 348279377Simp */ 349279377Simp compatible = "arm,coresight-replicator"; 350279377Simp 351279377Simp ports { 352279377Simp #address-cells = <1>; 353279377Simp #size-cells = <0>; 354279377Simp 355279377Simp /* replicator output ports */ 356279377Simp port@0 { 357279377Simp reg = <0>; 358279377Simp replicator0_out_port0: endpoint { 359279377Simp remote-endpoint = <&etb0_in_port>; 360279377Simp }; 361279377Simp }; 362279377Simp 363279377Simp port@1 { 364279377Simp reg = <1>; 365279377Simp replicator0_out_port1: endpoint { 366279377Simp remote-endpoint = <&funnel4_in_port0>; 367279377Simp }; 368279377Simp }; 369279377Simp 370279377Simp /* replicator input port */ 371279377Simp port@2 { 372279377Simp reg = <0>; 373279377Simp replicator0_in_port0: endpoint { 374279377Simp slave-mode; 375279377Simp remote-endpoint = <&funnel0_out_port0>; 376279377Simp }; 377279377Simp }; 378279377Simp }; 379279377Simp }; 380279377Simp 381279377Simp replicator1 { 382279377Simp /* non-configurable replicators don't show up on the 383279377Simp * AMBA bus. As such no need to add "arm,primecell". 384279377Simp */ 385279377Simp compatible = "arm,coresight-replicator"; 386279377Simp 387279377Simp ports { 388279377Simp #address-cells = <1>; 389279377Simp #size-cells = <0>; 390279377Simp 391279377Simp /* replicator output ports */ 392279377Simp port@0 { 393279377Simp reg = <0>; 394279377Simp replicator1_out_port0: endpoint { 395279377Simp remote-endpoint = <&etb1_in_port>; 396279377Simp }; 397279377Simp }; 398279377Simp 399279377Simp port@1 { 400279377Simp reg = <1>; 401279377Simp replicator1_out_port1: endpoint { 402279377Simp remote-endpoint = <&funnel4_in_port1>; 403279377Simp }; 404279377Simp }; 405279377Simp 406279377Simp /* replicator input port */ 407279377Simp port@2 { 408279377Simp reg = <0>; 409279377Simp replicator1_in_port0: endpoint { 410279377Simp slave-mode; 411279377Simp remote-endpoint = <&funnel1_out_port0>; 412279377Simp }; 413279377Simp }; 414279377Simp }; 415279377Simp }; 416279377Simp 417279377Simp replicator2 { 418279377Simp /* non-configurable replicators don't show up on the 419279377Simp * AMBA bus. As such no need to add "arm,primecell". 420279377Simp */ 421279377Simp compatible = "arm,coresight-replicator"; 422279377Simp 423279377Simp ports { 424279377Simp #address-cells = <1>; 425279377Simp #size-cells = <0>; 426279377Simp 427279377Simp /* replicator output ports */ 428279377Simp port@0 { 429279377Simp reg = <0>; 430279377Simp replicator2_out_port0: endpoint { 431279377Simp remote-endpoint = <&etb2_in_port>; 432279377Simp }; 433279377Simp }; 434279377Simp 435279377Simp port@1 { 436279377Simp reg = <1>; 437279377Simp replicator2_out_port1: endpoint { 438279377Simp remote-endpoint = <&funnel4_in_port2>; 439279377Simp }; 440279377Simp }; 441279377Simp 442279377Simp /* replicator input port */ 443279377Simp port@2 { 444279377Simp reg = <0>; 445279377Simp replicator2_in_port0: endpoint { 446279377Simp slave-mode; 447279377Simp remote-endpoint = <&funnel2_out_port0>; 448279377Simp }; 449279377Simp }; 450279377Simp }; 451279377Simp }; 452279377Simp 453279377Simp replicator3 { 454279377Simp /* non-configurable replicators don't show up on the 455279377Simp * AMBA bus. As such no need to add "arm,primecell". 456279377Simp */ 457279377Simp compatible = "arm,coresight-replicator"; 458279377Simp 459279377Simp ports { 460279377Simp #address-cells = <1>; 461279377Simp #size-cells = <0>; 462279377Simp 463279377Simp /* replicator output ports */ 464279377Simp port@0 { 465279377Simp reg = <0>; 466279377Simp replicator3_out_port0: endpoint { 467279377Simp remote-endpoint = <&etb3_in_port>; 468279377Simp }; 469279377Simp }; 470279377Simp 471279377Simp port@1 { 472279377Simp reg = <1>; 473279377Simp replicator3_out_port1: endpoint { 474279377Simp remote-endpoint = <&funnel4_in_port3>; 475279377Simp }; 476279377Simp }; 477279377Simp 478279377Simp /* replicator input port */ 479279377Simp port@2 { 480279377Simp reg = <0>; 481279377Simp replicator3_in_port0: endpoint { 482279377Simp slave-mode; 483279377Simp remote-endpoint = <&funnel3_out_port0>; 484279377Simp }; 485279377Simp }; 486279377Simp }; 487279377Simp }; 488279377Simp 489279377Simp funnel@0,e3c41000 { 490279377Simp compatible = "arm,coresight-funnel", "arm,primecell"; 491279377Simp reg = <0 0xe3c41000 0 0x1000>; 492279377Simp 493279377Simp clocks = <&clk_375m>; 494279377Simp clock-names = "apb_pclk"; 495279377Simp ports { 496279377Simp #address-cells = <1>; 497279377Simp #size-cells = <0>; 498279377Simp 499279377Simp /* funnel output port */ 500279377Simp port@0 { 501279377Simp reg = <0>; 502279377Simp funnel0_out_port0: endpoint { 503279377Simp remote-endpoint = 504279377Simp <&replicator0_in_port0>; 505279377Simp }; 506279377Simp }; 507279377Simp 508279377Simp /* funnel input ports */ 509279377Simp port@1 { 510279377Simp reg = <0>; 511279377Simp funnel0_in_port0: endpoint { 512279377Simp slave-mode; 513279377Simp remote-endpoint = <&ptm0_out_port>; 514279377Simp }; 515279377Simp }; 516279377Simp 517279377Simp port@2 { 518279377Simp reg = <1>; 519279377Simp funnel0_in_port1: endpoint { 520279377Simp slave-mode; 521279377Simp remote-endpoint = <&ptm1_out_port>; 522279377Simp }; 523279377Simp }; 524279377Simp 525279377Simp port@3 { 526279377Simp reg = <2>; 527279377Simp funnel0_in_port2: endpoint { 528279377Simp slave-mode; 529279377Simp remote-endpoint = <&ptm2_out_port>; 530279377Simp }; 531279377Simp }; 532279377Simp 533279377Simp port@4 { 534279377Simp reg = <3>; 535279377Simp funnel0_in_port3: endpoint { 536279377Simp slave-mode; 537279377Simp remote-endpoint = <&ptm3_out_port>; 538279377Simp }; 539279377Simp }; 540279377Simp }; 541279377Simp }; 542279377Simp 543279377Simp funnel@0,e3c81000 { 544279377Simp compatible = "arm,coresight-funnel", "arm,primecell"; 545279377Simp reg = <0 0xe3c81000 0 0x1000>; 546279377Simp 547279377Simp clocks = <&clk_375m>; 548279377Simp clock-names = "apb_pclk"; 549279377Simp ports { 550279377Simp #address-cells = <1>; 551279377Simp #size-cells = <0>; 552279377Simp 553279377Simp /* funnel output port */ 554279377Simp port@0 { 555279377Simp reg = <0>; 556279377Simp funnel1_out_port0: endpoint { 557279377Simp remote-endpoint = 558279377Simp <&replicator1_in_port0>; 559279377Simp }; 560279377Simp }; 561279377Simp 562279377Simp /* funnel input ports */ 563279377Simp port@1 { 564279377Simp reg = <0>; 565279377Simp funnel1_in_port0: endpoint { 566279377Simp slave-mode; 567279377Simp remote-endpoint = <&ptm4_out_port>; 568279377Simp }; 569279377Simp }; 570279377Simp 571279377Simp port@2 { 572279377Simp reg = <1>; 573279377Simp funnel1_in_port1: endpoint { 574279377Simp slave-mode; 575279377Simp remote-endpoint = <&ptm5_out_port>; 576279377Simp }; 577279377Simp }; 578279377Simp 579279377Simp port@3 { 580279377Simp reg = <2>; 581279377Simp funnel1_in_port2: endpoint { 582279377Simp slave-mode; 583279377Simp remote-endpoint = <&ptm6_out_port>; 584279377Simp }; 585279377Simp }; 586279377Simp 587279377Simp port@4 { 588279377Simp reg = <3>; 589279377Simp funnel1_in_port3: endpoint { 590279377Simp slave-mode; 591279377Simp remote-endpoint = <&ptm7_out_port>; 592279377Simp }; 593279377Simp }; 594279377Simp }; 595279377Simp }; 596279377Simp 597279377Simp funnel@0,e3cc1000 { 598279377Simp compatible = "arm,coresight-funnel", "arm,primecell"; 599279377Simp reg = <0 0xe3cc1000 0 0x1000>; 600279377Simp 601279377Simp clocks = <&clk_375m>; 602279377Simp clock-names = "apb_pclk"; 603279377Simp ports { 604279377Simp #address-cells = <1>; 605279377Simp #size-cells = <0>; 606279377Simp 607279377Simp /* funnel output port */ 608279377Simp port@0 { 609279377Simp reg = <0>; 610279377Simp funnel2_out_port0: endpoint { 611279377Simp remote-endpoint = 612279377Simp <&replicator2_in_port0>; 613279377Simp }; 614279377Simp }; 615279377Simp 616279377Simp /* funnel input ports */ 617279377Simp port@1 { 618279377Simp reg = <0>; 619279377Simp funnel2_in_port0: endpoint { 620279377Simp slave-mode; 621279377Simp remote-endpoint = <&ptm8_out_port>; 622279377Simp }; 623279377Simp }; 624279377Simp 625279377Simp port@2 { 626279377Simp reg = <1>; 627279377Simp funnel2_in_port1: endpoint { 628279377Simp slave-mode; 629279377Simp remote-endpoint = <&ptm9_out_port>; 630279377Simp }; 631279377Simp }; 632279377Simp 633279377Simp port@3 { 634279377Simp reg = <2>; 635279377Simp funnel2_in_port2: endpoint { 636279377Simp slave-mode; 637279377Simp remote-endpoint = <&ptm10_out_port>; 638279377Simp }; 639279377Simp }; 640279377Simp 641279377Simp port@4 { 642279377Simp reg = <3>; 643279377Simp funnel2_in_port3: endpoint { 644279377Simp slave-mode; 645279377Simp remote-endpoint = <&ptm11_out_port>; 646279377Simp }; 647279377Simp }; 648279377Simp }; 649279377Simp }; 650279377Simp 651279377Simp funnel@0,e3d01000 { 652279377Simp compatible = "arm,coresight-funnel", "arm,primecell"; 653279377Simp reg = <0 0xe3d01000 0 0x1000>; 654279377Simp 655279377Simp clocks = <&clk_375m>; 656279377Simp clock-names = "apb_pclk"; 657279377Simp ports { 658279377Simp #address-cells = <1>; 659279377Simp #size-cells = <0>; 660279377Simp 661279377Simp /* funnel output port */ 662279377Simp port@0 { 663279377Simp reg = <0>; 664279377Simp funnel3_out_port0: endpoint { 665279377Simp remote-endpoint = 666279377Simp <&replicator3_in_port0>; 667279377Simp }; 668279377Simp }; 669279377Simp 670279377Simp /* funnel input ports */ 671279377Simp port@1 { 672279377Simp reg = <0>; 673279377Simp funnel3_in_port0: endpoint { 674279377Simp slave-mode; 675279377Simp remote-endpoint = <&ptm12_out_port>; 676279377Simp }; 677279377Simp }; 678279377Simp 679279377Simp port@2 { 680279377Simp reg = <1>; 681279377Simp funnel3_in_port1: endpoint { 682279377Simp slave-mode; 683279377Simp remote-endpoint = <&ptm13_out_port>; 684279377Simp }; 685279377Simp }; 686279377Simp 687279377Simp port@3 { 688279377Simp reg = <2>; 689279377Simp funnel3_in_port2: endpoint { 690279377Simp slave-mode; 691279377Simp remote-endpoint = <&ptm14_out_port>; 692279377Simp }; 693279377Simp }; 694279377Simp 695279377Simp port@4 { 696279377Simp reg = <3>; 697279377Simp funnel3_in_port3: endpoint { 698279377Simp slave-mode; 699279377Simp remote-endpoint = <&ptm15_out_port>; 700279377Simp }; 701279377Simp }; 702279377Simp }; 703279377Simp }; 704279377Simp 705279377Simp funnel@0,e3c04000 { 706279377Simp compatible = "arm,coresight-funnel", "arm,primecell"; 707279377Simp reg = <0 0xe3c04000 0 0x1000>; 708279377Simp 709279377Simp clocks = <&clk_375m>; 710279377Simp clock-names = "apb_pclk"; 711279377Simp ports { 712279377Simp #address-cells = <1>; 713279377Simp #size-cells = <0>; 714279377Simp 715279377Simp /* funnel output port */ 716279377Simp port@0 { 717279377Simp reg = <0>; 718279377Simp funnel4_out_port0: endpoint { 719279377Simp remote-endpoint = <&tpiu_in_port>; 720279377Simp }; 721279377Simp }; 722279377Simp 723279377Simp /* funnel input ports */ 724279377Simp port@1 { 725279377Simp reg = <0>; 726279377Simp funnel4_in_port0: endpoint { 727279377Simp slave-mode; 728279377Simp remote-endpoint = 729279377Simp <&replicator0_out_port1>; 730279377Simp }; 731279377Simp }; 732279377Simp 733279377Simp port@2 { 734279377Simp reg = <1>; 735279377Simp funnel4_in_port1: endpoint { 736279377Simp slave-mode; 737279377Simp remote-endpoint = 738279377Simp <&replicator1_out_port1>; 739279377Simp }; 740279377Simp }; 741279377Simp 742279377Simp port@3 { 743279377Simp reg = <2>; 744279377Simp funnel4_in_port2: endpoint { 745279377Simp slave-mode; 746279377Simp remote-endpoint = 747279377Simp <&replicator2_out_port1>; 748279377Simp }; 749279377Simp }; 750279377Simp 751279377Simp port@4 { 752279377Simp reg = <3>; 753279377Simp funnel4_in_port3: endpoint { 754279377Simp slave-mode; 755279377Simp remote-endpoint = 756279377Simp <&replicator3_out_port1>; 757279377Simp }; 758279377Simp }; 759279377Simp }; 760279377Simp }; 761279377Simp 762279377Simp ptm@0,e3c7c000 { 763279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 764279377Simp reg = <0 0xe3c7c000 0 0x1000>; 765279377Simp 766279377Simp clocks = <&clk_375m>; 767279377Simp clock-names = "apb_pclk"; 768279377Simp cpu = <&CPU0>; 769279377Simp port { 770279377Simp ptm0_out_port: endpoint { 771279377Simp remote-endpoint = <&funnel0_in_port0>; 772279377Simp }; 773279377Simp }; 774279377Simp }; 775279377Simp 776279377Simp ptm@0,e3c7d000 { 777279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 778279377Simp reg = <0 0xe3c7d000 0 0x1000>; 779279377Simp 780279377Simp clocks = <&clk_375m>; 781279377Simp clock-names = "apb_pclk"; 782279377Simp cpu = <&CPU1>; 783279377Simp port { 784279377Simp ptm1_out_port: endpoint { 785279377Simp remote-endpoint = <&funnel0_in_port1>; 786279377Simp }; 787279377Simp }; 788279377Simp }; 789279377Simp 790279377Simp ptm@0,e3c7e000 { 791279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 792279377Simp reg = <0 0xe3c7e000 0 0x1000>; 793279377Simp 794279377Simp clocks = <&clk_375m>; 795279377Simp clock-names = "apb_pclk"; 796279377Simp cpu = <&CPU2>; 797279377Simp port { 798279377Simp ptm2_out_port: endpoint { 799279377Simp remote-endpoint = <&funnel0_in_port2>; 800279377Simp }; 801279377Simp }; 802279377Simp }; 803279377Simp 804279377Simp ptm@0,e3c7f000 { 805279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 806279377Simp reg = <0 0xe3c7f000 0 0x1000>; 807279377Simp 808279377Simp clocks = <&clk_375m>; 809279377Simp clock-names = "apb_pclk"; 810279377Simp cpu = <&CPU3>; 811279377Simp port { 812279377Simp ptm3_out_port: endpoint { 813279377Simp remote-endpoint = <&funnel0_in_port3>; 814279377Simp }; 815279377Simp }; 816279377Simp }; 817279377Simp 818279377Simp ptm@0,e3cbc000 { 819279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 820279377Simp reg = <0 0xe3cbc000 0 0x1000>; 821279377Simp 822279377Simp clocks = <&clk_375m>; 823279377Simp clock-names = "apb_pclk"; 824279377Simp cpu = <&CPU4>; 825279377Simp port { 826279377Simp ptm4_out_port: endpoint { 827279377Simp remote-endpoint = <&funnel1_in_port0>; 828279377Simp }; 829279377Simp }; 830279377Simp }; 831279377Simp 832279377Simp ptm@0,e3cbd000 { 833279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 834279377Simp reg = <0 0xe3cbd000 0 0x1000>; 835279377Simp 836279377Simp clocks = <&clk_375m>; 837279377Simp clock-names = "apb_pclk"; 838279377Simp cpu = <&CPU5>; 839279377Simp port { 840279377Simp ptm5_out_port: endpoint { 841279377Simp remote-endpoint = <&funnel1_in_port1>; 842279377Simp }; 843279377Simp }; 844279377Simp }; 845279377Simp 846279377Simp ptm@0,e3cbe000 { 847279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 848279377Simp reg = <0 0xe3cbe000 0 0x1000>; 849279377Simp 850279377Simp clocks = <&clk_375m>; 851279377Simp clock-names = "apb_pclk"; 852279377Simp cpu = <&CPU6>; 853279377Simp port { 854279377Simp ptm6_out_port: endpoint { 855279377Simp remote-endpoint = <&funnel1_in_port2>; 856279377Simp }; 857279377Simp }; 858279377Simp }; 859279377Simp 860279377Simp ptm@0,e3cbf000 { 861279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 862279377Simp reg = <0 0xe3cbf000 0 0x1000>; 863279377Simp 864279377Simp clocks = <&clk_375m>; 865279377Simp clock-names = "apb_pclk"; 866279377Simp cpu = <&CPU7>; 867279377Simp port { 868279377Simp ptm7_out_port: endpoint { 869279377Simp remote-endpoint = <&funnel1_in_port3>; 870279377Simp }; 871279377Simp }; 872279377Simp }; 873279377Simp 874279377Simp ptm@0,e3cfc000 { 875279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 876279377Simp reg = <0 0xe3cfc000 0 0x1000>; 877279377Simp 878279377Simp clocks = <&clk_375m>; 879279377Simp clock-names = "apb_pclk"; 880279377Simp cpu = <&CPU8>; 881279377Simp port { 882279377Simp ptm8_out_port: endpoint { 883279377Simp remote-endpoint = <&funnel2_in_port0>; 884279377Simp }; 885279377Simp }; 886279377Simp }; 887279377Simp 888279377Simp ptm@0,e3cfd000 { 889279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 890279377Simp reg = <0 0xe3cfd000 0 0x1000>; 891279377Simp clocks = <&clk_375m>; 892279377Simp clock-names = "apb_pclk"; 893279377Simp cpu = <&CPU9>; 894279377Simp port { 895279377Simp ptm9_out_port: endpoint { 896279377Simp remote-endpoint = <&funnel2_in_port1>; 897279377Simp }; 898279377Simp }; 899279377Simp }; 900279377Simp 901279377Simp ptm@0,e3cfe000 { 902279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 903279377Simp reg = <0 0xe3cfe000 0 0x1000>; 904279377Simp 905279377Simp clocks = <&clk_375m>; 906279377Simp clock-names = "apb_pclk"; 907279377Simp cpu = <&CPU10>; 908279377Simp port { 909279377Simp ptm10_out_port: endpoint { 910279377Simp remote-endpoint = <&funnel2_in_port2>; 911279377Simp }; 912279377Simp }; 913279377Simp }; 914279377Simp 915279377Simp ptm@0,e3cff000 { 916279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 917279377Simp reg = <0 0xe3cff000 0 0x1000>; 918279377Simp 919279377Simp clocks = <&clk_375m>; 920279377Simp clock-names = "apb_pclk"; 921279377Simp cpu = <&CPU11>; 922279377Simp port { 923279377Simp ptm11_out_port: endpoint { 924279377Simp remote-endpoint = <&funnel2_in_port3>; 925279377Simp }; 926279377Simp }; 927279377Simp }; 928279377Simp 929279377Simp ptm@0,e3d3c000 { 930279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 931279377Simp reg = <0 0xe3d3c000 0 0x1000>; 932279377Simp 933279377Simp clocks = <&clk_375m>; 934279377Simp clock-names = "apb_pclk"; 935279377Simp cpu = <&CPU12>; 936279377Simp port { 937279377Simp ptm12_out_port: endpoint { 938279377Simp remote-endpoint = <&funnel3_in_port0>; 939279377Simp }; 940279377Simp }; 941279377Simp }; 942279377Simp 943279377Simp ptm@0,e3d3d000 { 944279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 945279377Simp reg = <0 0xe3d3d000 0 0x1000>; 946279377Simp 947279377Simp clocks = <&clk_375m>; 948279377Simp clock-names = "apb_pclk"; 949279377Simp cpu = <&CPU13>; 950279377Simp port { 951279377Simp ptm13_out_port: endpoint { 952279377Simp remote-endpoint = <&funnel3_in_port1>; 953279377Simp }; 954279377Simp }; 955279377Simp }; 956279377Simp 957279377Simp ptm@0,e3d3e000 { 958279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 959279377Simp reg = <0 0xe3d3e000 0 0x1000>; 960279377Simp 961279377Simp clocks = <&clk_375m>; 962279377Simp clock-names = "apb_pclk"; 963279377Simp cpu = <&CPU14>; 964279377Simp port { 965279377Simp ptm14_out_port: endpoint { 966279377Simp remote-endpoint = <&funnel3_in_port2>; 967279377Simp }; 968279377Simp }; 969279377Simp }; 970279377Simp 971279377Simp ptm@0,e3d3f000 { 972279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 973279377Simp reg = <0 0xe3d3f000 0 0x1000>; 974279377Simp 975279377Simp clocks = <&clk_375m>; 976279377Simp clock-names = "apb_pclk"; 977279377Simp cpu = <&CPU15>; 978279377Simp port { 979279377Simp ptm15_out_port: endpoint { 980279377Simp remote-endpoint = <&funnel3_in_port3>; 981279377Simp }; 982279377Simp }; 983279377Simp }; 984279377Simp}; 985