1279377Simp/* 2279377Simp * Hisilicon Ltd. HiP04 SoC 3279377Simp * 4279377Simp * Copyright (C) 2013-2014 Hisilicon Ltd. 5279377Simp * Copyright (C) 2013-2014 Linaro Ltd. 6279377Simp * 7279377Simp * Author: Haojian Zhuang <haojian.zhuang@linaro.org> 8279377Simp * 9279377Simp * This program is free software; you can redistribute it and/or modify 10279377Simp * it under the terms of the GNU General Public License version 2 as 11279377Simp * published by the Free Software Foundation. 12279377Simp */ 13279377Simp 14279377Simp/ { 15279377Simp /* memory bus is 64-bit */ 16279377Simp #address-cells = <2>; 17279377Simp #size-cells = <2>; 18279377Simp 19279377Simp aliases { 20279377Simp serial0 = &uart0; 21279377Simp }; 22279377Simp 23279377Simp bootwrapper { 24279377Simp compatible = "hisilicon,hip04-bootwrapper"; 25279377Simp boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>; 26279377Simp }; 27279377Simp 28279377Simp cpus { 29279377Simp #address-cells = <1>; 30279377Simp #size-cells = <0>; 31279377Simp 32279377Simp cpu-map { 33279377Simp cluster0 { 34279377Simp core0 { 35279377Simp cpu = <&CPU0>; 36279377Simp }; 37279377Simp core1 { 38279377Simp cpu = <&CPU1>; 39279377Simp }; 40279377Simp core2 { 41279377Simp cpu = <&CPU2>; 42279377Simp }; 43279377Simp core3 { 44279377Simp cpu = <&CPU3>; 45279377Simp }; 46279377Simp }; 47279377Simp cluster1 { 48279377Simp core0 { 49279377Simp cpu = <&CPU4>; 50279377Simp }; 51279377Simp core1 { 52279377Simp cpu = <&CPU5>; 53279377Simp }; 54279377Simp core2 { 55279377Simp cpu = <&CPU6>; 56279377Simp }; 57279377Simp core3 { 58279377Simp cpu = <&CPU7>; 59279377Simp }; 60279377Simp }; 61279377Simp cluster2 { 62279377Simp core0 { 63279377Simp cpu = <&CPU8>; 64279377Simp }; 65279377Simp core1 { 66279377Simp cpu = <&CPU9>; 67279377Simp }; 68279377Simp core2 { 69279377Simp cpu = <&CPU10>; 70279377Simp }; 71279377Simp core3 { 72279377Simp cpu = <&CPU11>; 73279377Simp }; 74279377Simp }; 75279377Simp cluster3 { 76279377Simp core0 { 77279377Simp cpu = <&CPU12>; 78279377Simp }; 79279377Simp core1 { 80279377Simp cpu = <&CPU13>; 81279377Simp }; 82279377Simp core2 { 83279377Simp cpu = <&CPU14>; 84279377Simp }; 85279377Simp core3 { 86279377Simp cpu = <&CPU15>; 87279377Simp }; 88279377Simp }; 89279377Simp }; 90279377Simp CPU0: cpu@0 { 91279377Simp device_type = "cpu"; 92279377Simp compatible = "arm,cortex-a15"; 93279377Simp reg = <0>; 94279377Simp }; 95279377Simp CPU1: cpu@1 { 96279377Simp device_type = "cpu"; 97279377Simp compatible = "arm,cortex-a15"; 98279377Simp reg = <1>; 99279377Simp }; 100279377Simp CPU2: cpu@2 { 101279377Simp device_type = "cpu"; 102279377Simp compatible = "arm,cortex-a15"; 103279377Simp reg = <2>; 104279377Simp }; 105279377Simp CPU3: cpu@3 { 106279377Simp device_type = "cpu"; 107279377Simp compatible = "arm,cortex-a15"; 108279377Simp reg = <3>; 109279377Simp }; 110279377Simp CPU4: cpu@100 { 111279377Simp device_type = "cpu"; 112279377Simp compatible = "arm,cortex-a15"; 113279377Simp reg = <0x100>; 114279377Simp }; 115279377Simp CPU5: cpu@101 { 116279377Simp device_type = "cpu"; 117279377Simp compatible = "arm,cortex-a15"; 118279377Simp reg = <0x101>; 119279377Simp }; 120279377Simp CPU6: cpu@102 { 121279377Simp device_type = "cpu"; 122279377Simp compatible = "arm,cortex-a15"; 123279377Simp reg = <0x102>; 124279377Simp }; 125279377Simp CPU7: cpu@103 { 126279377Simp device_type = "cpu"; 127279377Simp compatible = "arm,cortex-a15"; 128279377Simp reg = <0x103>; 129279377Simp }; 130279377Simp CPU8: cpu@200 { 131279377Simp device_type = "cpu"; 132279377Simp compatible = "arm,cortex-a15"; 133279377Simp reg = <0x200>; 134279377Simp }; 135279377Simp CPU9: cpu@201 { 136279377Simp device_type = "cpu"; 137279377Simp compatible = "arm,cortex-a15"; 138279377Simp reg = <0x201>; 139279377Simp }; 140279377Simp CPU10: cpu@202 { 141279377Simp device_type = "cpu"; 142279377Simp compatible = "arm,cortex-a15"; 143279377Simp reg = <0x202>; 144279377Simp }; 145279377Simp CPU11: cpu@203 { 146279377Simp device_type = "cpu"; 147279377Simp compatible = "arm,cortex-a15"; 148279377Simp reg = <0x203>; 149279377Simp }; 150279377Simp CPU12: cpu@300 { 151279377Simp device_type = "cpu"; 152279377Simp compatible = "arm,cortex-a15"; 153279377Simp reg = <0x300>; 154279377Simp }; 155279377Simp CPU13: cpu@301 { 156279377Simp device_type = "cpu"; 157279377Simp compatible = "arm,cortex-a15"; 158279377Simp reg = <0x301>; 159279377Simp }; 160279377Simp CPU14: cpu@302 { 161279377Simp device_type = "cpu"; 162279377Simp compatible = "arm,cortex-a15"; 163279377Simp reg = <0x302>; 164279377Simp }; 165279377Simp CPU15: cpu@303 { 166279377Simp device_type = "cpu"; 167279377Simp compatible = "arm,cortex-a15"; 168279377Simp reg = <0x303>; 169279377Simp }; 170279377Simp }; 171279377Simp 172279377Simp timer { 173279377Simp compatible = "arm,armv7-timer"; 174279377Simp interrupt-parent = <&gic>; 175279377Simp interrupts = <1 13 0xf08>, 176279377Simp <1 14 0xf08>, 177279377Simp <1 11 0xf08>, 178279377Simp <1 10 0xf08>; 179279377Simp }; 180279377Simp 181279377Simp clk_50m: clk_50m { 182279377Simp #clock-cells = <0>; 183279377Simp compatible = "fixed-clock"; 184279377Simp clock-frequency = <50000000>; 185279377Simp }; 186279377Simp 187279377Simp clk_168m: clk_168m { 188279377Simp #clock-cells = <0>; 189279377Simp compatible = "fixed-clock"; 190279377Simp clock-frequency = <168000000>; 191279377Simp }; 192279377Simp 193279377Simp clk_375m: clk_375m { 194279377Simp #clock-cells = <0>; 195279377Simp compatible = "fixed-clock"; 196279377Simp clock-frequency = <375000000>; 197279377Simp }; 198279377Simp 199279377Simp soc { 200279377Simp /* It's a 32-bit SoC. */ 201279377Simp #address-cells = <1>; 202279377Simp #size-cells = <1>; 203279377Simp compatible = "simple-bus"; 204279377Simp interrupt-parent = <&gic>; 205279377Simp ranges = <0 0 0xe0000000 0x10000000>; 206279377Simp 207279377Simp gic: interrupt-controller@c01000 { 208279377Simp compatible = "hisilicon,hip04-intc"; 209279377Simp #interrupt-cells = <3>; 210279377Simp #address-cells = <0>; 211279377Simp interrupt-controller; 212279377Simp interrupts = <1 9 0xf04>; 213279377Simp 214279377Simp reg = <0xc01000 0x1000>, <0xc02000 0x1000>, 215279377Simp <0xc04000 0x2000>, <0xc06000 0x2000>; 216279377Simp }; 217279377Simp 218279377Simp sysctrl: sysctrl { 219279377Simp compatible = "hisilicon,sysctrl"; 220279377Simp reg = <0x3e00000 0x00100000>; 221279377Simp }; 222279377Simp 223279377Simp fabric: fabric { 224279377Simp compatible = "hisilicon,hip04-fabric"; 225279377Simp reg = <0x302a000 0x1000>; 226279377Simp }; 227279377Simp 228279377Simp dual_timer0: dual_timer@3000000 { 229279377Simp compatible = "arm,sp804", "arm,primecell"; 230279377Simp reg = <0x3000000 0x1000>; 231279377Simp interrupts = <0 224 4>; 232279377Simp clocks = <&clk_50m>, <&clk_50m>; 233279377Simp clock-names = "apb_pclk"; 234279377Simp }; 235279377Simp 236279377Simp arm-pmu { 237279377Simp compatible = "arm,cortex-a15-pmu"; 238279377Simp interrupts = <0 64 4>, 239279377Simp <0 65 4>, 240279377Simp <0 66 4>, 241279377Simp <0 67 4>, 242279377Simp <0 68 4>, 243279377Simp <0 69 4>, 244279377Simp <0 70 4>, 245279377Simp <0 71 4>, 246279377Simp <0 72 4>, 247279377Simp <0 73 4>, 248279377Simp <0 74 4>, 249279377Simp <0 75 4>, 250279377Simp <0 76 4>, 251279377Simp <0 77 4>, 252279377Simp <0 78 4>, 253279377Simp <0 79 4>; 254279377Simp }; 255279377Simp 256279377Simp uart0: uart@4007000 { 257279377Simp compatible = "snps,dw-apb-uart"; 258279377Simp reg = <0x4007000 0x1000>; 259279377Simp interrupts = <0 381 4>; 260279377Simp clocks = <&clk_168m>; 261279377Simp clock-names = "uartclk"; 262279377Simp reg-shift = <2>; 263279377Simp status = "disabled"; 264279377Simp }; 265279377Simp 266279377Simp sata0: sata@a000000 { 267279377Simp compatible = "hisilicon,hisi-ahci"; 268279377Simp reg = <0xa000000 0x1000000>; 269279377Simp interrupts = <0 372 4>; 270279377Simp }; 271279377Simp 272279377Simp }; 273279377Simp 274279377Simp etb@0,e3c42000 { 275279377Simp compatible = "arm,coresight-etb10", "arm,primecell"; 276279377Simp reg = <0 0xe3c42000 0 0x1000>; 277279377Simp 278279377Simp clocks = <&clk_375m>; 279279377Simp clock-names = "apb_pclk"; 280279377Simp port { 281279377Simp etb0_in_port: endpoint@0 { 282279377Simp slave-mode; 283279377Simp remote-endpoint = <&replicator0_out_port0>; 284279377Simp }; 285279377Simp }; 286279377Simp }; 287279377Simp 288279377Simp etb@0,e3c82000 { 289279377Simp compatible = "arm,coresight-etb10", "arm,primecell"; 290279377Simp reg = <0 0xe3c82000 0 0x1000>; 291279377Simp 292279377Simp clocks = <&clk_375m>; 293279377Simp clock-names = "apb_pclk"; 294279377Simp port { 295279377Simp etb1_in_port: endpoint@0 { 296279377Simp slave-mode; 297279377Simp remote-endpoint = <&replicator1_out_port0>; 298279377Simp }; 299279377Simp }; 300279377Simp }; 301279377Simp 302279377Simp etb@0,e3cc2000 { 303279377Simp compatible = "arm,coresight-etb10", "arm,primecell"; 304279377Simp reg = <0 0xe3cc2000 0 0x1000>; 305279377Simp 306279377Simp clocks = <&clk_375m>; 307279377Simp clock-names = "apb_pclk"; 308279377Simp port { 309279377Simp etb2_in_port: endpoint@0 { 310279377Simp slave-mode; 311279377Simp remote-endpoint = <&replicator2_out_port0>; 312279377Simp }; 313279377Simp }; 314279377Simp }; 315279377Simp 316279377Simp etb@0,e3d02000 { 317279377Simp compatible = "arm,coresight-etb10", "arm,primecell"; 318279377Simp reg = <0 0xe3d02000 0 0x1000>; 319279377Simp 320279377Simp clocks = <&clk_375m>; 321279377Simp clock-names = "apb_pclk"; 322279377Simp port { 323279377Simp etb3_in_port: endpoint@0 { 324279377Simp slave-mode; 325279377Simp remote-endpoint = <&replicator3_out_port0>; 326279377Simp }; 327279377Simp }; 328279377Simp }; 329279377Simp 330279377Simp tpiu@0,e3c05000 { 331279377Simp compatible = "arm,coresight-tpiu", "arm,primecell"; 332279377Simp reg = <0 0xe3c05000 0 0x1000>; 333279377Simp 334279377Simp clocks = <&clk_375m>; 335279377Simp clock-names = "apb_pclk"; 336279377Simp port { 337279377Simp tpiu_in_port: endpoint@0 { 338279377Simp slave-mode; 339279377Simp remote-endpoint = <&funnel4_out_port0>; 340279377Simp }; 341279377Simp }; 342279377Simp }; 343279377Simp 344279377Simp replicator0 { 345279377Simp /* non-configurable replicators don't show up on the 346279377Simp * AMBA bus. As such no need to add "arm,primecell". 347279377Simp */ 348279377Simp compatible = "arm,coresight-replicator"; 349279377Simp 350279377Simp ports { 351279377Simp #address-cells = <1>; 352279377Simp #size-cells = <0>; 353279377Simp 354279377Simp /* replicator output ports */ 355279377Simp port@0 { 356279377Simp reg = <0>; 357279377Simp replicator0_out_port0: endpoint { 358279377Simp remote-endpoint = <&etb0_in_port>; 359279377Simp }; 360279377Simp }; 361279377Simp 362279377Simp port@1 { 363279377Simp reg = <1>; 364279377Simp replicator0_out_port1: endpoint { 365279377Simp remote-endpoint = <&funnel4_in_port0>; 366279377Simp }; 367279377Simp }; 368279377Simp 369279377Simp /* replicator input port */ 370279377Simp port@2 { 371279377Simp reg = <0>; 372279377Simp replicator0_in_port0: endpoint { 373279377Simp slave-mode; 374279377Simp remote-endpoint = <&funnel0_out_port0>; 375279377Simp }; 376279377Simp }; 377279377Simp }; 378279377Simp }; 379279377Simp 380279377Simp replicator1 { 381279377Simp /* non-configurable replicators don't show up on the 382279377Simp * AMBA bus. As such no need to add "arm,primecell". 383279377Simp */ 384279377Simp compatible = "arm,coresight-replicator"; 385279377Simp 386279377Simp ports { 387279377Simp #address-cells = <1>; 388279377Simp #size-cells = <0>; 389279377Simp 390279377Simp /* replicator output ports */ 391279377Simp port@0 { 392279377Simp reg = <0>; 393279377Simp replicator1_out_port0: endpoint { 394279377Simp remote-endpoint = <&etb1_in_port>; 395279377Simp }; 396279377Simp }; 397279377Simp 398279377Simp port@1 { 399279377Simp reg = <1>; 400279377Simp replicator1_out_port1: endpoint { 401279377Simp remote-endpoint = <&funnel4_in_port1>; 402279377Simp }; 403279377Simp }; 404279377Simp 405279377Simp /* replicator input port */ 406279377Simp port@2 { 407279377Simp reg = <0>; 408279377Simp replicator1_in_port0: endpoint { 409279377Simp slave-mode; 410279377Simp remote-endpoint = <&funnel1_out_port0>; 411279377Simp }; 412279377Simp }; 413279377Simp }; 414279377Simp }; 415279377Simp 416279377Simp replicator2 { 417279377Simp /* non-configurable replicators don't show up on the 418279377Simp * AMBA bus. As such no need to add "arm,primecell". 419279377Simp */ 420279377Simp compatible = "arm,coresight-replicator"; 421279377Simp 422279377Simp ports { 423279377Simp #address-cells = <1>; 424279377Simp #size-cells = <0>; 425279377Simp 426279377Simp /* replicator output ports */ 427279377Simp port@0 { 428279377Simp reg = <0>; 429279377Simp replicator2_out_port0: endpoint { 430279377Simp remote-endpoint = <&etb2_in_port>; 431279377Simp }; 432279377Simp }; 433279377Simp 434279377Simp port@1 { 435279377Simp reg = <1>; 436279377Simp replicator2_out_port1: endpoint { 437279377Simp remote-endpoint = <&funnel4_in_port2>; 438279377Simp }; 439279377Simp }; 440279377Simp 441279377Simp /* replicator input port */ 442279377Simp port@2 { 443279377Simp reg = <0>; 444279377Simp replicator2_in_port0: endpoint { 445279377Simp slave-mode; 446279377Simp remote-endpoint = <&funnel2_out_port0>; 447279377Simp }; 448279377Simp }; 449279377Simp }; 450279377Simp }; 451279377Simp 452279377Simp replicator3 { 453279377Simp /* non-configurable replicators don't show up on the 454279377Simp * AMBA bus. As such no need to add "arm,primecell". 455279377Simp */ 456279377Simp compatible = "arm,coresight-replicator"; 457279377Simp 458279377Simp ports { 459279377Simp #address-cells = <1>; 460279377Simp #size-cells = <0>; 461279377Simp 462279377Simp /* replicator output ports */ 463279377Simp port@0 { 464279377Simp reg = <0>; 465279377Simp replicator3_out_port0: endpoint { 466279377Simp remote-endpoint = <&etb3_in_port>; 467279377Simp }; 468279377Simp }; 469279377Simp 470279377Simp port@1 { 471279377Simp reg = <1>; 472279377Simp replicator3_out_port1: endpoint { 473279377Simp remote-endpoint = <&funnel4_in_port3>; 474279377Simp }; 475279377Simp }; 476279377Simp 477279377Simp /* replicator input port */ 478279377Simp port@2 { 479279377Simp reg = <0>; 480279377Simp replicator3_in_port0: endpoint { 481279377Simp slave-mode; 482279377Simp remote-endpoint = <&funnel3_out_port0>; 483279377Simp }; 484279377Simp }; 485279377Simp }; 486279377Simp }; 487279377Simp 488279377Simp funnel@0,e3c41000 { 489279377Simp compatible = "arm,coresight-funnel", "arm,primecell"; 490279377Simp reg = <0 0xe3c41000 0 0x1000>; 491279377Simp 492279377Simp clocks = <&clk_375m>; 493279377Simp clock-names = "apb_pclk"; 494279377Simp ports { 495279377Simp #address-cells = <1>; 496279377Simp #size-cells = <0>; 497279377Simp 498279377Simp /* funnel output port */ 499279377Simp port@0 { 500279377Simp reg = <0>; 501279377Simp funnel0_out_port0: endpoint { 502279377Simp remote-endpoint = 503279377Simp <&replicator0_in_port0>; 504279377Simp }; 505279377Simp }; 506279377Simp 507279377Simp /* funnel input ports */ 508279377Simp port@1 { 509279377Simp reg = <0>; 510279377Simp funnel0_in_port0: endpoint { 511279377Simp slave-mode; 512279377Simp remote-endpoint = <&ptm0_out_port>; 513279377Simp }; 514279377Simp }; 515279377Simp 516279377Simp port@2 { 517279377Simp reg = <1>; 518279377Simp funnel0_in_port1: endpoint { 519279377Simp slave-mode; 520279377Simp remote-endpoint = <&ptm1_out_port>; 521279377Simp }; 522279377Simp }; 523279377Simp 524279377Simp port@3 { 525279377Simp reg = <2>; 526279377Simp funnel0_in_port2: endpoint { 527279377Simp slave-mode; 528279377Simp remote-endpoint = <&ptm2_out_port>; 529279377Simp }; 530279377Simp }; 531279377Simp 532279377Simp port@4 { 533279377Simp reg = <3>; 534279377Simp funnel0_in_port3: endpoint { 535279377Simp slave-mode; 536279377Simp remote-endpoint = <&ptm3_out_port>; 537279377Simp }; 538279377Simp }; 539279377Simp }; 540279377Simp }; 541279377Simp 542279377Simp funnel@0,e3c81000 { 543279377Simp compatible = "arm,coresight-funnel", "arm,primecell"; 544279377Simp reg = <0 0xe3c81000 0 0x1000>; 545279377Simp 546279377Simp clocks = <&clk_375m>; 547279377Simp clock-names = "apb_pclk"; 548279377Simp ports { 549279377Simp #address-cells = <1>; 550279377Simp #size-cells = <0>; 551279377Simp 552279377Simp /* funnel output port */ 553279377Simp port@0 { 554279377Simp reg = <0>; 555279377Simp funnel1_out_port0: endpoint { 556279377Simp remote-endpoint = 557279377Simp <&replicator1_in_port0>; 558279377Simp }; 559279377Simp }; 560279377Simp 561279377Simp /* funnel input ports */ 562279377Simp port@1 { 563279377Simp reg = <0>; 564279377Simp funnel1_in_port0: endpoint { 565279377Simp slave-mode; 566279377Simp remote-endpoint = <&ptm4_out_port>; 567279377Simp }; 568279377Simp }; 569279377Simp 570279377Simp port@2 { 571279377Simp reg = <1>; 572279377Simp funnel1_in_port1: endpoint { 573279377Simp slave-mode; 574279377Simp remote-endpoint = <&ptm5_out_port>; 575279377Simp }; 576279377Simp }; 577279377Simp 578279377Simp port@3 { 579279377Simp reg = <2>; 580279377Simp funnel1_in_port2: endpoint { 581279377Simp slave-mode; 582279377Simp remote-endpoint = <&ptm6_out_port>; 583279377Simp }; 584279377Simp }; 585279377Simp 586279377Simp port@4 { 587279377Simp reg = <3>; 588279377Simp funnel1_in_port3: endpoint { 589279377Simp slave-mode; 590279377Simp remote-endpoint = <&ptm7_out_port>; 591279377Simp }; 592279377Simp }; 593279377Simp }; 594279377Simp }; 595279377Simp 596279377Simp funnel@0,e3cc1000 { 597279377Simp compatible = "arm,coresight-funnel", "arm,primecell"; 598279377Simp reg = <0 0xe3cc1000 0 0x1000>; 599279377Simp 600279377Simp clocks = <&clk_375m>; 601279377Simp clock-names = "apb_pclk"; 602279377Simp ports { 603279377Simp #address-cells = <1>; 604279377Simp #size-cells = <0>; 605279377Simp 606279377Simp /* funnel output port */ 607279377Simp port@0 { 608279377Simp reg = <0>; 609279377Simp funnel2_out_port0: endpoint { 610279377Simp remote-endpoint = 611279377Simp <&replicator2_in_port0>; 612279377Simp }; 613279377Simp }; 614279377Simp 615279377Simp /* funnel input ports */ 616279377Simp port@1 { 617279377Simp reg = <0>; 618279377Simp funnel2_in_port0: endpoint { 619279377Simp slave-mode; 620279377Simp remote-endpoint = <&ptm8_out_port>; 621279377Simp }; 622279377Simp }; 623279377Simp 624279377Simp port@2 { 625279377Simp reg = <1>; 626279377Simp funnel2_in_port1: endpoint { 627279377Simp slave-mode; 628279377Simp remote-endpoint = <&ptm9_out_port>; 629279377Simp }; 630279377Simp }; 631279377Simp 632279377Simp port@3 { 633279377Simp reg = <2>; 634279377Simp funnel2_in_port2: endpoint { 635279377Simp slave-mode; 636279377Simp remote-endpoint = <&ptm10_out_port>; 637279377Simp }; 638279377Simp }; 639279377Simp 640279377Simp port@4 { 641279377Simp reg = <3>; 642279377Simp funnel2_in_port3: endpoint { 643279377Simp slave-mode; 644279377Simp remote-endpoint = <&ptm11_out_port>; 645279377Simp }; 646279377Simp }; 647279377Simp }; 648279377Simp }; 649279377Simp 650279377Simp funnel@0,e3d01000 { 651279377Simp compatible = "arm,coresight-funnel", "arm,primecell"; 652279377Simp reg = <0 0xe3d01000 0 0x1000>; 653279377Simp 654279377Simp clocks = <&clk_375m>; 655279377Simp clock-names = "apb_pclk"; 656279377Simp ports { 657279377Simp #address-cells = <1>; 658279377Simp #size-cells = <0>; 659279377Simp 660279377Simp /* funnel output port */ 661279377Simp port@0 { 662279377Simp reg = <0>; 663279377Simp funnel3_out_port0: endpoint { 664279377Simp remote-endpoint = 665279377Simp <&replicator3_in_port0>; 666279377Simp }; 667279377Simp }; 668279377Simp 669279377Simp /* funnel input ports */ 670279377Simp port@1 { 671279377Simp reg = <0>; 672279377Simp funnel3_in_port0: endpoint { 673279377Simp slave-mode; 674279377Simp remote-endpoint = <&ptm12_out_port>; 675279377Simp }; 676279377Simp }; 677279377Simp 678279377Simp port@2 { 679279377Simp reg = <1>; 680279377Simp funnel3_in_port1: endpoint { 681279377Simp slave-mode; 682279377Simp remote-endpoint = <&ptm13_out_port>; 683279377Simp }; 684279377Simp }; 685279377Simp 686279377Simp port@3 { 687279377Simp reg = <2>; 688279377Simp funnel3_in_port2: endpoint { 689279377Simp slave-mode; 690279377Simp remote-endpoint = <&ptm14_out_port>; 691279377Simp }; 692279377Simp }; 693279377Simp 694279377Simp port@4 { 695279377Simp reg = <3>; 696279377Simp funnel3_in_port3: endpoint { 697279377Simp slave-mode; 698279377Simp remote-endpoint = <&ptm15_out_port>; 699279377Simp }; 700279377Simp }; 701279377Simp }; 702279377Simp }; 703279377Simp 704279377Simp funnel@0,e3c04000 { 705279377Simp compatible = "arm,coresight-funnel", "arm,primecell"; 706279377Simp reg = <0 0xe3c04000 0 0x1000>; 707279377Simp 708279377Simp clocks = <&clk_375m>; 709279377Simp clock-names = "apb_pclk"; 710279377Simp ports { 711279377Simp #address-cells = <1>; 712279377Simp #size-cells = <0>; 713279377Simp 714279377Simp /* funnel output port */ 715279377Simp port@0 { 716279377Simp reg = <0>; 717279377Simp funnel4_out_port0: endpoint { 718279377Simp remote-endpoint = <&tpiu_in_port>; 719279377Simp }; 720279377Simp }; 721279377Simp 722279377Simp /* funnel input ports */ 723279377Simp port@1 { 724279377Simp reg = <0>; 725279377Simp funnel4_in_port0: endpoint { 726279377Simp slave-mode; 727279377Simp remote-endpoint = 728279377Simp <&replicator0_out_port1>; 729279377Simp }; 730279377Simp }; 731279377Simp 732279377Simp port@2 { 733279377Simp reg = <1>; 734279377Simp funnel4_in_port1: endpoint { 735279377Simp slave-mode; 736279377Simp remote-endpoint = 737279377Simp <&replicator1_out_port1>; 738279377Simp }; 739279377Simp }; 740279377Simp 741279377Simp port@3 { 742279377Simp reg = <2>; 743279377Simp funnel4_in_port2: endpoint { 744279377Simp slave-mode; 745279377Simp remote-endpoint = 746279377Simp <&replicator2_out_port1>; 747279377Simp }; 748279377Simp }; 749279377Simp 750279377Simp port@4 { 751279377Simp reg = <3>; 752279377Simp funnel4_in_port3: endpoint { 753279377Simp slave-mode; 754279377Simp remote-endpoint = 755279377Simp <&replicator3_out_port1>; 756279377Simp }; 757279377Simp }; 758279377Simp }; 759279377Simp }; 760279377Simp 761279377Simp ptm@0,e3c7c000 { 762279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 763279377Simp reg = <0 0xe3c7c000 0 0x1000>; 764279377Simp 765279377Simp clocks = <&clk_375m>; 766279377Simp clock-names = "apb_pclk"; 767279377Simp cpu = <&CPU0>; 768279377Simp port { 769279377Simp ptm0_out_port: endpoint { 770279377Simp remote-endpoint = <&funnel0_in_port0>; 771279377Simp }; 772279377Simp }; 773279377Simp }; 774279377Simp 775279377Simp ptm@0,e3c7d000 { 776279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 777279377Simp reg = <0 0xe3c7d000 0 0x1000>; 778279377Simp 779279377Simp clocks = <&clk_375m>; 780279377Simp clock-names = "apb_pclk"; 781279377Simp cpu = <&CPU1>; 782279377Simp port { 783279377Simp ptm1_out_port: endpoint { 784279377Simp remote-endpoint = <&funnel0_in_port1>; 785279377Simp }; 786279377Simp }; 787279377Simp }; 788279377Simp 789279377Simp ptm@0,e3c7e000 { 790279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 791279377Simp reg = <0 0xe3c7e000 0 0x1000>; 792279377Simp 793279377Simp clocks = <&clk_375m>; 794279377Simp clock-names = "apb_pclk"; 795279377Simp cpu = <&CPU2>; 796279377Simp port { 797279377Simp ptm2_out_port: endpoint { 798279377Simp remote-endpoint = <&funnel0_in_port2>; 799279377Simp }; 800279377Simp }; 801279377Simp }; 802279377Simp 803279377Simp ptm@0,e3c7f000 { 804279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 805279377Simp reg = <0 0xe3c7f000 0 0x1000>; 806279377Simp 807279377Simp clocks = <&clk_375m>; 808279377Simp clock-names = "apb_pclk"; 809279377Simp cpu = <&CPU3>; 810279377Simp port { 811279377Simp ptm3_out_port: endpoint { 812279377Simp remote-endpoint = <&funnel0_in_port3>; 813279377Simp }; 814279377Simp }; 815279377Simp }; 816279377Simp 817279377Simp ptm@0,e3cbc000 { 818279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 819279377Simp reg = <0 0xe3cbc000 0 0x1000>; 820279377Simp 821279377Simp clocks = <&clk_375m>; 822279377Simp clock-names = "apb_pclk"; 823279377Simp cpu = <&CPU4>; 824279377Simp port { 825279377Simp ptm4_out_port: endpoint { 826279377Simp remote-endpoint = <&funnel1_in_port0>; 827279377Simp }; 828279377Simp }; 829279377Simp }; 830279377Simp 831279377Simp ptm@0,e3cbd000 { 832279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 833279377Simp reg = <0 0xe3cbd000 0 0x1000>; 834279377Simp 835279377Simp clocks = <&clk_375m>; 836279377Simp clock-names = "apb_pclk"; 837279377Simp cpu = <&CPU5>; 838279377Simp port { 839279377Simp ptm5_out_port: endpoint { 840279377Simp remote-endpoint = <&funnel1_in_port1>; 841279377Simp }; 842279377Simp }; 843279377Simp }; 844279377Simp 845279377Simp ptm@0,e3cbe000 { 846279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 847279377Simp reg = <0 0xe3cbe000 0 0x1000>; 848279377Simp 849279377Simp clocks = <&clk_375m>; 850279377Simp clock-names = "apb_pclk"; 851279377Simp cpu = <&CPU6>; 852279377Simp port { 853279377Simp ptm6_out_port: endpoint { 854279377Simp remote-endpoint = <&funnel1_in_port2>; 855279377Simp }; 856279377Simp }; 857279377Simp }; 858279377Simp 859279377Simp ptm@0,e3cbf000 { 860279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 861279377Simp reg = <0 0xe3cbf000 0 0x1000>; 862279377Simp 863279377Simp clocks = <&clk_375m>; 864279377Simp clock-names = "apb_pclk"; 865279377Simp cpu = <&CPU7>; 866279377Simp port { 867279377Simp ptm7_out_port: endpoint { 868279377Simp remote-endpoint = <&funnel1_in_port3>; 869279377Simp }; 870279377Simp }; 871279377Simp }; 872279377Simp 873279377Simp ptm@0,e3cfc000 { 874279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 875279377Simp reg = <0 0xe3cfc000 0 0x1000>; 876279377Simp 877279377Simp clocks = <&clk_375m>; 878279377Simp clock-names = "apb_pclk"; 879279377Simp cpu = <&CPU8>; 880279377Simp port { 881279377Simp ptm8_out_port: endpoint { 882279377Simp remote-endpoint = <&funnel2_in_port0>; 883279377Simp }; 884279377Simp }; 885279377Simp }; 886279377Simp 887279377Simp ptm@0,e3cfd000 { 888279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 889279377Simp reg = <0 0xe3cfd000 0 0x1000>; 890279377Simp clocks = <&clk_375m>; 891279377Simp clock-names = "apb_pclk"; 892279377Simp cpu = <&CPU9>; 893279377Simp port { 894279377Simp ptm9_out_port: endpoint { 895279377Simp remote-endpoint = <&funnel2_in_port1>; 896279377Simp }; 897279377Simp }; 898279377Simp }; 899279377Simp 900279377Simp ptm@0,e3cfe000 { 901279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 902279377Simp reg = <0 0xe3cfe000 0 0x1000>; 903279377Simp 904279377Simp clocks = <&clk_375m>; 905279377Simp clock-names = "apb_pclk"; 906279377Simp cpu = <&CPU10>; 907279377Simp port { 908279377Simp ptm10_out_port: endpoint { 909279377Simp remote-endpoint = <&funnel2_in_port2>; 910279377Simp }; 911279377Simp }; 912279377Simp }; 913279377Simp 914279377Simp ptm@0,e3cff000 { 915279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 916279377Simp reg = <0 0xe3cff000 0 0x1000>; 917279377Simp 918279377Simp clocks = <&clk_375m>; 919279377Simp clock-names = "apb_pclk"; 920279377Simp cpu = <&CPU11>; 921279377Simp port { 922279377Simp ptm11_out_port: endpoint { 923279377Simp remote-endpoint = <&funnel2_in_port3>; 924279377Simp }; 925279377Simp }; 926279377Simp }; 927279377Simp 928279377Simp ptm@0,e3d3c000 { 929279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 930279377Simp reg = <0 0xe3d3c000 0 0x1000>; 931279377Simp 932279377Simp clocks = <&clk_375m>; 933279377Simp clock-names = "apb_pclk"; 934279377Simp cpu = <&CPU12>; 935279377Simp port { 936279377Simp ptm12_out_port: endpoint { 937279377Simp remote-endpoint = <&funnel3_in_port0>; 938279377Simp }; 939279377Simp }; 940279377Simp }; 941279377Simp 942279377Simp ptm@0,e3d3d000 { 943279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 944279377Simp reg = <0 0xe3d3d000 0 0x1000>; 945279377Simp 946279377Simp clocks = <&clk_375m>; 947279377Simp clock-names = "apb_pclk"; 948279377Simp cpu = <&CPU13>; 949279377Simp port { 950279377Simp ptm13_out_port: endpoint { 951279377Simp remote-endpoint = <&funnel3_in_port1>; 952279377Simp }; 953279377Simp }; 954279377Simp }; 955279377Simp 956279377Simp ptm@0,e3d3e000 { 957279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 958279377Simp reg = <0 0xe3d3e000 0 0x1000>; 959279377Simp 960279377Simp clocks = <&clk_375m>; 961279377Simp clock-names = "apb_pclk"; 962279377Simp cpu = <&CPU14>; 963279377Simp port { 964279377Simp ptm14_out_port: endpoint { 965279377Simp remote-endpoint = <&funnel3_in_port2>; 966279377Simp }; 967279377Simp }; 968279377Simp }; 969279377Simp 970279377Simp ptm@0,e3d3f000 { 971279377Simp compatible = "arm,coresight-etm3x", "arm,primecell"; 972279377Simp reg = <0 0xe3d3f000 0 0x1000>; 973279377Simp 974279377Simp clocks = <&clk_375m>; 975279377Simp clock-names = "apb_pclk"; 976279377Simp cpu = <&CPU15>; 977279377Simp port { 978279377Simp ptm15_out_port: endpoint { 979279377Simp remote-endpoint = <&funnel3_in_port3>; 980279377Simp }; 981279377Simp }; 982279377Simp }; 983279377Simp}; 984