exynos5440.dtsi revision 279377
1123550Smaxim/* 2254400Sglebius * SAMSUNG EXYNOS5440 SoC device tree source 3123550Smaxim * 4123550Smaxim * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5123550Smaxim * http://www.samsung.com 6123550Smaxim * 7254400Sglebius * This program is free software; you can redistribute it and/or modify 8254400Sglebius * it under the terms of the GNU General Public License version 2 as 9123550Smaxim * published by the Free Software Foundation. 10254400Sglebius*/ 11123550Smaxim 12254400Sglebius#include <dt-bindings/clock/exynos5440.h> 13254400Sglebius#include "skeleton.dtsi" 14254400Sglebius 15254400Sglebius/ { 16254400Sglebius compatible = "samsung,exynos5440", "samsung,exynos5"; 17254400Sglebius 18254400Sglebius interrupt-parent = <&gic>; 19254400Sglebius 20254400Sglebius aliases { 21254400Sglebius serial0 = &serial_0; 22254400Sglebius serial1 = &serial_1; 23254400Sglebius spi0 = &spi_0; 24254400Sglebius tmuctrl0 = &tmuctrl_0; 25254400Sglebius tmuctrl1 = &tmuctrl_1; 26254400Sglebius tmuctrl2 = &tmuctrl_2; 27123550Smaxim }; 28254400Sglebius 29 clock: clock-controller@160000 { 30 compatible = "samsung,exynos5440-clock"; 31 reg = <0x160000 0x1000>; 32 #clock-cells = <1>; 33 }; 34 35 gic: interrupt-controller@2E0000 { 36 compatible = "arm,cortex-a15-gic"; 37 #interrupt-cells = <3>; 38 interrupt-controller; 39 reg = <0x2E1000 0x1000>, 40 <0x2E2000 0x1000>, 41 <0x2E4000 0x2000>, 42 <0x2E6000 0x2000>; 43 interrupts = <1 9 0xf04>; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a15"; 53 reg = <0>; 54 }; 55 cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a15"; 58 reg = <1>; 59 }; 60 cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a15"; 63 reg = <2>; 64 }; 65 cpu@3 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a15"; 68 reg = <3>; 69 }; 70 }; 71 72 arm-pmu { 73 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; 74 interrupts = <0 52 4>, 75 <0 53 4>, 76 <0 54 4>, 77 <0 55 4>; 78 }; 79 80 timer { 81 compatible = "arm,cortex-a15-timer", 82 "arm,armv7-timer"; 83 interrupts = <1 13 0xf08>, 84 <1 14 0xf08>, 85 <1 11 0xf08>, 86 <1 10 0xf08>; 87 clock-frequency = <50000000>; 88 }; 89 90 cpufreq@160000 { 91 compatible = "samsung,exynos5440-cpufreq"; 92 reg = <0x160000 0x1000>; 93 interrupts = <0 57 0>; 94 operating-points = < 95 /* KHz uV */ 96 1500000 1100000 97 1400000 1075000 98 1300000 1050000 99 1200000 1025000 100 1100000 1000000 101 1000000 975000 102 900000 950000 103 800000 925000 104 >; 105 }; 106 107 serial_0: serial@B0000 { 108 compatible = "samsung,exynos4210-uart"; 109 reg = <0xB0000 0x1000>; 110 interrupts = <0 2 0>; 111 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; 112 clock-names = "uart", "clk_uart_baud0"; 113 }; 114 115 serial_1: serial@C0000 { 116 compatible = "samsung,exynos4210-uart"; 117 reg = <0xC0000 0x1000>; 118 interrupts = <0 3 0>; 119 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; 120 clock-names = "uart", "clk_uart_baud0"; 121 }; 122 123 spi_0: spi@D0000 { 124 compatible = "samsung,exynos5440-spi"; 125 reg = <0xD0000 0x100>; 126 interrupts = <0 4 0>; 127 #address-cells = <1>; 128 #size-cells = <0>; 129 samsung,spi-src-clk = <0>; 130 num-cs = <1>; 131 clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>; 132 clock-names = "spi", "spi_busclk0"; 133 }; 134 135 pin_ctrl: pinctrl { 136 compatible = "samsung,exynos5440-pinctrl"; 137 reg = <0xE0000 0x1000>; 138 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, 139 <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>; 140 interrupt-controller; 141 #interrupt-cells = <2>; 142 #gpio-cells = <2>; 143 144 fan: fan { 145 samsung,exynos5440-pin-function = <1>; 146 }; 147 148 hdd_led0: hdd_led0 { 149 samsung,exynos5440-pin-function = <2>; 150 }; 151 152 hdd_led1: hdd_led1 { 153 samsung,exynos5440-pin-function = <3>; 154 }; 155 156 uart1: uart1 { 157 samsung,exynos5440-pin-function = <4>; 158 }; 159 }; 160 161 i2c@F0000 { 162 compatible = "samsung,exynos5440-i2c"; 163 reg = <0xF0000 0x1000>; 164 interrupts = <0 5 0>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 clocks = <&clock CLK_B_125>; 168 clock-names = "i2c"; 169 }; 170 171 i2c@100000 { 172 compatible = "samsung,exynos5440-i2c"; 173 reg = <0x100000 0x1000>; 174 interrupts = <0 6 0>; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 clocks = <&clock CLK_B_125>; 178 clock-names = "i2c"; 179 }; 180 181 watchdog@110000 { 182 compatible = "samsung,s3c2410-wdt"; 183 reg = <0x110000 0x1000>; 184 interrupts = <0 1 0>; 185 clocks = <&clock CLK_B_125>; 186 clock-names = "watchdog"; 187 }; 188 189 gmac: ethernet@00230000 { 190 compatible = "snps,dwmac-3.70a"; 191 reg = <0x00230000 0x8000>; 192 interrupt-parent = <&gic>; 193 interrupts = <0 31 4>; 194 interrupt-names = "macirq"; 195 phy-mode = "sgmii"; 196 clocks = <&clock CLK_GMAC0>; 197 clock-names = "stmmaceth"; 198 }; 199 200 amba { 201 #address-cells = <1>; 202 #size-cells = <1>; 203 compatible = "arm,amba-bus"; 204 interrupt-parent = <&gic>; 205 ranges; 206 }; 207 208 rtc { 209 compatible = "samsung,s3c6410-rtc"; 210 reg = <0x130000 0x1000>; 211 interrupts = <0 17 0>, <0 16 0>; 212 clocks = <&clock CLK_B_125>; 213 clock-names = "rtc"; 214 }; 215 216 tmuctrl_0: tmuctrl@160118 { 217 compatible = "samsung,exynos5440-tmu"; 218 reg = <0x160118 0x230>, <0x160368 0x10>; 219 interrupts = <0 58 0>; 220 clocks = <&clock CLK_B_125>; 221 clock-names = "tmu_apbif"; 222 }; 223 224 tmuctrl_1: tmuctrl@16011C { 225 compatible = "samsung,exynos5440-tmu"; 226 reg = <0x16011C 0x230>, <0x160368 0x10>; 227 interrupts = <0 58 0>; 228 clocks = <&clock CLK_B_125>; 229 clock-names = "tmu_apbif"; 230 }; 231 232 tmuctrl_2: tmuctrl@160120 { 233 compatible = "samsung,exynos5440-tmu"; 234 reg = <0x160120 0x230>, <0x160368 0x10>; 235 interrupts = <0 58 0>; 236 clocks = <&clock CLK_B_125>; 237 clock-names = "tmu_apbif"; 238 }; 239 240 sata@210000 { 241 compatible = "snps,exynos5440-ahci"; 242 reg = <0x210000 0x10000>; 243 interrupts = <0 30 0>; 244 clocks = <&clock CLK_SATA>; 245 clock-names = "sata"; 246 }; 247 248 ohci@220000 { 249 compatible = "samsung,exynos5440-ohci"; 250 reg = <0x220000 0x1000>; 251 interrupts = <0 29 0>; 252 clocks = <&clock CLK_USB>; 253 clock-names = "usbhost"; 254 }; 255 256 ehci@221000 { 257 compatible = "samsung,exynos5440-ehci"; 258 reg = <0x221000 0x1000>; 259 interrupts = <0 29 0>; 260 clocks = <&clock CLK_USB>; 261 clock-names = "usbhost"; 262 }; 263 264 pcie@290000 { 265 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; 266 reg = <0x290000 0x1000 267 0x270000 0x1000 268 0x271000 0x40>; 269 interrupts = <0 20 0>, <0 21 0>, <0 22 0>; 270 clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>; 271 clock-names = "pcie", "pcie_bus"; 272 #address-cells = <3>; 273 #size-cells = <2>; 274 device_type = "pci"; 275 ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ 276 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ 277 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ 278 #interrupt-cells = <1>; 279 interrupt-map-mask = <0 0 0 0>; 280 interrupt-map = <0x0 0 &gic 53>; 281 num-lanes = <4>; 282 status = "disabled"; 283 }; 284 285 pcie@2a0000 { 286 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; 287 reg = <0x2a0000 0x1000 288 0x272000 0x1000 289 0x271040 0x40>; 290 interrupts = <0 23 0>, <0 24 0>, <0 25 0>; 291 clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>; 292 clock-names = "pcie", "pcie_bus"; 293 #address-cells = <3>; 294 #size-cells = <2>; 295 device_type = "pci"; 296 ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ 297 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ 298 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ 299 #interrupt-cells = <1>; 300 interrupt-map-mask = <0 0 0 0>; 301 interrupt-map = <0x0 0 &gic 56>; 302 num-lanes = <4>; 303 status = "disabled"; 304 }; 305}; 306