1279377Simp/* 2279377Simp * SAMSUNG EXYNOS5420 SoC device tree source 3279377Simp * 4279377Simp * Copyright (c) 2013 Samsung Electronics Co., Ltd. 5279377Simp * http://www.samsung.com 6279377Simp * 7279377Simp * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. 8279377Simp * EXYNOS5420 based board files can include this file and provide 9279377Simp * values for board specfic bindings. 10279377Simp * 11279377Simp * This program is free software; you can redistribute it and/or modify 12279377Simp * it under the terms of the GNU General Public License version 2 as 13279377Simp * published by the Free Software Foundation. 14279377Simp */ 15279377Simp 16279377Simp#include <dt-bindings/clock/exynos5420.h> 17279377Simp#include "exynos5.dtsi" 18279377Simp 19279377Simp#include <dt-bindings/clock/exynos-audss-clk.h> 20279377Simp 21279377Simp/ { 22279377Simp compatible = "samsung,exynos5420", "samsung,exynos5"; 23279377Simp 24279377Simp aliases { 25279377Simp mshc0 = &mmc_0; 26279377Simp mshc1 = &mmc_1; 27279377Simp mshc2 = &mmc_2; 28279377Simp pinctrl0 = &pinctrl_0; 29279377Simp pinctrl1 = &pinctrl_1; 30279377Simp pinctrl2 = &pinctrl_2; 31279377Simp pinctrl3 = &pinctrl_3; 32279377Simp pinctrl4 = &pinctrl_4; 33279377Simp i2c0 = &i2c_0; 34279377Simp i2c1 = &i2c_1; 35279377Simp i2c2 = &i2c_2; 36279377Simp i2c3 = &i2c_3; 37279377Simp i2c4 = &hsi2c_4; 38279377Simp i2c5 = &hsi2c_5; 39279377Simp i2c6 = &hsi2c_6; 40279377Simp i2c7 = &hsi2c_7; 41279377Simp i2c8 = &hsi2c_8; 42279377Simp i2c9 = &hsi2c_9; 43279377Simp i2c10 = &hsi2c_10; 44279377Simp gsc0 = &gsc_0; 45279377Simp gsc1 = &gsc_1; 46279377Simp spi0 = &spi_0; 47279377Simp spi1 = &spi_1; 48279377Simp spi2 = &spi_2; 49279377Simp usbdrdphy0 = &usbdrd_phy0; 50279377Simp usbdrdphy1 = &usbdrd_phy1; 51279377Simp }; 52279377Simp 53279377Simp cpus { 54279377Simp #address-cells = <1>; 55279377Simp #size-cells = <0>; 56279377Simp 57279377Simp cpu0: cpu@0 { 58279377Simp device_type = "cpu"; 59279377Simp compatible = "arm,cortex-a15"; 60279377Simp reg = <0x0>; 61279377Simp clock-frequency = <1800000000>; 62279377Simp cci-control-port = <&cci_control1>; 63279377Simp }; 64279377Simp 65279377Simp cpu1: cpu@1 { 66279377Simp device_type = "cpu"; 67279377Simp compatible = "arm,cortex-a15"; 68279377Simp reg = <0x1>; 69279377Simp clock-frequency = <1800000000>; 70279377Simp cci-control-port = <&cci_control1>; 71279377Simp }; 72279377Simp 73279377Simp cpu2: cpu@2 { 74279377Simp device_type = "cpu"; 75279377Simp compatible = "arm,cortex-a15"; 76279377Simp reg = <0x2>; 77279377Simp clock-frequency = <1800000000>; 78279377Simp cci-control-port = <&cci_control1>; 79279377Simp }; 80279377Simp 81279377Simp cpu3: cpu@3 { 82279377Simp device_type = "cpu"; 83279377Simp compatible = "arm,cortex-a15"; 84279377Simp reg = <0x3>; 85279377Simp clock-frequency = <1800000000>; 86279377Simp cci-control-port = <&cci_control1>; 87279377Simp }; 88279377Simp 89279377Simp cpu4: cpu@100 { 90279377Simp device_type = "cpu"; 91279377Simp compatible = "arm,cortex-a7"; 92279377Simp reg = <0x100>; 93279377Simp clock-frequency = <1000000000>; 94279377Simp cci-control-port = <&cci_control0>; 95279377Simp }; 96279377Simp 97279377Simp cpu5: cpu@101 { 98279377Simp device_type = "cpu"; 99279377Simp compatible = "arm,cortex-a7"; 100279377Simp reg = <0x101>; 101279377Simp clock-frequency = <1000000000>; 102279377Simp cci-control-port = <&cci_control0>; 103279377Simp }; 104279377Simp 105279377Simp cpu6: cpu@102 { 106279377Simp device_type = "cpu"; 107279377Simp compatible = "arm,cortex-a7"; 108279377Simp reg = <0x102>; 109279377Simp clock-frequency = <1000000000>; 110279377Simp cci-control-port = <&cci_control0>; 111279377Simp }; 112279377Simp 113279377Simp cpu7: cpu@103 { 114279377Simp device_type = "cpu"; 115279377Simp compatible = "arm,cortex-a7"; 116279377Simp reg = <0x103>; 117279377Simp clock-frequency = <1000000000>; 118279377Simp cci-control-port = <&cci_control0>; 119279377Simp }; 120279377Simp }; 121279377Simp 122279377Simp cci: cci@10d20000 { 123279377Simp compatible = "arm,cci-400"; 124279377Simp #address-cells = <1>; 125279377Simp #size-cells = <1>; 126279377Simp reg = <0x10d20000 0x1000>; 127279377Simp ranges = <0x0 0x10d20000 0x6000>; 128279377Simp 129279377Simp cci_control0: slave-if@4000 { 130279377Simp compatible = "arm,cci-400-ctrl-if"; 131279377Simp interface-type = "ace"; 132279377Simp reg = <0x4000 0x1000>; 133279377Simp }; 134279377Simp cci_control1: slave-if@5000 { 135279377Simp compatible = "arm,cci-400-ctrl-if"; 136279377Simp interface-type = "ace"; 137279377Simp reg = <0x5000 0x1000>; 138279377Simp }; 139279377Simp }; 140279377Simp 141279377Simp sysram@02020000 { 142279377Simp compatible = "mmio-sram"; 143279377Simp reg = <0x02020000 0x54000>; 144279377Simp #address-cells = <1>; 145279377Simp #size-cells = <1>; 146279377Simp ranges = <0 0x02020000 0x54000>; 147279377Simp 148279377Simp smp-sysram@0 { 149279377Simp compatible = "samsung,exynos4210-sysram"; 150279377Simp reg = <0x0 0x1000>; 151279377Simp }; 152279377Simp 153279377Simp smp-sysram@53000 { 154279377Simp compatible = "samsung,exynos4210-sysram-ns"; 155279377Simp reg = <0x53000 0x1000>; 156279377Simp }; 157279377Simp }; 158279377Simp 159279377Simp clock: clock-controller@10010000 { 160279377Simp compatible = "samsung,exynos5420-clock"; 161279377Simp reg = <0x10010000 0x30000>; 162279377Simp #clock-cells = <1>; 163279377Simp }; 164279377Simp 165279377Simp clock_audss: audss-clock-controller@3810000 { 166279377Simp compatible = "samsung,exynos5420-audss-clock"; 167279377Simp reg = <0x03810000 0x0C>; 168279377Simp #clock-cells = <1>; 169279377Simp clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, 170279377Simp <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; 171279377Simp clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 172279377Simp }; 173279377Simp 174279377Simp mfc: codec@11000000 { 175279377Simp compatible = "samsung,mfc-v7"; 176279377Simp reg = <0x11000000 0x10000>; 177279377Simp interrupts = <0 96 0>; 178279377Simp clocks = <&clock CLK_MFC>; 179279377Simp clock-names = "mfc"; 180279377Simp power-domains = <&mfc_pd>; 181295436Sandrew iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; 182295436Sandrew iommu-names = "left", "right"; 183279377Simp }; 184279377Simp 185279377Simp mmc_0: mmc@12200000 { 186279377Simp compatible = "samsung,exynos5420-dw-mshc-smu"; 187279377Simp interrupts = <0 75 0>; 188279377Simp #address-cells = <1>; 189279377Simp #size-cells = <0>; 190279377Simp reg = <0x12200000 0x2000>; 191279377Simp clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; 192279377Simp clock-names = "biu", "ciu"; 193279377Simp fifo-depth = <0x40>; 194279377Simp status = "disabled"; 195279377Simp }; 196279377Simp 197279377Simp mmc_1: mmc@12210000 { 198279377Simp compatible = "samsung,exynos5420-dw-mshc-smu"; 199279377Simp interrupts = <0 76 0>; 200279377Simp #address-cells = <1>; 201279377Simp #size-cells = <0>; 202279377Simp reg = <0x12210000 0x2000>; 203279377Simp clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; 204279377Simp clock-names = "biu", "ciu"; 205279377Simp fifo-depth = <0x40>; 206279377Simp status = "disabled"; 207279377Simp }; 208279377Simp 209279377Simp mmc_2: mmc@12220000 { 210279377Simp compatible = "samsung,exynos5420-dw-mshc"; 211279377Simp interrupts = <0 77 0>; 212279377Simp #address-cells = <1>; 213279377Simp #size-cells = <0>; 214279377Simp reg = <0x12220000 0x1000>; 215279377Simp clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; 216279377Simp clock-names = "biu", "ciu"; 217279377Simp fifo-depth = <0x40>; 218279377Simp status = "disabled"; 219279377Simp }; 220279377Simp 221279377Simp mct: mct@101C0000 { 222279377Simp compatible = "samsung,exynos4210-mct"; 223279377Simp reg = <0x101C0000 0x800>; 224279377Simp interrupt-controller; 225295436Sandrew #interrupt-cells = <1>; 226279377Simp interrupt-parent = <&mct_map>; 227279377Simp interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, 228279377Simp <8>, <9>, <10>, <11>; 229279377Simp clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 230279377Simp clock-names = "fin_pll", "mct"; 231279377Simp 232279377Simp mct_map: mct-map { 233279377Simp #interrupt-cells = <1>; 234279377Simp #address-cells = <0>; 235279377Simp #size-cells = <0>; 236279377Simp interrupt-map = <0 &combiner 23 3>, 237279377Simp <1 &combiner 23 4>, 238279377Simp <2 &combiner 25 2>, 239279377Simp <3 &combiner 25 3>, 240279377Simp <4 &gic 0 120 0>, 241279377Simp <5 &gic 0 121 0>, 242279377Simp <6 &gic 0 122 0>, 243279377Simp <7 &gic 0 123 0>, 244279377Simp <8 &gic 0 128 0>, 245279377Simp <9 &gic 0 129 0>, 246279377Simp <10 &gic 0 130 0>, 247279377Simp <11 &gic 0 131 0>; 248279377Simp }; 249279377Simp }; 250279377Simp 251279377Simp gsc_pd: power-domain@10044000 { 252279377Simp compatible = "samsung,exynos4210-pd"; 253279377Simp reg = <0x10044000 0x20>; 254279377Simp #power-domain-cells = <0>; 255295436Sandrew clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; 256295436Sandrew clock-names = "asb0", "asb1"; 257279377Simp }; 258279377Simp 259279377Simp isp_pd: power-domain@10044020 { 260279377Simp compatible = "samsung,exynos4210-pd"; 261279377Simp reg = <0x10044020 0x20>; 262279377Simp #power-domain-cells = <0>; 263279377Simp }; 264279377Simp 265279377Simp mfc_pd: power-domain@10044060 { 266279377Simp compatible = "samsung,exynos4210-pd"; 267279377Simp reg = <0x10044060 0x20>; 268295436Sandrew clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>; 269295436Sandrew clock-names = "oscclk", "clk0"; 270279377Simp #power-domain-cells = <0>; 271279377Simp }; 272279377Simp 273279377Simp msc_pd: power-domain@10044120 { 274279377Simp compatible = "samsung,exynos4210-pd"; 275279377Simp reg = <0x10044120 0x20>; 276279377Simp #power-domain-cells = <0>; 277279377Simp }; 278279377Simp 279279377Simp disp_pd: power-domain@100440C0 { 280279377Simp compatible = "samsung,exynos4210-pd"; 281279377Simp reg = <0x100440C0 0x20>; 282279377Simp #power-domain-cells = <0>; 283295436Sandrew clocks = <&clock CLK_FIN_PLL>, 284279377Simp <&clock CLK_MOUT_USER_ACLK200_DISP1>, 285279377Simp <&clock CLK_MOUT_USER_ACLK300_DISP1>, 286295436Sandrew <&clock CLK_MOUT_USER_ACLK400_DISP1>, 287295436Sandrew <&clock CLK_FIMD1>, <&clock CLK_MIXER>; 288295436Sandrew clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; 289279377Simp }; 290279377Simp 291279377Simp pinctrl_0: pinctrl@13400000 { 292279377Simp compatible = "samsung,exynos5420-pinctrl"; 293279377Simp reg = <0x13400000 0x1000>; 294279377Simp interrupts = <0 45 0>; 295279377Simp 296279377Simp wakeup-interrupt-controller { 297279377Simp compatible = "samsung,exynos4210-wakeup-eint"; 298279377Simp interrupt-parent = <&gic>; 299279377Simp interrupts = <0 32 0>; 300279377Simp }; 301279377Simp }; 302279377Simp 303279377Simp pinctrl_1: pinctrl@13410000 { 304279377Simp compatible = "samsung,exynos5420-pinctrl"; 305279377Simp reg = <0x13410000 0x1000>; 306279377Simp interrupts = <0 78 0>; 307279377Simp }; 308279377Simp 309279377Simp pinctrl_2: pinctrl@14000000 { 310279377Simp compatible = "samsung,exynos5420-pinctrl"; 311279377Simp reg = <0x14000000 0x1000>; 312279377Simp interrupts = <0 46 0>; 313279377Simp }; 314279377Simp 315279377Simp pinctrl_3: pinctrl@14010000 { 316279377Simp compatible = "samsung,exynos5420-pinctrl"; 317279377Simp reg = <0x14010000 0x1000>; 318279377Simp interrupts = <0 50 0>; 319279377Simp }; 320279377Simp 321279377Simp pinctrl_4: pinctrl@03860000 { 322279377Simp compatible = "samsung,exynos5420-pinctrl"; 323279377Simp reg = <0x03860000 0x1000>; 324279377Simp interrupts = <0 47 0>; 325279377Simp }; 326279377Simp 327279377Simp amba { 328279377Simp #address-cells = <1>; 329279377Simp #size-cells = <1>; 330279377Simp compatible = "arm,amba-bus"; 331279377Simp interrupt-parent = <&gic>; 332279377Simp ranges; 333279377Simp 334279377Simp adma: adma@03880000 { 335279377Simp compatible = "arm,pl330", "arm,primecell"; 336279377Simp reg = <0x03880000 0x1000>; 337279377Simp interrupts = <0 110 0>; 338279377Simp clocks = <&clock_audss EXYNOS_ADMA>; 339279377Simp clock-names = "apb_pclk"; 340279377Simp #dma-cells = <1>; 341279377Simp #dma-channels = <6>; 342279377Simp #dma-requests = <16>; 343279377Simp }; 344279377Simp 345279377Simp pdma0: pdma@121A0000 { 346279377Simp compatible = "arm,pl330", "arm,primecell"; 347279377Simp reg = <0x121A0000 0x1000>; 348279377Simp interrupts = <0 34 0>; 349279377Simp clocks = <&clock CLK_PDMA0>; 350279377Simp clock-names = "apb_pclk"; 351279377Simp #dma-cells = <1>; 352279377Simp #dma-channels = <8>; 353279377Simp #dma-requests = <32>; 354279377Simp }; 355279377Simp 356279377Simp pdma1: pdma@121B0000 { 357279377Simp compatible = "arm,pl330", "arm,primecell"; 358279377Simp reg = <0x121B0000 0x1000>; 359279377Simp interrupts = <0 35 0>; 360279377Simp clocks = <&clock CLK_PDMA1>; 361279377Simp clock-names = "apb_pclk"; 362279377Simp #dma-cells = <1>; 363279377Simp #dma-channels = <8>; 364279377Simp #dma-requests = <32>; 365279377Simp }; 366279377Simp 367279377Simp mdma0: mdma@10800000 { 368279377Simp compatible = "arm,pl330", "arm,primecell"; 369279377Simp reg = <0x10800000 0x1000>; 370279377Simp interrupts = <0 33 0>; 371279377Simp clocks = <&clock CLK_MDMA0>; 372279377Simp clock-names = "apb_pclk"; 373279377Simp #dma-cells = <1>; 374279377Simp #dma-channels = <8>; 375279377Simp #dma-requests = <1>; 376279377Simp }; 377279377Simp 378279377Simp mdma1: mdma@11C10000 { 379279377Simp compatible = "arm,pl330", "arm,primecell"; 380279377Simp reg = <0x11C10000 0x1000>; 381279377Simp interrupts = <0 124 0>; 382279377Simp clocks = <&clock CLK_MDMA1>; 383279377Simp clock-names = "apb_pclk"; 384279377Simp #dma-cells = <1>; 385279377Simp #dma-channels = <8>; 386279377Simp #dma-requests = <1>; 387279377Simp /* 388279377Simp * MDMA1 can support both secure and non-secure 389279377Simp * AXI transactions. When this is enabled in the kernel 390279377Simp * for boards that run in secure mode, we are getting 391279377Simp * imprecise external aborts causing the kernel to oops. 392279377Simp */ 393279377Simp status = "disabled"; 394279377Simp }; 395279377Simp }; 396279377Simp 397279377Simp i2s0: i2s@03830000 { 398279377Simp compatible = "samsung,exynos5420-i2s"; 399279377Simp reg = <0x03830000 0x100>; 400279377Simp dmas = <&adma 0 401279377Simp &adma 2 402279377Simp &adma 1>; 403279377Simp dma-names = "tx", "rx", "tx-sec"; 404279377Simp clocks = <&clock_audss EXYNOS_I2S_BUS>, 405279377Simp <&clock_audss EXYNOS_I2S_BUS>, 406279377Simp <&clock_audss EXYNOS_SCLK_I2S>; 407279377Simp clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 408295436Sandrew #clock-cells = <1>; 409295436Sandrew clock-output-names = "i2s_cdclk0"; 410295436Sandrew #sound-dai-cells = <1>; 411279377Simp samsung,idma-addr = <0x03000000>; 412279377Simp pinctrl-names = "default"; 413279377Simp pinctrl-0 = <&i2s0_bus>; 414279377Simp status = "disabled"; 415279377Simp }; 416279377Simp 417279377Simp i2s1: i2s@12D60000 { 418279377Simp compatible = "samsung,exynos5420-i2s"; 419279377Simp reg = <0x12D60000 0x100>; 420279377Simp dmas = <&pdma1 12 421279377Simp &pdma1 11>; 422279377Simp dma-names = "tx", "rx"; 423279377Simp clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>; 424279377Simp clock-names = "iis", "i2s_opclk0"; 425295436Sandrew #clock-cells = <1>; 426295436Sandrew clock-output-names = "i2s_cdclk1"; 427295436Sandrew #sound-dai-cells = <1>; 428279377Simp pinctrl-names = "default"; 429279377Simp pinctrl-0 = <&i2s1_bus>; 430279377Simp status = "disabled"; 431279377Simp }; 432279377Simp 433279377Simp i2s2: i2s@12D70000 { 434279377Simp compatible = "samsung,exynos5420-i2s"; 435279377Simp reg = <0x12D70000 0x100>; 436279377Simp dmas = <&pdma0 12 437279377Simp &pdma0 11>; 438279377Simp dma-names = "tx", "rx"; 439279377Simp clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>; 440279377Simp clock-names = "iis", "i2s_opclk0"; 441295436Sandrew #clock-cells = <1>; 442295436Sandrew clock-output-names = "i2s_cdclk2"; 443295436Sandrew #sound-dai-cells = <1>; 444279377Simp pinctrl-names = "default"; 445279377Simp pinctrl-0 = <&i2s2_bus>; 446279377Simp status = "disabled"; 447279377Simp }; 448279377Simp 449279377Simp spi_0: spi@12d20000 { 450279377Simp compatible = "samsung,exynos4210-spi"; 451279377Simp reg = <0x12d20000 0x100>; 452279377Simp interrupts = <0 68 0>; 453279377Simp dmas = <&pdma0 5 454279377Simp &pdma0 4>; 455279377Simp dma-names = "tx", "rx"; 456279377Simp #address-cells = <1>; 457279377Simp #size-cells = <0>; 458279377Simp pinctrl-names = "default"; 459279377Simp pinctrl-0 = <&spi0_bus>; 460279377Simp clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 461279377Simp clock-names = "spi", "spi_busclk0"; 462279377Simp status = "disabled"; 463279377Simp }; 464279377Simp 465279377Simp spi_1: spi@12d30000 { 466279377Simp compatible = "samsung,exynos4210-spi"; 467279377Simp reg = <0x12d30000 0x100>; 468279377Simp interrupts = <0 69 0>; 469279377Simp dmas = <&pdma1 5 470279377Simp &pdma1 4>; 471279377Simp dma-names = "tx", "rx"; 472279377Simp #address-cells = <1>; 473279377Simp #size-cells = <0>; 474279377Simp pinctrl-names = "default"; 475279377Simp pinctrl-0 = <&spi1_bus>; 476279377Simp clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 477279377Simp clock-names = "spi", "spi_busclk0"; 478279377Simp status = "disabled"; 479279377Simp }; 480279377Simp 481279377Simp spi_2: spi@12d40000 { 482279377Simp compatible = "samsung,exynos4210-spi"; 483279377Simp reg = <0x12d40000 0x100>; 484279377Simp interrupts = <0 70 0>; 485279377Simp dmas = <&pdma0 7 486279377Simp &pdma0 6>; 487279377Simp dma-names = "tx", "rx"; 488279377Simp #address-cells = <1>; 489279377Simp #size-cells = <0>; 490279377Simp pinctrl-names = "default"; 491279377Simp pinctrl-0 = <&spi2_bus>; 492279377Simp clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 493279377Simp clock-names = "spi", "spi_busclk0"; 494279377Simp status = "disabled"; 495279377Simp }; 496279377Simp 497279377Simp pwm: pwm@12dd0000 { 498279377Simp compatible = "samsung,exynos4210-pwm"; 499279377Simp reg = <0x12dd0000 0x100>; 500279377Simp samsung,pwm-outputs = <0>, <1>, <2>, <3>; 501279377Simp #pwm-cells = <3>; 502279377Simp clocks = <&clock CLK_PWM>; 503279377Simp clock-names = "timers"; 504279377Simp }; 505279377Simp 506279377Simp dp_phy: video-phy@10040728 { 507279377Simp compatible = "samsung,exynos5420-dp-video-phy"; 508279377Simp samsung,pmu-syscon = <&pmu_system_controller>; 509279377Simp #phy-cells = <0>; 510279377Simp }; 511279377Simp 512279377Simp mipi_phy: video-phy@10040714 { 513279377Simp compatible = "samsung,s5pv210-mipi-video-phy"; 514295436Sandrew syscon = <&pmu_system_controller>; 515279377Simp #phy-cells = <1>; 516279377Simp }; 517279377Simp 518279377Simp dsi@14500000 { 519279377Simp compatible = "samsung,exynos5410-mipi-dsi"; 520279377Simp reg = <0x14500000 0x10000>; 521279377Simp interrupts = <0 82 0>; 522279377Simp phys = <&mipi_phy 1>; 523279377Simp phy-names = "dsim"; 524279377Simp clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; 525279377Simp clock-names = "bus_clk", "pll_clk"; 526279377Simp #address-cells = <1>; 527279377Simp #size-cells = <0>; 528279377Simp status = "disabled"; 529279377Simp }; 530279377Simp 531279377Simp adc: adc@12D10000 { 532279377Simp compatible = "samsung,exynos-adc-v2"; 533279377Simp reg = <0x12D10000 0x100>; 534279377Simp interrupts = <0 106 0>; 535279377Simp clocks = <&clock CLK_TSADC>; 536279377Simp clock-names = "adc"; 537279377Simp #io-channel-cells = <1>; 538279377Simp io-channel-ranges; 539279377Simp samsung,syscon-phandle = <&pmu_system_controller>; 540279377Simp status = "disabled"; 541279377Simp }; 542279377Simp 543279377Simp i2c_0: i2c@12C60000 { 544279377Simp compatible = "samsung,s3c2440-i2c"; 545279377Simp reg = <0x12C60000 0x100>; 546279377Simp interrupts = <0 56 0>; 547279377Simp #address-cells = <1>; 548279377Simp #size-cells = <0>; 549279377Simp clocks = <&clock CLK_I2C0>; 550279377Simp clock-names = "i2c"; 551279377Simp pinctrl-names = "default"; 552279377Simp pinctrl-0 = <&i2c0_bus>; 553279377Simp samsung,sysreg-phandle = <&sysreg_system_controller>; 554279377Simp status = "disabled"; 555279377Simp }; 556279377Simp 557279377Simp i2c_1: i2c@12C70000 { 558279377Simp compatible = "samsung,s3c2440-i2c"; 559279377Simp reg = <0x12C70000 0x100>; 560279377Simp interrupts = <0 57 0>; 561279377Simp #address-cells = <1>; 562279377Simp #size-cells = <0>; 563279377Simp clocks = <&clock CLK_I2C1>; 564279377Simp clock-names = "i2c"; 565279377Simp pinctrl-names = "default"; 566279377Simp pinctrl-0 = <&i2c1_bus>; 567279377Simp samsung,sysreg-phandle = <&sysreg_system_controller>; 568279377Simp status = "disabled"; 569279377Simp }; 570279377Simp 571279377Simp i2c_2: i2c@12C80000 { 572279377Simp compatible = "samsung,s3c2440-i2c"; 573279377Simp reg = <0x12C80000 0x100>; 574279377Simp interrupts = <0 58 0>; 575279377Simp #address-cells = <1>; 576279377Simp #size-cells = <0>; 577279377Simp clocks = <&clock CLK_I2C2>; 578279377Simp clock-names = "i2c"; 579279377Simp pinctrl-names = "default"; 580279377Simp pinctrl-0 = <&i2c2_bus>; 581279377Simp samsung,sysreg-phandle = <&sysreg_system_controller>; 582279377Simp status = "disabled"; 583279377Simp }; 584279377Simp 585279377Simp i2c_3: i2c@12C90000 { 586279377Simp compatible = "samsung,s3c2440-i2c"; 587279377Simp reg = <0x12C90000 0x100>; 588279377Simp interrupts = <0 59 0>; 589279377Simp #address-cells = <1>; 590279377Simp #size-cells = <0>; 591279377Simp clocks = <&clock CLK_I2C3>; 592279377Simp clock-names = "i2c"; 593279377Simp pinctrl-names = "default"; 594279377Simp pinctrl-0 = <&i2c3_bus>; 595279377Simp samsung,sysreg-phandle = <&sysreg_system_controller>; 596279377Simp status = "disabled"; 597279377Simp }; 598279377Simp 599279377Simp hsi2c_4: i2c@12CA0000 { 600279377Simp compatible = "samsung,exynos5-hsi2c"; 601279377Simp reg = <0x12CA0000 0x1000>; 602279377Simp interrupts = <0 60 0>; 603279377Simp #address-cells = <1>; 604279377Simp #size-cells = <0>; 605279377Simp pinctrl-names = "default"; 606279377Simp pinctrl-0 = <&i2c4_hs_bus>; 607279377Simp clocks = <&clock CLK_USI0>; 608279377Simp clock-names = "hsi2c"; 609279377Simp status = "disabled"; 610279377Simp }; 611279377Simp 612279377Simp hsi2c_5: i2c@12CB0000 { 613279377Simp compatible = "samsung,exynos5-hsi2c"; 614279377Simp reg = <0x12CB0000 0x1000>; 615279377Simp interrupts = <0 61 0>; 616279377Simp #address-cells = <1>; 617279377Simp #size-cells = <0>; 618279377Simp pinctrl-names = "default"; 619279377Simp pinctrl-0 = <&i2c5_hs_bus>; 620279377Simp clocks = <&clock CLK_USI1>; 621279377Simp clock-names = "hsi2c"; 622279377Simp status = "disabled"; 623279377Simp }; 624279377Simp 625279377Simp hsi2c_6: i2c@12CC0000 { 626279377Simp compatible = "samsung,exynos5-hsi2c"; 627279377Simp reg = <0x12CC0000 0x1000>; 628279377Simp interrupts = <0 62 0>; 629279377Simp #address-cells = <1>; 630279377Simp #size-cells = <0>; 631279377Simp pinctrl-names = "default"; 632279377Simp pinctrl-0 = <&i2c6_hs_bus>; 633279377Simp clocks = <&clock CLK_USI2>; 634279377Simp clock-names = "hsi2c"; 635279377Simp status = "disabled"; 636279377Simp }; 637279377Simp 638279377Simp hsi2c_7: i2c@12CD0000 { 639279377Simp compatible = "samsung,exynos5-hsi2c"; 640279377Simp reg = <0x12CD0000 0x1000>; 641279377Simp interrupts = <0 63 0>; 642279377Simp #address-cells = <1>; 643279377Simp #size-cells = <0>; 644279377Simp pinctrl-names = "default"; 645279377Simp pinctrl-0 = <&i2c7_hs_bus>; 646279377Simp clocks = <&clock CLK_USI3>; 647279377Simp clock-names = "hsi2c"; 648279377Simp status = "disabled"; 649279377Simp }; 650279377Simp 651279377Simp hsi2c_8: i2c@12E00000 { 652279377Simp compatible = "samsung,exynos5-hsi2c"; 653279377Simp reg = <0x12E00000 0x1000>; 654279377Simp interrupts = <0 87 0>; 655279377Simp #address-cells = <1>; 656279377Simp #size-cells = <0>; 657279377Simp pinctrl-names = "default"; 658279377Simp pinctrl-0 = <&i2c8_hs_bus>; 659279377Simp clocks = <&clock CLK_USI4>; 660279377Simp clock-names = "hsi2c"; 661279377Simp status = "disabled"; 662279377Simp }; 663279377Simp 664279377Simp hsi2c_9: i2c@12E10000 { 665279377Simp compatible = "samsung,exynos5-hsi2c"; 666279377Simp reg = <0x12E10000 0x1000>; 667279377Simp interrupts = <0 88 0>; 668279377Simp #address-cells = <1>; 669279377Simp #size-cells = <0>; 670279377Simp pinctrl-names = "default"; 671279377Simp pinctrl-0 = <&i2c9_hs_bus>; 672279377Simp clocks = <&clock CLK_USI5>; 673279377Simp clock-names = "hsi2c"; 674279377Simp status = "disabled"; 675279377Simp }; 676279377Simp 677279377Simp hsi2c_10: i2c@12E20000 { 678279377Simp compatible = "samsung,exynos5-hsi2c"; 679279377Simp reg = <0x12E20000 0x1000>; 680279377Simp interrupts = <0 203 0>; 681279377Simp #address-cells = <1>; 682279377Simp #size-cells = <0>; 683279377Simp pinctrl-names = "default"; 684279377Simp pinctrl-0 = <&i2c10_hs_bus>; 685279377Simp clocks = <&clock CLK_USI6>; 686279377Simp clock-names = "hsi2c"; 687279377Simp status = "disabled"; 688279377Simp }; 689279377Simp 690279377Simp hdmi: hdmi@14530000 { 691279377Simp compatible = "samsung,exynos5420-hdmi"; 692279377Simp reg = <0x14530000 0x70000>; 693279377Simp interrupts = <0 95 0>; 694279377Simp clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 695279377Simp <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 696279377Simp <&clock CLK_MOUT_HDMI>; 697279377Simp clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 698279377Simp "sclk_hdmiphy", "mout_hdmi"; 699279377Simp phy = <&hdmiphy>; 700279377Simp samsung,syscon-phandle = <&pmu_system_controller>; 701279377Simp status = "disabled"; 702279377Simp power-domains = <&disp_pd>; 703279377Simp }; 704279377Simp 705279377Simp hdmiphy: hdmiphy@145D0000 { 706279377Simp reg = <0x145D0000 0x20>; 707279377Simp }; 708279377Simp 709279377Simp mixer: mixer@14450000 { 710279377Simp compatible = "samsung,exynos5420-mixer"; 711279377Simp reg = <0x14450000 0x10000>; 712279377Simp interrupts = <0 94 0>; 713295436Sandrew clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 714295436Sandrew <&clock CLK_SCLK_HDMI>; 715295436Sandrew clock-names = "mixer", "hdmi", "sclk_hdmi"; 716279377Simp power-domains = <&disp_pd>; 717295436Sandrew iommus = <&sysmmu_tv>; 718279377Simp }; 719279377Simp 720295436Sandrew rotator: rotator@11C00000 { 721295436Sandrew compatible = "samsung,exynos5250-rotator"; 722295436Sandrew reg = <0x11C00000 0x64>; 723295436Sandrew interrupts = <0 84 0>; 724295436Sandrew clocks = <&clock CLK_ROTATOR>; 725295436Sandrew clock-names = "rotator"; 726295436Sandrew iommus = <&sysmmu_rotator>; 727295436Sandrew }; 728295436Sandrew 729279377Simp gsc_0: video-scaler@13e00000 { 730279377Simp compatible = "samsung,exynos5-gsc"; 731279377Simp reg = <0x13e00000 0x1000>; 732279377Simp interrupts = <0 85 0>; 733279377Simp clocks = <&clock CLK_GSCL0>; 734279377Simp clock-names = "gscl"; 735279377Simp power-domains = <&gsc_pd>; 736295436Sandrew iommus = <&sysmmu_gscl0>; 737279377Simp }; 738279377Simp 739279377Simp gsc_1: video-scaler@13e10000 { 740279377Simp compatible = "samsung,exynos5-gsc"; 741279377Simp reg = <0x13e10000 0x1000>; 742279377Simp interrupts = <0 86 0>; 743279377Simp clocks = <&clock CLK_GSCL1>; 744279377Simp clock-names = "gscl"; 745279377Simp power-domains = <&gsc_pd>; 746295436Sandrew iommus = <&sysmmu_gscl1>; 747279377Simp }; 748279377Simp 749295436Sandrew jpeg_0: jpeg@11F50000 { 750295436Sandrew compatible = "samsung,exynos5420-jpeg"; 751295436Sandrew reg = <0x11F50000 0x1000>; 752295436Sandrew interrupts = <0 89 0>; 753295436Sandrew clock-names = "jpeg"; 754295436Sandrew clocks = <&clock CLK_JPEG>; 755295436Sandrew iommus = <&sysmmu_jpeg0>; 756295436Sandrew }; 757295436Sandrew 758295436Sandrew jpeg_1: jpeg@11F60000 { 759295436Sandrew compatible = "samsung,exynos5420-jpeg"; 760295436Sandrew reg = <0x11F60000 0x1000>; 761295436Sandrew interrupts = <0 168 0>; 762295436Sandrew clock-names = "jpeg"; 763295436Sandrew clocks = <&clock CLK_JPEG2>; 764295436Sandrew iommus = <&sysmmu_jpeg1>; 765295436Sandrew }; 766295436Sandrew 767279377Simp pmu_system_controller: system-controller@10040000 { 768279377Simp compatible = "samsung,exynos5420-pmu", "syscon"; 769279377Simp reg = <0x10040000 0x5000>; 770279377Simp clock-names = "clkout16"; 771279377Simp clocks = <&clock CLK_FIN_PLL>; 772279377Simp #clock-cells = <1>; 773295436Sandrew interrupt-controller; 774295436Sandrew #interrupt-cells = <3>; 775295436Sandrew interrupt-parent = <&gic>; 776279377Simp }; 777279377Simp 778279377Simp sysreg_system_controller: syscon@10050000 { 779279377Simp compatible = "samsung,exynos5-sysreg", "syscon"; 780279377Simp reg = <0x10050000 0x5000>; 781279377Simp }; 782279377Simp 783279377Simp tmu_cpu0: tmu@10060000 { 784279377Simp compatible = "samsung,exynos5420-tmu"; 785279377Simp reg = <0x10060000 0x100>; 786279377Simp interrupts = <0 65 0>; 787279377Simp clocks = <&clock CLK_TMU>; 788279377Simp clock-names = "tmu_apbif"; 789295436Sandrew #include "exynos4412-tmu-sensor-conf.dtsi" 790279377Simp }; 791279377Simp 792279377Simp tmu_cpu1: tmu@10064000 { 793279377Simp compatible = "samsung,exynos5420-tmu"; 794279377Simp reg = <0x10064000 0x100>; 795279377Simp interrupts = <0 183 0>; 796279377Simp clocks = <&clock CLK_TMU>; 797279377Simp clock-names = "tmu_apbif"; 798295436Sandrew #include "exynos4412-tmu-sensor-conf.dtsi" 799279377Simp }; 800279377Simp 801279377Simp tmu_cpu2: tmu@10068000 { 802279377Simp compatible = "samsung,exynos5420-tmu-ext-triminfo"; 803279377Simp reg = <0x10068000 0x100>, <0x1006c000 0x4>; 804279377Simp interrupts = <0 184 0>; 805279377Simp clocks = <&clock CLK_TMU>, <&clock CLK_TMU>; 806279377Simp clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 807295436Sandrew #include "exynos4412-tmu-sensor-conf.dtsi" 808279377Simp }; 809279377Simp 810279377Simp tmu_cpu3: tmu@1006c000 { 811279377Simp compatible = "samsung,exynos5420-tmu-ext-triminfo"; 812279377Simp reg = <0x1006c000 0x100>, <0x100a0000 0x4>; 813279377Simp interrupts = <0 185 0>; 814279377Simp clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>; 815279377Simp clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 816295436Sandrew #include "exynos4412-tmu-sensor-conf.dtsi" 817279377Simp }; 818279377Simp 819279377Simp tmu_gpu: tmu@100a0000 { 820279377Simp compatible = "samsung,exynos5420-tmu-ext-triminfo"; 821279377Simp reg = <0x100a0000 0x100>, <0x10068000 0x4>; 822279377Simp interrupts = <0 215 0>; 823279377Simp clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>; 824279377Simp clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 825295436Sandrew #include "exynos4412-tmu-sensor-conf.dtsi" 826279377Simp }; 827279377Simp 828295436Sandrew thermal-zones { 829295436Sandrew cpu0_thermal: cpu0-thermal { 830295436Sandrew thermal-sensors = <&tmu_cpu0>; 831295436Sandrew #include "exynos5420-trip-points.dtsi" 832295436Sandrew }; 833295436Sandrew cpu1_thermal: cpu1-thermal { 834295436Sandrew thermal-sensors = <&tmu_cpu1>; 835295436Sandrew #include "exynos5420-trip-points.dtsi" 836295436Sandrew }; 837295436Sandrew cpu2_thermal: cpu2-thermal { 838295436Sandrew thermal-sensors = <&tmu_cpu2>; 839295436Sandrew #include "exynos5420-trip-points.dtsi" 840295436Sandrew }; 841295436Sandrew cpu3_thermal: cpu3-thermal { 842295436Sandrew thermal-sensors = <&tmu_cpu3>; 843295436Sandrew #include "exynos5420-trip-points.dtsi" 844295436Sandrew }; 845295436Sandrew gpu_thermal: gpu-thermal { 846295436Sandrew thermal-sensors = <&tmu_gpu>; 847295436Sandrew #include "exynos5420-trip-points.dtsi" 848295436Sandrew }; 849295436Sandrew }; 850295436Sandrew 851279377Simp watchdog: watchdog@101D0000 { 852279377Simp compatible = "samsung,exynos5420-wdt"; 853279377Simp reg = <0x101D0000 0x100>; 854279377Simp interrupts = <0 42 0>; 855279377Simp clocks = <&clock CLK_WDT>; 856279377Simp clock-names = "watchdog"; 857279377Simp samsung,syscon-phandle = <&pmu_system_controller>; 858279377Simp }; 859279377Simp 860279377Simp sss: sss@10830000 { 861279377Simp compatible = "samsung,exynos4210-secss"; 862279377Simp reg = <0x10830000 0x10000>; 863279377Simp interrupts = <0 112 0>; 864279377Simp clocks = <&clock CLK_SSS>; 865279377Simp clock-names = "secss"; 866279377Simp }; 867279377Simp 868279377Simp usbdrd3_0: usb@12000000 { 869279377Simp compatible = "samsung,exynos5250-dwusb3"; 870279377Simp clocks = <&clock CLK_USBD300>; 871279377Simp clock-names = "usbdrd30"; 872279377Simp #address-cells = <1>; 873279377Simp #size-cells = <1>; 874279377Simp ranges; 875279377Simp 876279377Simp usbdrd_dwc3_0: dwc3 { 877279377Simp compatible = "snps,dwc3"; 878279377Simp reg = <0x12000000 0x10000>; 879279377Simp interrupts = <0 72 0>; 880279377Simp phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; 881279377Simp phy-names = "usb2-phy", "usb3-phy"; 882279377Simp }; 883279377Simp }; 884279377Simp 885279377Simp usbdrd_phy0: phy@12100000 { 886279377Simp compatible = "samsung,exynos5420-usbdrd-phy"; 887279377Simp reg = <0x12100000 0x100>; 888279377Simp clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>; 889279377Simp clock-names = "phy", "ref"; 890279377Simp samsung,pmu-syscon = <&pmu_system_controller>; 891279377Simp #phy-cells = <1>; 892279377Simp }; 893279377Simp 894279377Simp usbdrd3_1: usb@12400000 { 895279377Simp compatible = "samsung,exynos5250-dwusb3"; 896279377Simp clocks = <&clock CLK_USBD301>; 897279377Simp clock-names = "usbdrd30"; 898279377Simp #address-cells = <1>; 899279377Simp #size-cells = <1>; 900279377Simp ranges; 901279377Simp 902279377Simp usbdrd_dwc3_1: dwc3 { 903279377Simp compatible = "snps,dwc3"; 904279377Simp reg = <0x12400000 0x10000>; 905279377Simp interrupts = <0 73 0>; 906279377Simp phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; 907279377Simp phy-names = "usb2-phy", "usb3-phy"; 908279377Simp }; 909279377Simp }; 910279377Simp 911279377Simp usbdrd_phy1: phy@12500000 { 912279377Simp compatible = "samsung,exynos5420-usbdrd-phy"; 913279377Simp reg = <0x12500000 0x100>; 914279377Simp clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>; 915279377Simp clock-names = "phy", "ref"; 916279377Simp samsung,pmu-syscon = <&pmu_system_controller>; 917279377Simp #phy-cells = <1>; 918279377Simp }; 919279377Simp 920279377Simp usbhost2: usb@12110000 { 921279377Simp compatible = "samsung,exynos4210-ehci"; 922279377Simp reg = <0x12110000 0x100>; 923279377Simp interrupts = <0 71 0>; 924279377Simp 925279377Simp clocks = <&clock CLK_USBH20>; 926279377Simp clock-names = "usbhost"; 927279377Simp #address-cells = <1>; 928279377Simp #size-cells = <0>; 929279377Simp port@0 { 930279377Simp reg = <0>; 931279377Simp phys = <&usb2_phy 1>; 932279377Simp }; 933279377Simp }; 934279377Simp 935279377Simp usbhost1: usb@12120000 { 936279377Simp compatible = "samsung,exynos4210-ohci"; 937279377Simp reg = <0x12120000 0x100>; 938279377Simp interrupts = <0 71 0>; 939279377Simp 940279377Simp clocks = <&clock CLK_USBH20>; 941279377Simp clock-names = "usbhost"; 942279377Simp #address-cells = <1>; 943279377Simp #size-cells = <0>; 944279377Simp port@0 { 945279377Simp reg = <0>; 946279377Simp phys = <&usb2_phy 1>; 947279377Simp }; 948279377Simp }; 949279377Simp 950279377Simp usb2_phy: phy@12130000 { 951279377Simp compatible = "samsung,exynos5250-usb2-phy"; 952279377Simp reg = <0x12130000 0x100>; 953279377Simp clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>; 954279377Simp clock-names = "phy", "ref"; 955279377Simp #phy-cells = <1>; 956279377Simp samsung,sysreg-phandle = <&sysreg_system_controller>; 957279377Simp samsung,pmureg-phandle = <&pmu_system_controller>; 958279377Simp }; 959295436Sandrew 960295436Sandrew sysmmu_g2dr: sysmmu@0x10A60000 { 961295436Sandrew compatible = "samsung,exynos-sysmmu"; 962295436Sandrew reg = <0x10A60000 0x1000>; 963295436Sandrew interrupt-parent = <&combiner>; 964295436Sandrew interrupts = <24 5>; 965295436Sandrew clock-names = "sysmmu", "master"; 966295436Sandrew clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 967295436Sandrew #iommu-cells = <0>; 968295436Sandrew }; 969295436Sandrew 970295436Sandrew sysmmu_g2dw: sysmmu@0x10A70000 { 971295436Sandrew compatible = "samsung,exynos-sysmmu"; 972295436Sandrew reg = <0x10A70000 0x1000>; 973295436Sandrew interrupt-parent = <&combiner>; 974295436Sandrew interrupts = <22 2>; 975295436Sandrew clock-names = "sysmmu", "master"; 976295436Sandrew clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 977295436Sandrew #iommu-cells = <0>; 978295436Sandrew }; 979295436Sandrew 980295436Sandrew sysmmu_tv: sysmmu@0x14650000 { 981295436Sandrew compatible = "samsung,exynos-sysmmu"; 982295436Sandrew reg = <0x14650000 0x1000>; 983295436Sandrew interrupt-parent = <&combiner>; 984295436Sandrew interrupts = <7 4>; 985295436Sandrew clock-names = "sysmmu", "master"; 986295436Sandrew clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>; 987295436Sandrew power-domains = <&disp_pd>; 988295436Sandrew #iommu-cells = <0>; 989295436Sandrew }; 990295436Sandrew 991295436Sandrew sysmmu_gscl0: sysmmu@0x13E80000 { 992295436Sandrew compatible = "samsung,exynos-sysmmu"; 993295436Sandrew reg = <0x13E80000 0x1000>; 994295436Sandrew interrupt-parent = <&combiner>; 995295436Sandrew interrupts = <2 0>; 996295436Sandrew clock-names = "sysmmu", "master"; 997295436Sandrew clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; 998295436Sandrew power-domains = <&gsc_pd>; 999295436Sandrew #iommu-cells = <0>; 1000295436Sandrew }; 1001295436Sandrew 1002295436Sandrew sysmmu_gscl1: sysmmu@0x13E90000 { 1003295436Sandrew compatible = "samsung,exynos-sysmmu"; 1004295436Sandrew reg = <0x13E90000 0x1000>; 1005295436Sandrew interrupt-parent = <&combiner>; 1006295436Sandrew interrupts = <2 2>; 1007295436Sandrew clock-names = "sysmmu", "master"; 1008295436Sandrew clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; 1009295436Sandrew power-domains = <&gsc_pd>; 1010295436Sandrew #iommu-cells = <0>; 1011295436Sandrew }; 1012295436Sandrew 1013295436Sandrew sysmmu_scaler0r: sysmmu@0x12880000 { 1014295436Sandrew compatible = "samsung,exynos-sysmmu"; 1015295436Sandrew reg = <0x12880000 0x1000>; 1016295436Sandrew interrupt-parent = <&combiner>; 1017295436Sandrew interrupts = <22 4>; 1018295436Sandrew clock-names = "sysmmu", "master"; 1019295436Sandrew clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; 1020295436Sandrew #iommu-cells = <0>; 1021295436Sandrew }; 1022295436Sandrew 1023295436Sandrew sysmmu_scaler1r: sysmmu@0x12890000 { 1024295436Sandrew compatible = "samsung,exynos-sysmmu"; 1025295436Sandrew reg = <0x12890000 0x1000>; 1026295436Sandrew interrupts = <0 186 0>; 1027295436Sandrew clock-names = "sysmmu", "master"; 1028295436Sandrew clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; 1029295436Sandrew #iommu-cells = <0>; 1030295436Sandrew }; 1031295436Sandrew 1032295436Sandrew sysmmu_scaler2r: sysmmu@0x128A0000 { 1033295436Sandrew compatible = "samsung,exynos-sysmmu"; 1034295436Sandrew reg = <0x128A0000 0x1000>; 1035295436Sandrew interrupts = <0 188 0>; 1036295436Sandrew clock-names = "sysmmu", "master"; 1037295436Sandrew clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; 1038295436Sandrew #iommu-cells = <0>; 1039295436Sandrew }; 1040295436Sandrew 1041295436Sandrew sysmmu_scaler0w: sysmmu@0x128C0000 { 1042295436Sandrew compatible = "samsung,exynos-sysmmu"; 1043295436Sandrew reg = <0x128C0000 0x1000>; 1044295436Sandrew interrupt-parent = <&combiner>; 1045295436Sandrew interrupts = <27 2>; 1046295436Sandrew clock-names = "sysmmu", "master"; 1047295436Sandrew clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; 1048295436Sandrew #iommu-cells = <0>; 1049295436Sandrew }; 1050295436Sandrew 1051295436Sandrew sysmmu_scaler1w: sysmmu@0x128D0000 { 1052295436Sandrew compatible = "samsung,exynos-sysmmu"; 1053295436Sandrew reg = <0x128D0000 0x1000>; 1054295436Sandrew interrupt-parent = <&combiner>; 1055295436Sandrew interrupts = <22 6>; 1056295436Sandrew clock-names = "sysmmu", "master"; 1057295436Sandrew clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; 1058295436Sandrew #iommu-cells = <0>; 1059295436Sandrew }; 1060295436Sandrew 1061295436Sandrew sysmmu_scaler2w: sysmmu@0x128E0000 { 1062295436Sandrew compatible = "samsung,exynos-sysmmu"; 1063295436Sandrew reg = <0x128E0000 0x1000>; 1064295436Sandrew interrupt-parent = <&combiner>; 1065295436Sandrew interrupts = <19 6>; 1066295436Sandrew clock-names = "sysmmu", "master"; 1067295436Sandrew clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; 1068295436Sandrew #iommu-cells = <0>; 1069295436Sandrew }; 1070295436Sandrew 1071295436Sandrew sysmmu_rotator: sysmmu@0x11D40000 { 1072295436Sandrew compatible = "samsung,exynos-sysmmu"; 1073295436Sandrew reg = <0x11D40000 0x1000>; 1074295436Sandrew interrupt-parent = <&combiner>; 1075295436Sandrew interrupts = <4 0>; 1076295436Sandrew clock-names = "sysmmu", "master"; 1077295436Sandrew clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; 1078295436Sandrew #iommu-cells = <0>; 1079295436Sandrew }; 1080295436Sandrew 1081295436Sandrew sysmmu_jpeg0: sysmmu@0x11F10000 { 1082295436Sandrew compatible = "samsung,exynos-sysmmu"; 1083295436Sandrew reg = <0x11F10000 0x1000>; 1084295436Sandrew interrupt-parent = <&combiner>; 1085295436Sandrew interrupts = <4 2>; 1086295436Sandrew clock-names = "sysmmu", "master"; 1087295436Sandrew clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; 1088295436Sandrew #iommu-cells = <0>; 1089295436Sandrew }; 1090295436Sandrew 1091295436Sandrew sysmmu_jpeg1: sysmmu@0x11F20000 { 1092295436Sandrew compatible = "samsung,exynos-sysmmu"; 1093295436Sandrew reg = <0x11F20000 0x1000>; 1094295436Sandrew interrupts = <0 169 0>; 1095295436Sandrew clock-names = "sysmmu", "master"; 1096295436Sandrew clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; 1097295436Sandrew #iommu-cells = <0>; 1098295436Sandrew }; 1099295436Sandrew 1100295436Sandrew sysmmu_mfc_l: sysmmu@0x11200000 { 1101295436Sandrew compatible = "samsung,exynos-sysmmu"; 1102295436Sandrew reg = <0x11200000 0x1000>; 1103295436Sandrew interrupt-parent = <&combiner>; 1104295436Sandrew interrupts = <6 2>; 1105295436Sandrew clock-names = "sysmmu", "master"; 1106295436Sandrew clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; 1107295436Sandrew power-domains = <&mfc_pd>; 1108295436Sandrew #iommu-cells = <0>; 1109295436Sandrew }; 1110295436Sandrew 1111295436Sandrew sysmmu_mfc_r: sysmmu@0x11210000 { 1112295436Sandrew compatible = "samsung,exynos-sysmmu"; 1113295436Sandrew reg = <0x11210000 0x1000>; 1114295436Sandrew interrupt-parent = <&combiner>; 1115295436Sandrew interrupts = <8 5>; 1116295436Sandrew clock-names = "sysmmu", "master"; 1117295436Sandrew clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; 1118295436Sandrew power-domains = <&mfc_pd>; 1119295436Sandrew #iommu-cells = <0>; 1120295436Sandrew }; 1121295436Sandrew 1122295436Sandrew sysmmu_fimd1_0: sysmmu@0x14640000 { 1123295436Sandrew compatible = "samsung,exynos-sysmmu"; 1124295436Sandrew reg = <0x14640000 0x1000>; 1125295436Sandrew interrupt-parent = <&combiner>; 1126295436Sandrew interrupts = <3 2>; 1127295436Sandrew clock-names = "sysmmu", "master"; 1128295436Sandrew clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>; 1129295436Sandrew power-domains = <&disp_pd>; 1130295436Sandrew #iommu-cells = <0>; 1131295436Sandrew }; 1132295436Sandrew 1133295436Sandrew sysmmu_fimd1_1: sysmmu@0x14680000 { 1134295436Sandrew compatible = "samsung,exynos-sysmmu"; 1135295436Sandrew reg = <0x14680000 0x1000>; 1136295436Sandrew interrupt-parent = <&combiner>; 1137295436Sandrew interrupts = <3 0>; 1138295436Sandrew clock-names = "sysmmu", "master"; 1139295436Sandrew clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>; 1140295436Sandrew power-domains = <&disp_pd>; 1141295436Sandrew #iommu-cells = <0>; 1142295436Sandrew }; 1143279377Simp}; 1144295436Sandrew 1145295436Sandrew&dp { 1146295436Sandrew clocks = <&clock CLK_DP1>; 1147295436Sandrew clock-names = "dp"; 1148295436Sandrew phys = <&dp_phy>; 1149295436Sandrew phy-names = "dp"; 1150295436Sandrew power-domains = <&disp_pd>; 1151295436Sandrew}; 1152295436Sandrew 1153295436Sandrew&fimd { 1154295436Sandrew clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 1155295436Sandrew clock-names = "sclk_fimd", "fimd"; 1156295436Sandrew power-domains = <&disp_pd>; 1157295436Sandrew iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>; 1158295436Sandrew iommu-names = "m0", "m1"; 1159295436Sandrew}; 1160295436Sandrew 1161295436Sandrew&rtc { 1162295436Sandrew clocks = <&clock CLK_RTC>; 1163295436Sandrew clock-names = "rtc"; 1164295436Sandrew interrupt-parent = <&pmu_system_controller>; 1165295436Sandrew status = "disabled"; 1166295436Sandrew}; 1167295436Sandrew 1168295436Sandrew&serial_0 { 1169295436Sandrew clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 1170295436Sandrew clock-names = "uart", "clk_uart_baud0"; 1171295436Sandrew}; 1172295436Sandrew 1173295436Sandrew&serial_1 { 1174295436Sandrew clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 1175295436Sandrew clock-names = "uart", "clk_uart_baud0"; 1176295436Sandrew}; 1177295436Sandrew 1178295436Sandrew&serial_2 { 1179295436Sandrew clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 1180295436Sandrew clock-names = "uart", "clk_uart_baud0"; 1181295436Sandrew}; 1182295436Sandrew 1183295436Sandrew&serial_3 { 1184295436Sandrew clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 1185295436Sandrew clock-names = "uart", "clk_uart_baud0"; 1186295436Sandrew}; 1187295436Sandrew 1188295436Sandrew#include "exynos5420-pinctrl.dtsi" 1189