1279377Simp/* 2279377Simp * SAMSUNG EXYNOS5250 SoC device tree source 3279377Simp * 4279377Simp * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5279377Simp * http://www.samsung.com 6279377Simp * 7279377Simp * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file. 8279377Simp * EXYNOS5250 based board files can include this file and provide 9279377Simp * values for board specfic bindings. 10279377Simp * 11279377Simp * Note: This file does not include device nodes for all the controllers in 12279377Simp * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases, 13279377Simp * additional nodes can be added to this file. 14279377Simp * 15279377Simp * This program is free software; you can redistribute it and/or modify 16279377Simp * it under the terms of the GNU General Public License version 2 as 17279377Simp * published by the Free Software Foundation. 18279377Simp*/ 19279377Simp 20279377Simp#include <dt-bindings/clock/exynos5250.h> 21279377Simp#include "exynos5.dtsi" 22295436Sandrew#include "exynos4-cpu-thermal.dtsi" 23279377Simp#include <dt-bindings/clock/exynos-audss-clk.h> 24279377Simp 25279377Simp/ { 26279377Simp compatible = "samsung,exynos5250", "samsung,exynos5"; 27279377Simp 28279377Simp aliases { 29279377Simp spi0 = &spi_0; 30279377Simp spi1 = &spi_1; 31279377Simp spi2 = &spi_2; 32279377Simp gsc0 = &gsc_0; 33279377Simp gsc1 = &gsc_1; 34279377Simp gsc2 = &gsc_2; 35279377Simp gsc3 = &gsc_3; 36279377Simp mshc0 = &mmc_0; 37279377Simp mshc1 = &mmc_1; 38279377Simp mshc2 = &mmc_2; 39279377Simp mshc3 = &mmc_3; 40279377Simp i2c0 = &i2c_0; 41279377Simp i2c1 = &i2c_1; 42279377Simp i2c2 = &i2c_2; 43279377Simp i2c3 = &i2c_3; 44279377Simp i2c4 = &i2c_4; 45279377Simp i2c5 = &i2c_5; 46279377Simp i2c6 = &i2c_6; 47279377Simp i2c7 = &i2c_7; 48279377Simp i2c8 = &i2c_8; 49279377Simp i2c9 = &i2c_9; 50279377Simp pinctrl0 = &pinctrl_0; 51279377Simp pinctrl1 = &pinctrl_1; 52279377Simp pinctrl2 = &pinctrl_2; 53279377Simp pinctrl3 = &pinctrl_3; 54279377Simp }; 55279377Simp 56279377Simp cpus { 57279377Simp #address-cells = <1>; 58279377Simp #size-cells = <0>; 59279377Simp 60295436Sandrew cpu0: cpu@0 { 61279377Simp device_type = "cpu"; 62279377Simp compatible = "arm,cortex-a15"; 63279377Simp reg = <0>; 64279377Simp clock-frequency = <1700000000>; 65295436Sandrew clocks = <&clock CLK_ARM_CLK>; 66295436Sandrew clock-names = "cpu"; 67295436Sandrew clock-latency = <140000>; 68295436Sandrew 69295436Sandrew operating-points = < 70295436Sandrew 1700000 1300000 71295436Sandrew 1600000 1250000 72295436Sandrew 1500000 1225000 73295436Sandrew 1400000 1200000 74295436Sandrew 1300000 1150000 75295436Sandrew 1200000 1125000 76295436Sandrew 1100000 1100000 77295436Sandrew 1000000 1075000 78295436Sandrew 900000 1050000 79295436Sandrew 800000 1025000 80295436Sandrew 700000 1012500 81295436Sandrew 600000 1000000 82295436Sandrew 500000 975000 83295436Sandrew 400000 950000 84295436Sandrew 300000 937500 85295436Sandrew 200000 925000 86295436Sandrew >; 87295436Sandrew cooling-min-level = <15>; 88295436Sandrew cooling-max-level = <9>; 89295436Sandrew #cooling-cells = <2>; /* min followed by max */ 90279377Simp }; 91279377Simp cpu@1 { 92279377Simp device_type = "cpu"; 93279377Simp compatible = "arm,cortex-a15"; 94279377Simp reg = <1>; 95279377Simp clock-frequency = <1700000000>; 96279377Simp }; 97279377Simp }; 98279377Simp 99279377Simp sysram@02020000 { 100279377Simp compatible = "mmio-sram"; 101279377Simp reg = <0x02020000 0x30000>; 102279377Simp #address-cells = <1>; 103279377Simp #size-cells = <1>; 104279377Simp ranges = <0 0x02020000 0x30000>; 105279377Simp 106279377Simp smp-sysram@0 { 107279377Simp compatible = "samsung,exynos4210-sysram"; 108279377Simp reg = <0x0 0x1000>; 109279377Simp }; 110279377Simp 111279377Simp smp-sysram@2f000 { 112279377Simp compatible = "samsung,exynos4210-sysram-ns"; 113279377Simp reg = <0x2f000 0x1000>; 114279377Simp }; 115279377Simp }; 116279377Simp 117279377Simp pd_gsc: gsc-power-domain@10044000 { 118279377Simp compatible = "samsung,exynos4210-pd"; 119279377Simp reg = <0x10044000 0x20>; 120279377Simp #power-domain-cells = <0>; 121279377Simp }; 122279377Simp 123279377Simp pd_mfc: mfc-power-domain@10044040 { 124279377Simp compatible = "samsung,exynos4210-pd"; 125279377Simp reg = <0x10044040 0x20>; 126279377Simp #power-domain-cells = <0>; 127279377Simp }; 128279377Simp 129295436Sandrew pd_disp1: disp1-power-domain@100440A0 { 130295436Sandrew compatible = "samsung,exynos4210-pd"; 131295436Sandrew reg = <0x100440A0 0x20>; 132295436Sandrew #power-domain-cells = <0>; 133295436Sandrew clocks = <&clock CLK_FIN_PLL>, 134295436Sandrew <&clock CLK_MOUT_ACLK200_DISP1_SUB>, 135295436Sandrew <&clock CLK_MOUT_ACLK300_DISP1_SUB>; 136295436Sandrew clock-names = "oscclk", "clk0", "clk1"; 137295436Sandrew }; 138295436Sandrew 139279377Simp clock: clock-controller@10010000 { 140279377Simp compatible = "samsung,exynos5250-clock"; 141279377Simp reg = <0x10010000 0x30000>; 142279377Simp #clock-cells = <1>; 143279377Simp }; 144279377Simp 145279377Simp clock_audss: audss-clock-controller@3810000 { 146279377Simp compatible = "samsung,exynos5250-audss-clock"; 147279377Simp reg = <0x03810000 0x0C>; 148279377Simp #clock-cells = <1>; 149279377Simp clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, 150279377Simp <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; 151279377Simp clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 152279377Simp }; 153279377Simp 154279377Simp timer { 155279377Simp compatible = "arm,armv7-timer"; 156279377Simp interrupts = <1 13 0xf08>, 157279377Simp <1 14 0xf08>, 158279377Simp <1 11 0xf08>, 159279377Simp <1 10 0xf08>; 160279377Simp /* Unfortunately we need this since some versions of U-Boot 161279377Simp * on Exynos don't set the CNTFRQ register, so we need the 162279377Simp * value from DT. 163279377Simp */ 164279377Simp clock-frequency = <24000000>; 165279377Simp }; 166279377Simp 167279377Simp mct@101C0000 { 168279377Simp compatible = "samsung,exynos4210-mct"; 169279377Simp reg = <0x101C0000 0x800>; 170279377Simp interrupt-controller; 171295436Sandrew #interrupt-cells = <2>; 172279377Simp interrupt-parent = <&mct_map>; 173279377Simp interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 174279377Simp <4 0>, <5 0>; 175279377Simp clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 176279377Simp clock-names = "fin_pll", "mct"; 177279377Simp 178279377Simp mct_map: mct-map { 179279377Simp #interrupt-cells = <2>; 180279377Simp #address-cells = <0>; 181279377Simp #size-cells = <0>; 182279377Simp interrupt-map = <0x0 0 &combiner 23 3>, 183279377Simp <0x1 0 &combiner 23 4>, 184279377Simp <0x2 0 &combiner 25 2>, 185279377Simp <0x3 0 &combiner 25 3>, 186279377Simp <0x4 0 &gic 0 120 0>, 187279377Simp <0x5 0 &gic 0 121 0>; 188279377Simp }; 189279377Simp }; 190279377Simp 191279377Simp pmu { 192279377Simp compatible = "arm,cortex-a15-pmu"; 193279377Simp interrupt-parent = <&combiner>; 194279377Simp interrupts = <1 2>, <22 4>; 195279377Simp }; 196279377Simp 197279377Simp pinctrl_0: pinctrl@11400000 { 198279377Simp compatible = "samsung,exynos5250-pinctrl"; 199279377Simp reg = <0x11400000 0x1000>; 200279377Simp interrupts = <0 46 0>; 201279377Simp 202279377Simp wakup_eint: wakeup-interrupt-controller { 203279377Simp compatible = "samsung,exynos4210-wakeup-eint"; 204279377Simp interrupt-parent = <&gic>; 205279377Simp interrupts = <0 32 0>; 206279377Simp }; 207279377Simp }; 208279377Simp 209279377Simp pinctrl_1: pinctrl@13400000 { 210279377Simp compatible = "samsung,exynos5250-pinctrl"; 211279377Simp reg = <0x13400000 0x1000>; 212279377Simp interrupts = <0 45 0>; 213279377Simp }; 214279377Simp 215279377Simp pinctrl_2: pinctrl@10d10000 { 216279377Simp compatible = "samsung,exynos5250-pinctrl"; 217279377Simp reg = <0x10d10000 0x1000>; 218279377Simp interrupts = <0 50 0>; 219279377Simp }; 220279377Simp 221279377Simp pinctrl_3: pinctrl@03860000 { 222279377Simp compatible = "samsung,exynos5250-pinctrl"; 223279377Simp reg = <0x03860000 0x1000>; 224279377Simp interrupts = <0 47 0>; 225279377Simp }; 226279377Simp 227279377Simp pmu_system_controller: system-controller@10040000 { 228279377Simp compatible = "samsung,exynos5250-pmu", "syscon"; 229279377Simp reg = <0x10040000 0x5000>; 230279377Simp clock-names = "clkout16"; 231279377Simp clocks = <&clock CLK_FIN_PLL>; 232279377Simp #clock-cells = <1>; 233295436Sandrew interrupt-controller; 234295436Sandrew #interrupt-cells = <3>; 235295436Sandrew interrupt-parent = <&gic>; 236279377Simp }; 237279377Simp 238279377Simp sysreg_system_controller: syscon@10050000 { 239279377Simp compatible = "samsung,exynos5-sysreg", "syscon"; 240279377Simp reg = <0x10050000 0x5000>; 241279377Simp }; 242279377Simp 243279377Simp watchdog@101D0000 { 244279377Simp compatible = "samsung,exynos5250-wdt"; 245279377Simp reg = <0x101D0000 0x100>; 246279377Simp interrupts = <0 42 0>; 247279377Simp clocks = <&clock CLK_WDT>; 248279377Simp clock-names = "watchdog"; 249279377Simp samsung,syscon-phandle = <&pmu_system_controller>; 250279377Simp }; 251279377Simp 252279377Simp g2d@10850000 { 253279377Simp compatible = "samsung,exynos5250-g2d"; 254279377Simp reg = <0x10850000 0x1000>; 255279377Simp interrupts = <0 91 0>; 256279377Simp clocks = <&clock CLK_G2D>; 257279377Simp clock-names = "fimg2d"; 258295436Sandrew iommus = <&sysmmu_g2d>; 259279377Simp }; 260279377Simp 261279377Simp mfc: codec@11000000 { 262279377Simp compatible = "samsung,mfc-v6"; 263279377Simp reg = <0x11000000 0x10000>; 264279377Simp interrupts = <0 96 0>; 265279377Simp power-domains = <&pd_mfc>; 266279377Simp clocks = <&clock CLK_MFC>; 267279377Simp clock-names = "mfc"; 268295436Sandrew iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; 269295436Sandrew iommu-names = "left", "right"; 270279377Simp }; 271279377Simp 272295436Sandrew rotator: rotator@11C00000 { 273295436Sandrew compatible = "samsung,exynos5250-rotator"; 274295436Sandrew reg = <0x11C00000 0x64>; 275295436Sandrew interrupts = <0 84 0>; 276295436Sandrew clocks = <&clock CLK_ROTATOR>; 277295436Sandrew clock-names = "rotator"; 278295436Sandrew iommus = <&sysmmu_rotator>; 279279377Simp }; 280279377Simp 281295436Sandrew tmu: tmu@10060000 { 282279377Simp compatible = "samsung,exynos5250-tmu"; 283279377Simp reg = <0x10060000 0x100>; 284279377Simp interrupts = <0 65 0>; 285279377Simp clocks = <&clock CLK_TMU>; 286279377Simp clock-names = "tmu_apbif"; 287295436Sandrew #include "exynos4412-tmu-sensor-conf.dtsi" 288279377Simp }; 289279377Simp 290295436Sandrew thermal-zones { 291295436Sandrew cpu_thermal: cpu-thermal { 292295436Sandrew polling-delay-passive = <0>; 293295436Sandrew polling-delay = <0>; 294295436Sandrew thermal-sensors = <&tmu 0>; 295279377Simp 296295436Sandrew cooling-maps { 297295436Sandrew map0 { 298295436Sandrew /* Corresponds to 800MHz at freq_table */ 299295436Sandrew cooling-device = <&cpu0 9 9>; 300295436Sandrew }; 301295436Sandrew map1 { 302295436Sandrew /* Corresponds to 200MHz at freq_table */ 303295436Sandrew cooling-device = <&cpu0 15 15>; 304295436Sandrew }; 305295436Sandrew }; 306295436Sandrew }; 307279377Simp }; 308279377Simp 309279377Simp sata: sata@122F0000 { 310279377Simp compatible = "snps,dwc-ahci"; 311279377Simp samsung,sata-freq = <66>; 312279377Simp reg = <0x122F0000 0x1ff>; 313279377Simp interrupts = <0 115 0>; 314279377Simp clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; 315279377Simp clock-names = "sata", "sclk_sata"; 316279377Simp phys = <&sata_phy>; 317279377Simp phy-names = "sata-phy"; 318279377Simp status = "disabled"; 319279377Simp }; 320279377Simp 321279377Simp sata_phy: sata-phy@12170000 { 322279377Simp compatible = "samsung,exynos5250-sata-phy"; 323279377Simp reg = <0x12170000 0x1ff>; 324279377Simp clocks = <&clock CLK_SATA_PHYCTRL>; 325279377Simp clock-names = "sata_phyctrl"; 326279377Simp #phy-cells = <0>; 327279377Simp samsung,syscon-phandle = <&pmu_system_controller>; 328279377Simp status = "disabled"; 329279377Simp }; 330279377Simp 331279377Simp i2c_0: i2c@12C60000 { 332279377Simp compatible = "samsung,s3c2440-i2c"; 333279377Simp reg = <0x12C60000 0x100>; 334279377Simp interrupts = <0 56 0>; 335279377Simp #address-cells = <1>; 336279377Simp #size-cells = <0>; 337279377Simp clocks = <&clock CLK_I2C0>; 338279377Simp clock-names = "i2c"; 339279377Simp pinctrl-names = "default"; 340279377Simp pinctrl-0 = <&i2c0_bus>; 341279377Simp samsung,sysreg-phandle = <&sysreg_system_controller>; 342279377Simp status = "disabled"; 343279377Simp }; 344279377Simp 345279377Simp i2c_1: i2c@12C70000 { 346279377Simp compatible = "samsung,s3c2440-i2c"; 347279377Simp reg = <0x12C70000 0x100>; 348279377Simp interrupts = <0 57 0>; 349279377Simp #address-cells = <1>; 350279377Simp #size-cells = <0>; 351279377Simp clocks = <&clock CLK_I2C1>; 352279377Simp clock-names = "i2c"; 353279377Simp pinctrl-names = "default"; 354279377Simp pinctrl-0 = <&i2c1_bus>; 355279377Simp samsung,sysreg-phandle = <&sysreg_system_controller>; 356279377Simp status = "disabled"; 357279377Simp }; 358279377Simp 359279377Simp i2c_2: i2c@12C80000 { 360279377Simp compatible = "samsung,s3c2440-i2c"; 361279377Simp reg = <0x12C80000 0x100>; 362279377Simp interrupts = <0 58 0>; 363279377Simp #address-cells = <1>; 364279377Simp #size-cells = <0>; 365279377Simp clocks = <&clock CLK_I2C2>; 366279377Simp clock-names = "i2c"; 367279377Simp pinctrl-names = "default"; 368279377Simp pinctrl-0 = <&i2c2_bus>; 369279377Simp samsung,sysreg-phandle = <&sysreg_system_controller>; 370279377Simp status = "disabled"; 371279377Simp }; 372279377Simp 373279377Simp i2c_3: i2c@12C90000 { 374279377Simp compatible = "samsung,s3c2440-i2c"; 375279377Simp reg = <0x12C90000 0x100>; 376279377Simp interrupts = <0 59 0>; 377279377Simp #address-cells = <1>; 378279377Simp #size-cells = <0>; 379279377Simp clocks = <&clock CLK_I2C3>; 380279377Simp clock-names = "i2c"; 381279377Simp pinctrl-names = "default"; 382279377Simp pinctrl-0 = <&i2c3_bus>; 383279377Simp samsung,sysreg-phandle = <&sysreg_system_controller>; 384279377Simp status = "disabled"; 385279377Simp }; 386279377Simp 387279377Simp i2c_4: i2c@12CA0000 { 388279377Simp compatible = "samsung,s3c2440-i2c"; 389279377Simp reg = <0x12CA0000 0x100>; 390279377Simp interrupts = <0 60 0>; 391279377Simp #address-cells = <1>; 392279377Simp #size-cells = <0>; 393279377Simp clocks = <&clock CLK_I2C4>; 394279377Simp clock-names = "i2c"; 395279377Simp pinctrl-names = "default"; 396279377Simp pinctrl-0 = <&i2c4_bus>; 397279377Simp status = "disabled"; 398279377Simp }; 399279377Simp 400279377Simp i2c_5: i2c@12CB0000 { 401279377Simp compatible = "samsung,s3c2440-i2c"; 402279377Simp reg = <0x12CB0000 0x100>; 403279377Simp interrupts = <0 61 0>; 404279377Simp #address-cells = <1>; 405279377Simp #size-cells = <0>; 406279377Simp clocks = <&clock CLK_I2C5>; 407279377Simp clock-names = "i2c"; 408279377Simp pinctrl-names = "default"; 409279377Simp pinctrl-0 = <&i2c5_bus>; 410279377Simp status = "disabled"; 411279377Simp }; 412279377Simp 413279377Simp i2c_6: i2c@12CC0000 { 414279377Simp compatible = "samsung,s3c2440-i2c"; 415279377Simp reg = <0x12CC0000 0x100>; 416279377Simp interrupts = <0 62 0>; 417279377Simp #address-cells = <1>; 418279377Simp #size-cells = <0>; 419279377Simp clocks = <&clock CLK_I2C6>; 420279377Simp clock-names = "i2c"; 421279377Simp pinctrl-names = "default"; 422279377Simp pinctrl-0 = <&i2c6_bus>; 423279377Simp status = "disabled"; 424279377Simp }; 425279377Simp 426279377Simp i2c_7: i2c@12CD0000 { 427279377Simp compatible = "samsung,s3c2440-i2c"; 428279377Simp reg = <0x12CD0000 0x100>; 429279377Simp interrupts = <0 63 0>; 430279377Simp #address-cells = <1>; 431279377Simp #size-cells = <0>; 432279377Simp clocks = <&clock CLK_I2C7>; 433279377Simp clock-names = "i2c"; 434279377Simp pinctrl-names = "default"; 435279377Simp pinctrl-0 = <&i2c7_bus>; 436279377Simp status = "disabled"; 437279377Simp }; 438279377Simp 439279377Simp i2c_8: i2c@12CE0000 { 440279377Simp compatible = "samsung,s3c2440-hdmiphy-i2c"; 441279377Simp reg = <0x12CE0000 0x1000>; 442279377Simp interrupts = <0 64 0>; 443279377Simp #address-cells = <1>; 444279377Simp #size-cells = <0>; 445279377Simp clocks = <&clock CLK_I2C_HDMI>; 446279377Simp clock-names = "i2c"; 447279377Simp status = "disabled"; 448279377Simp }; 449279377Simp 450279377Simp i2c_9: i2c@121D0000 { 451279377Simp compatible = "samsung,exynos5-sata-phy-i2c"; 452279377Simp reg = <0x121D0000 0x100>; 453279377Simp #address-cells = <1>; 454279377Simp #size-cells = <0>; 455279377Simp clocks = <&clock CLK_SATA_PHYI2C>; 456279377Simp clock-names = "i2c"; 457279377Simp status = "disabled"; 458279377Simp }; 459279377Simp 460279377Simp spi_0: spi@12d20000 { 461279377Simp compatible = "samsung,exynos4210-spi"; 462279377Simp status = "disabled"; 463279377Simp reg = <0x12d20000 0x100>; 464279377Simp interrupts = <0 66 0>; 465279377Simp dmas = <&pdma0 5 466279377Simp &pdma0 4>; 467279377Simp dma-names = "tx", "rx"; 468279377Simp #address-cells = <1>; 469279377Simp #size-cells = <0>; 470279377Simp clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 471279377Simp clock-names = "spi", "spi_busclk0"; 472279377Simp pinctrl-names = "default"; 473279377Simp pinctrl-0 = <&spi0_bus>; 474279377Simp }; 475279377Simp 476279377Simp spi_1: spi@12d30000 { 477279377Simp compatible = "samsung,exynos4210-spi"; 478279377Simp status = "disabled"; 479279377Simp reg = <0x12d30000 0x100>; 480279377Simp interrupts = <0 67 0>; 481279377Simp dmas = <&pdma1 5 482279377Simp &pdma1 4>; 483279377Simp dma-names = "tx", "rx"; 484279377Simp #address-cells = <1>; 485279377Simp #size-cells = <0>; 486279377Simp clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 487279377Simp clock-names = "spi", "spi_busclk0"; 488279377Simp pinctrl-names = "default"; 489279377Simp pinctrl-0 = <&spi1_bus>; 490279377Simp }; 491279377Simp 492279377Simp spi_2: spi@12d40000 { 493279377Simp compatible = "samsung,exynos4210-spi"; 494279377Simp status = "disabled"; 495279377Simp reg = <0x12d40000 0x100>; 496279377Simp interrupts = <0 68 0>; 497279377Simp dmas = <&pdma0 7 498279377Simp &pdma0 6>; 499279377Simp dma-names = "tx", "rx"; 500279377Simp #address-cells = <1>; 501279377Simp #size-cells = <0>; 502279377Simp clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 503279377Simp clock-names = "spi", "spi_busclk0"; 504279377Simp pinctrl-names = "default"; 505279377Simp pinctrl-0 = <&spi2_bus>; 506279377Simp }; 507279377Simp 508279377Simp mmc_0: mmc@12200000 { 509279377Simp compatible = "samsung,exynos5250-dw-mshc"; 510279377Simp interrupts = <0 75 0>; 511279377Simp #address-cells = <1>; 512279377Simp #size-cells = <0>; 513279377Simp reg = <0x12200000 0x1000>; 514279377Simp clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; 515279377Simp clock-names = "biu", "ciu"; 516279377Simp fifo-depth = <0x80>; 517279377Simp status = "disabled"; 518279377Simp }; 519279377Simp 520279377Simp mmc_1: mmc@12210000 { 521279377Simp compatible = "samsung,exynos5250-dw-mshc"; 522279377Simp interrupts = <0 76 0>; 523279377Simp #address-cells = <1>; 524279377Simp #size-cells = <0>; 525279377Simp reg = <0x12210000 0x1000>; 526279377Simp clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; 527279377Simp clock-names = "biu", "ciu"; 528279377Simp fifo-depth = <0x80>; 529279377Simp status = "disabled"; 530279377Simp }; 531279377Simp 532279377Simp mmc_2: mmc@12220000 { 533279377Simp compatible = "samsung,exynos5250-dw-mshc"; 534279377Simp interrupts = <0 77 0>; 535279377Simp #address-cells = <1>; 536279377Simp #size-cells = <0>; 537279377Simp reg = <0x12220000 0x1000>; 538279377Simp clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; 539279377Simp clock-names = "biu", "ciu"; 540279377Simp fifo-depth = <0x80>; 541279377Simp status = "disabled"; 542279377Simp }; 543279377Simp 544279377Simp mmc_3: mmc@12230000 { 545279377Simp compatible = "samsung,exynos5250-dw-mshc"; 546279377Simp reg = <0x12230000 0x1000>; 547279377Simp interrupts = <0 78 0>; 548279377Simp #address-cells = <1>; 549279377Simp #size-cells = <0>; 550279377Simp clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; 551279377Simp clock-names = "biu", "ciu"; 552279377Simp fifo-depth = <0x80>; 553279377Simp status = "disabled"; 554279377Simp }; 555279377Simp 556279377Simp i2s0: i2s@03830000 { 557279377Simp compatible = "samsung,s5pv210-i2s"; 558279377Simp status = "disabled"; 559279377Simp reg = <0x03830000 0x100>; 560279377Simp dmas = <&pdma0 10 561279377Simp &pdma0 9 562279377Simp &pdma0 8>; 563279377Simp dma-names = "tx", "rx", "tx-sec"; 564279377Simp clocks = <&clock_audss EXYNOS_I2S_BUS>, 565279377Simp <&clock_audss EXYNOS_I2S_BUS>, 566279377Simp <&clock_audss EXYNOS_SCLK_I2S>; 567279377Simp clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; 568279377Simp samsung,idma-addr = <0x03000000>; 569279377Simp pinctrl-names = "default"; 570279377Simp pinctrl-0 = <&i2s0_bus>; 571279377Simp }; 572279377Simp 573279377Simp i2s1: i2s@12D60000 { 574279377Simp compatible = "samsung,s3c6410-i2s"; 575279377Simp status = "disabled"; 576279377Simp reg = <0x12D60000 0x100>; 577279377Simp dmas = <&pdma1 12 578279377Simp &pdma1 11>; 579279377Simp dma-names = "tx", "rx"; 580279377Simp clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>; 581279377Simp clock-names = "iis", "i2s_opclk0"; 582279377Simp pinctrl-names = "default"; 583279377Simp pinctrl-0 = <&i2s1_bus>; 584279377Simp }; 585279377Simp 586279377Simp i2s2: i2s@12D70000 { 587279377Simp compatible = "samsung,s3c6410-i2s"; 588279377Simp status = "disabled"; 589279377Simp reg = <0x12D70000 0x100>; 590279377Simp dmas = <&pdma0 12 591279377Simp &pdma0 11>; 592279377Simp dma-names = "tx", "rx"; 593279377Simp clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>; 594279377Simp clock-names = "iis", "i2s_opclk0"; 595279377Simp pinctrl-names = "default"; 596279377Simp pinctrl-0 = <&i2s2_bus>; 597279377Simp }; 598279377Simp 599279377Simp usb@12000000 { 600279377Simp compatible = "samsung,exynos5250-dwusb3"; 601279377Simp clocks = <&clock CLK_USB3>; 602279377Simp clock-names = "usbdrd30"; 603279377Simp #address-cells = <1>; 604279377Simp #size-cells = <1>; 605279377Simp ranges; 606279377Simp 607279377Simp usbdrd_dwc3: dwc3 { 608279377Simp compatible = "synopsys,dwc3"; 609279377Simp reg = <0x12000000 0x10000>; 610279377Simp interrupts = <0 72 0>; 611279377Simp phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; 612279377Simp phy-names = "usb2-phy", "usb3-phy"; 613279377Simp }; 614279377Simp }; 615279377Simp 616279377Simp usbdrd_phy: phy@12100000 { 617279377Simp compatible = "samsung,exynos5250-usbdrd-phy"; 618279377Simp reg = <0x12100000 0x100>; 619279377Simp clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>; 620279377Simp clock-names = "phy", "ref"; 621279377Simp samsung,pmu-syscon = <&pmu_system_controller>; 622279377Simp #phy-cells = <1>; 623279377Simp }; 624279377Simp 625279377Simp ehci: usb@12110000 { 626279377Simp compatible = "samsung,exynos4210-ehci"; 627279377Simp reg = <0x12110000 0x100>; 628279377Simp interrupts = <0 71 0>; 629279377Simp 630279377Simp clocks = <&clock CLK_USB2>; 631279377Simp clock-names = "usbhost"; 632279377Simp #address-cells = <1>; 633279377Simp #size-cells = <0>; 634279377Simp port@0 { 635279377Simp reg = <0>; 636279377Simp phys = <&usb2_phy_gen 1>; 637279377Simp }; 638279377Simp }; 639279377Simp 640279377Simp ohci: usb@12120000 { 641279377Simp compatible = "samsung,exynos4210-ohci"; 642279377Simp reg = <0x12120000 0x100>; 643279377Simp interrupts = <0 71 0>; 644279377Simp 645279377Simp clocks = <&clock CLK_USB2>; 646279377Simp clock-names = "usbhost"; 647279377Simp #address-cells = <1>; 648279377Simp #size-cells = <0>; 649279377Simp port@0 { 650279377Simp reg = <0>; 651279377Simp phys = <&usb2_phy_gen 1>; 652279377Simp }; 653279377Simp }; 654279377Simp 655279377Simp usb2_phy_gen: phy@12130000 { 656279377Simp compatible = "samsung,exynos5250-usb2-phy"; 657279377Simp reg = <0x12130000 0x100>; 658279377Simp clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>; 659279377Simp clock-names = "phy", "ref"; 660279377Simp #phy-cells = <1>; 661279377Simp samsung,sysreg-phandle = <&sysreg_system_controller>; 662279377Simp samsung,pmureg-phandle = <&pmu_system_controller>; 663279377Simp }; 664279377Simp 665279377Simp pwm: pwm@12dd0000 { 666279377Simp compatible = "samsung,exynos4210-pwm"; 667279377Simp reg = <0x12dd0000 0x100>; 668279377Simp samsung,pwm-outputs = <0>, <1>, <2>, <3>; 669279377Simp #pwm-cells = <3>; 670279377Simp clocks = <&clock CLK_PWM>; 671279377Simp clock-names = "timers"; 672279377Simp }; 673279377Simp 674279377Simp amba { 675279377Simp #address-cells = <1>; 676279377Simp #size-cells = <1>; 677279377Simp compatible = "arm,amba-bus"; 678279377Simp interrupt-parent = <&gic>; 679279377Simp ranges; 680279377Simp 681279377Simp pdma0: pdma@121A0000 { 682279377Simp compatible = "arm,pl330", "arm,primecell"; 683279377Simp reg = <0x121A0000 0x1000>; 684279377Simp interrupts = <0 34 0>; 685279377Simp clocks = <&clock CLK_PDMA0>; 686279377Simp clock-names = "apb_pclk"; 687279377Simp #dma-cells = <1>; 688279377Simp #dma-channels = <8>; 689279377Simp #dma-requests = <32>; 690279377Simp }; 691279377Simp 692279377Simp pdma1: pdma@121B0000 { 693279377Simp compatible = "arm,pl330", "arm,primecell"; 694279377Simp reg = <0x121B0000 0x1000>; 695279377Simp interrupts = <0 35 0>; 696279377Simp clocks = <&clock CLK_PDMA1>; 697279377Simp clock-names = "apb_pclk"; 698279377Simp #dma-cells = <1>; 699279377Simp #dma-channels = <8>; 700279377Simp #dma-requests = <32>; 701279377Simp }; 702279377Simp 703279377Simp mdma0: mdma@10800000 { 704279377Simp compatible = "arm,pl330", "arm,primecell"; 705279377Simp reg = <0x10800000 0x1000>; 706279377Simp interrupts = <0 33 0>; 707279377Simp clocks = <&clock CLK_MDMA0>; 708279377Simp clock-names = "apb_pclk"; 709279377Simp #dma-cells = <1>; 710279377Simp #dma-channels = <8>; 711279377Simp #dma-requests = <1>; 712279377Simp }; 713279377Simp 714279377Simp mdma1: mdma@11C10000 { 715279377Simp compatible = "arm,pl330", "arm,primecell"; 716279377Simp reg = <0x11C10000 0x1000>; 717279377Simp interrupts = <0 124 0>; 718279377Simp clocks = <&clock CLK_MDMA1>; 719279377Simp clock-names = "apb_pclk"; 720279377Simp #dma-cells = <1>; 721279377Simp #dma-channels = <8>; 722279377Simp #dma-requests = <1>; 723279377Simp }; 724279377Simp }; 725279377Simp 726279377Simp gsc_0: gsc@13e00000 { 727279377Simp compatible = "samsung,exynos5-gsc"; 728279377Simp reg = <0x13e00000 0x1000>; 729279377Simp interrupts = <0 85 0>; 730279377Simp power-domains = <&pd_gsc>; 731279377Simp clocks = <&clock CLK_GSCL0>; 732279377Simp clock-names = "gscl"; 733295436Sandrew iommu = <&sysmmu_gsc0>; 734279377Simp }; 735279377Simp 736279377Simp gsc_1: gsc@13e10000 { 737279377Simp compatible = "samsung,exynos5-gsc"; 738279377Simp reg = <0x13e10000 0x1000>; 739279377Simp interrupts = <0 86 0>; 740279377Simp power-domains = <&pd_gsc>; 741279377Simp clocks = <&clock CLK_GSCL1>; 742279377Simp clock-names = "gscl"; 743295436Sandrew iommu = <&sysmmu_gsc1>; 744279377Simp }; 745279377Simp 746279377Simp gsc_2: gsc@13e20000 { 747279377Simp compatible = "samsung,exynos5-gsc"; 748279377Simp reg = <0x13e20000 0x1000>; 749279377Simp interrupts = <0 87 0>; 750279377Simp power-domains = <&pd_gsc>; 751279377Simp clocks = <&clock CLK_GSCL2>; 752279377Simp clock-names = "gscl"; 753295436Sandrew iommu = <&sysmmu_gsc2>; 754279377Simp }; 755279377Simp 756279377Simp gsc_3: gsc@13e30000 { 757279377Simp compatible = "samsung,exynos5-gsc"; 758279377Simp reg = <0x13e30000 0x1000>; 759279377Simp interrupts = <0 88 0>; 760279377Simp power-domains = <&pd_gsc>; 761279377Simp clocks = <&clock CLK_GSCL3>; 762279377Simp clock-names = "gscl"; 763295436Sandrew iommu = <&sysmmu_gsc3>; 764279377Simp }; 765279377Simp 766279377Simp hdmi: hdmi { 767279377Simp compatible = "samsung,exynos4212-hdmi"; 768279377Simp reg = <0x14530000 0x70000>; 769295436Sandrew power-domains = <&pd_disp1>; 770279377Simp interrupts = <0 95 0>; 771279377Simp clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 772279377Simp <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 773279377Simp <&clock CLK_MOUT_HDMI>; 774279377Simp clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 775279377Simp "sclk_hdmiphy", "mout_hdmi"; 776279377Simp samsung,syscon-phandle = <&pmu_system_controller>; 777279377Simp }; 778279377Simp 779279377Simp mixer { 780279377Simp compatible = "samsung,exynos5250-mixer"; 781279377Simp reg = <0x14450000 0x10000>; 782295436Sandrew power-domains = <&pd_disp1>; 783279377Simp interrupts = <0 94 0>; 784295436Sandrew clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 785295436Sandrew <&clock CLK_SCLK_HDMI>; 786295436Sandrew clock-names = "mixer", "hdmi", "sclk_hdmi"; 787295436Sandrew iommus = <&sysmmu_tv>; 788279377Simp }; 789279377Simp 790279377Simp dp_phy: video-phy@10040720 { 791279377Simp compatible = "samsung,exynos5250-dp-video-phy"; 792279377Simp samsung,pmu-syscon = <&pmu_system_controller>; 793279377Simp #phy-cells = <0>; 794279377Simp }; 795279377Simp 796279377Simp adc: adc@12D10000 { 797279377Simp compatible = "samsung,exynos-adc-v1"; 798279377Simp reg = <0x12D10000 0x100>; 799279377Simp interrupts = <0 106 0>; 800279377Simp clocks = <&clock CLK_ADC>; 801279377Simp clock-names = "adc"; 802279377Simp #io-channel-cells = <1>; 803279377Simp io-channel-ranges; 804279377Simp samsung,syscon-phandle = <&pmu_system_controller>; 805279377Simp status = "disabled"; 806279377Simp }; 807279377Simp 808279377Simp sss@10830000 { 809279377Simp compatible = "samsung,exynos4210-secss"; 810279377Simp reg = <0x10830000 0x10000>; 811279377Simp interrupts = <0 112 0>; 812279377Simp clocks = <&clock CLK_SSS>; 813279377Simp clock-names = "secss"; 814279377Simp }; 815295436Sandrew 816295436Sandrew sysmmu_g2d: sysmmu@10A60000 { 817295436Sandrew compatible = "samsung,exynos-sysmmu"; 818295436Sandrew reg = <0x10A60000 0x1000>; 819295436Sandrew interrupt-parent = <&combiner>; 820295436Sandrew interrupts = <24 5>; 821295436Sandrew clock-names = "sysmmu", "master"; 822295436Sandrew clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>; 823295436Sandrew #iommu-cells = <0>; 824295436Sandrew }; 825295436Sandrew 826295436Sandrew sysmmu_mfc_r: sysmmu@11200000 { 827295436Sandrew compatible = "samsung,exynos-sysmmu"; 828295436Sandrew reg = <0x11200000 0x1000>; 829295436Sandrew interrupt-parent = <&combiner>; 830295436Sandrew interrupts = <6 2>; 831295436Sandrew power-domains = <&pd_mfc>; 832295436Sandrew clock-names = "sysmmu", "master"; 833295436Sandrew clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; 834295436Sandrew #iommu-cells = <0>; 835295436Sandrew }; 836295436Sandrew 837295436Sandrew sysmmu_mfc_l: sysmmu@11210000 { 838295436Sandrew compatible = "samsung,exynos-sysmmu"; 839295436Sandrew reg = <0x11210000 0x1000>; 840295436Sandrew interrupt-parent = <&combiner>; 841295436Sandrew interrupts = <8 5>; 842295436Sandrew power-domains = <&pd_mfc>; 843295436Sandrew clock-names = "sysmmu", "master"; 844295436Sandrew clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; 845295436Sandrew #iommu-cells = <0>; 846295436Sandrew }; 847295436Sandrew 848295436Sandrew sysmmu_rotator: sysmmu@11D40000 { 849295436Sandrew compatible = "samsung,exynos-sysmmu"; 850295436Sandrew reg = <0x11D40000 0x1000>; 851295436Sandrew interrupt-parent = <&combiner>; 852295436Sandrew interrupts = <4 0>; 853295436Sandrew clock-names = "sysmmu", "master"; 854295436Sandrew clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; 855295436Sandrew #iommu-cells = <0>; 856295436Sandrew }; 857295436Sandrew 858295436Sandrew sysmmu_jpeg: sysmmu@11F20000 { 859295436Sandrew compatible = "samsung,exynos-sysmmu"; 860295436Sandrew reg = <0x11F20000 0x1000>; 861295436Sandrew interrupt-parent = <&combiner>; 862295436Sandrew interrupts = <4 2>; 863295436Sandrew power-domains = <&pd_gsc>; 864295436Sandrew clock-names = "sysmmu", "master"; 865295436Sandrew clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; 866295436Sandrew #iommu-cells = <0>; 867295436Sandrew }; 868295436Sandrew 869295436Sandrew sysmmu_fimc_isp: sysmmu@13260000 { 870295436Sandrew compatible = "samsung,exynos-sysmmu"; 871295436Sandrew reg = <0x13260000 0x1000>; 872295436Sandrew interrupt-parent = <&combiner>; 873295436Sandrew interrupts = <10 6>; 874295436Sandrew clock-names = "sysmmu"; 875295436Sandrew clocks = <&clock CLK_SMMU_FIMC_ISP>; 876295436Sandrew #iommu-cells = <0>; 877295436Sandrew }; 878295436Sandrew 879295436Sandrew sysmmu_fimc_drc: sysmmu@13270000 { 880295436Sandrew compatible = "samsung,exynos-sysmmu"; 881295436Sandrew reg = <0x13270000 0x1000>; 882295436Sandrew interrupt-parent = <&combiner>; 883295436Sandrew interrupts = <11 6>; 884295436Sandrew clock-names = "sysmmu"; 885295436Sandrew clocks = <&clock CLK_SMMU_FIMC_DRC>; 886295436Sandrew #iommu-cells = <0>; 887295436Sandrew }; 888295436Sandrew 889295436Sandrew sysmmu_fimc_fd: sysmmu@132A0000 { 890295436Sandrew compatible = "samsung,exynos-sysmmu"; 891295436Sandrew reg = <0x132A0000 0x1000>; 892295436Sandrew interrupt-parent = <&combiner>; 893295436Sandrew interrupts = <5 0>; 894295436Sandrew clock-names = "sysmmu"; 895295436Sandrew clocks = <&clock CLK_SMMU_FIMC_FD>; 896295436Sandrew #iommu-cells = <0>; 897295436Sandrew }; 898295436Sandrew 899295436Sandrew sysmmu_fimc_scc: sysmmu@13280000 { 900295436Sandrew compatible = "samsung,exynos-sysmmu"; 901295436Sandrew reg = <0x13280000 0x1000>; 902295436Sandrew interrupt-parent = <&combiner>; 903295436Sandrew interrupts = <5 2>; 904295436Sandrew clock-names = "sysmmu"; 905295436Sandrew clocks = <&clock CLK_SMMU_FIMC_SCC>; 906295436Sandrew #iommu-cells = <0>; 907295436Sandrew }; 908295436Sandrew 909295436Sandrew sysmmu_fimc_scp: sysmmu@13290000 { 910295436Sandrew compatible = "samsung,exynos-sysmmu"; 911295436Sandrew reg = <0x13290000 0x1000>; 912295436Sandrew interrupt-parent = <&combiner>; 913295436Sandrew interrupts = <3 6>; 914295436Sandrew clock-names = "sysmmu"; 915295436Sandrew clocks = <&clock CLK_SMMU_FIMC_SCP>; 916295436Sandrew #iommu-cells = <0>; 917295436Sandrew }; 918295436Sandrew 919295436Sandrew sysmmu_fimc_mcuctl: sysmmu@132B0000 { 920295436Sandrew compatible = "samsung,exynos-sysmmu"; 921295436Sandrew reg = <0x132B0000 0x1000>; 922295436Sandrew interrupt-parent = <&combiner>; 923295436Sandrew interrupts = <5 4>; 924295436Sandrew clock-names = "sysmmu"; 925295436Sandrew clocks = <&clock CLK_SMMU_FIMC_MCU>; 926295436Sandrew #iommu-cells = <0>; 927295436Sandrew }; 928295436Sandrew 929295436Sandrew sysmmu_fimc_odc: sysmmu@132C0000 { 930295436Sandrew compatible = "samsung,exynos-sysmmu"; 931295436Sandrew reg = <0x132C0000 0x1000>; 932295436Sandrew interrupt-parent = <&combiner>; 933295436Sandrew interrupts = <11 0>; 934295436Sandrew clock-names = "sysmmu"; 935295436Sandrew clocks = <&clock CLK_SMMU_FIMC_ODC>; 936295436Sandrew #iommu-cells = <0>; 937295436Sandrew }; 938295436Sandrew 939295436Sandrew sysmmu_fimc_dis0: sysmmu@132D0000 { 940295436Sandrew compatible = "samsung,exynos-sysmmu"; 941295436Sandrew reg = <0x132D0000 0x1000>; 942295436Sandrew interrupt-parent = <&combiner>; 943295436Sandrew interrupts = <10 4>; 944295436Sandrew clock-names = "sysmmu"; 945295436Sandrew clocks = <&clock CLK_SMMU_FIMC_DIS0>; 946295436Sandrew #iommu-cells = <0>; 947295436Sandrew }; 948295436Sandrew 949295436Sandrew sysmmu_fimc_dis1: sysmmu@132E0000{ 950295436Sandrew compatible = "samsung,exynos-sysmmu"; 951295436Sandrew reg = <0x132E0000 0x1000>; 952295436Sandrew interrupt-parent = <&combiner>; 953295436Sandrew interrupts = <9 4>; 954295436Sandrew clock-names = "sysmmu"; 955295436Sandrew clocks = <&clock CLK_SMMU_FIMC_DIS1>; 956295436Sandrew #iommu-cells = <0>; 957295436Sandrew }; 958295436Sandrew 959295436Sandrew sysmmu_fimc_3dnr: sysmmu@132F0000 { 960295436Sandrew compatible = "samsung,exynos-sysmmu"; 961295436Sandrew reg = <0x132F0000 0x1000>; 962295436Sandrew interrupt-parent = <&combiner>; 963295436Sandrew interrupts = <5 6>; 964295436Sandrew clock-names = "sysmmu"; 965295436Sandrew clocks = <&clock CLK_SMMU_FIMC_3DNR>; 966295436Sandrew #iommu-cells = <0>; 967295436Sandrew }; 968295436Sandrew 969295436Sandrew sysmmu_fimc_lite0: sysmmu@13C40000 { 970295436Sandrew compatible = "samsung,exynos-sysmmu"; 971295436Sandrew reg = <0x13C40000 0x1000>; 972295436Sandrew interrupt-parent = <&combiner>; 973295436Sandrew interrupts = <3 4>; 974295436Sandrew power-domains = <&pd_gsc>; 975295436Sandrew clock-names = "sysmmu", "master"; 976295436Sandrew clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>; 977295436Sandrew #iommu-cells = <0>; 978295436Sandrew }; 979295436Sandrew 980295436Sandrew sysmmu_fimc_lite1: sysmmu@13C50000 { 981295436Sandrew compatible = "samsung,exynos-sysmmu"; 982295436Sandrew reg = <0x13C50000 0x1000>; 983295436Sandrew interrupt-parent = <&combiner>; 984295436Sandrew interrupts = <24 1>; 985295436Sandrew power-domains = <&pd_gsc>; 986295436Sandrew clock-names = "sysmmu", "master"; 987295436Sandrew clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>; 988295436Sandrew #iommu-cells = <0>; 989295436Sandrew }; 990295436Sandrew 991295436Sandrew sysmmu_gsc0: sysmmu@13E80000 { 992295436Sandrew compatible = "samsung,exynos-sysmmu"; 993295436Sandrew reg = <0x13E80000 0x1000>; 994295436Sandrew interrupt-parent = <&combiner>; 995295436Sandrew interrupts = <2 0>; 996295436Sandrew power-domains = <&pd_gsc>; 997295436Sandrew clock-names = "sysmmu", "master"; 998295436Sandrew clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; 999295436Sandrew #iommu-cells = <0>; 1000295436Sandrew }; 1001295436Sandrew 1002295436Sandrew sysmmu_gsc1: sysmmu@13E90000 { 1003295436Sandrew compatible = "samsung,exynos-sysmmu"; 1004295436Sandrew reg = <0x13E90000 0x1000>; 1005295436Sandrew interrupt-parent = <&combiner>; 1006295436Sandrew interrupts = <2 2>; 1007295436Sandrew power-domains = <&pd_gsc>; 1008295436Sandrew clock-names = "sysmmu", "master"; 1009295436Sandrew clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>; 1010295436Sandrew #iommu-cells = <0>; 1011295436Sandrew }; 1012295436Sandrew 1013295436Sandrew sysmmu_gsc2: sysmmu@13EA0000 { 1014295436Sandrew compatible = "samsung,exynos-sysmmu"; 1015295436Sandrew reg = <0x13EA0000 0x1000>; 1016295436Sandrew interrupt-parent = <&combiner>; 1017295436Sandrew interrupts = <2 4>; 1018295436Sandrew power-domains = <&pd_gsc>; 1019295436Sandrew clock-names = "sysmmu", "master"; 1020295436Sandrew clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>; 1021295436Sandrew #iommu-cells = <0>; 1022295436Sandrew }; 1023295436Sandrew 1024295436Sandrew sysmmu_gsc3: sysmmu@13EB0000 { 1025295436Sandrew compatible = "samsung,exynos-sysmmu"; 1026295436Sandrew reg = <0x13EB0000 0x1000>; 1027295436Sandrew interrupt-parent = <&combiner>; 1028295436Sandrew interrupts = <2 6>; 1029295436Sandrew power-domains = <&pd_gsc>; 1030295436Sandrew clock-names = "sysmmu", "master"; 1031295436Sandrew clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>; 1032295436Sandrew #iommu-cells = <0>; 1033295436Sandrew }; 1034295436Sandrew 1035295436Sandrew sysmmu_fimd1: sysmmu@14640000 { 1036295436Sandrew compatible = "samsung,exynos-sysmmu"; 1037295436Sandrew reg = <0x14640000 0x1000>; 1038295436Sandrew interrupt-parent = <&combiner>; 1039295436Sandrew interrupts = <3 2>; 1040295436Sandrew power-domains = <&pd_disp1>; 1041295436Sandrew clock-names = "sysmmu", "master"; 1042295436Sandrew clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; 1043295436Sandrew #iommu-cells = <0>; 1044295436Sandrew }; 1045295436Sandrew 1046295436Sandrew sysmmu_tv: sysmmu@14650000 { 1047295436Sandrew compatible = "samsung,exynos-sysmmu"; 1048295436Sandrew reg = <0x14650000 0x1000>; 1049295436Sandrew interrupt-parent = <&combiner>; 1050295436Sandrew interrupts = <7 4>; 1051295436Sandrew power-domains = <&pd_disp1>; 1052295436Sandrew clock-names = "sysmmu", "master"; 1053295436Sandrew clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; 1054295436Sandrew #iommu-cells = <0>; 1055295436Sandrew }; 1056279377Simp}; 1057295436Sandrew 1058295436Sandrew&dp { 1059295436Sandrew power-domains = <&pd_disp1>; 1060295436Sandrew clocks = <&clock CLK_DP>; 1061295436Sandrew clock-names = "dp"; 1062295436Sandrew phys = <&dp_phy>; 1063295436Sandrew phy-names = "dp"; 1064295436Sandrew}; 1065295436Sandrew 1066295436Sandrew&fimd { 1067295436Sandrew power-domains = <&pd_disp1>; 1068295436Sandrew clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 1069295436Sandrew clock-names = "sclk_fimd", "fimd"; 1070295436Sandrew iommus = <&sysmmu_fimd1>; 1071295436Sandrew}; 1072295436Sandrew 1073295436Sandrew&rtc { 1074295436Sandrew clocks = <&clock CLK_RTC>; 1075295436Sandrew clock-names = "rtc"; 1076295436Sandrew interrupt-parent = <&pmu_system_controller>; 1077295436Sandrew status = "disabled"; 1078295436Sandrew}; 1079295436Sandrew 1080295436Sandrew&serial_0 { 1081295436Sandrew clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 1082295436Sandrew clock-names = "uart", "clk_uart_baud0"; 1083295436Sandrew}; 1084295436Sandrew 1085295436Sandrew&serial_1 { 1086295436Sandrew clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 1087295436Sandrew clock-names = "uart", "clk_uart_baud0"; 1088295436Sandrew}; 1089295436Sandrew 1090295436Sandrew&serial_2 { 1091295436Sandrew clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 1092295436Sandrew clock-names = "uart", "clk_uart_baud0"; 1093295436Sandrew}; 1094295436Sandrew 1095295436Sandrew&serial_3 { 1096295436Sandrew clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 1097295436Sandrew clock-names = "uart", "clk_uart_baud0"; 1098295436Sandrew}; 1099295436Sandrew 1100295436Sandrew#include "exynos5250-pinctrl.dtsi" 1101