1279377Simp/* 2279377Simp * Samsung's Exynos4x12 SoCs device tree source 3279377Simp * 4279377Simp * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5279377Simp * http://www.samsung.com 6279377Simp * 7279377Simp * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12 8279377Simp * based board files can include this file and provide values for board specfic 9279377Simp * bindings. 10279377Simp * 11279377Simp * Note: This file does not include device nodes for all the controllers in 12279377Simp * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional 13279377Simp * nodes can be added to this file. 14279377Simp * 15279377Simp * This program is free software; you can redistribute it and/or modify 16279377Simp * it under the terms of the GNU General Public License version 2 as 17279377Simp * published by the Free Software Foundation. 18279377Simp*/ 19279377Simp 20279377Simp#include "exynos4.dtsi" 21279377Simp#include "exynos4x12-pinctrl.dtsi" 22295436Sandrew#include "exynos4-cpu-thermal.dtsi" 23279377Simp 24279377Simp/ { 25279377Simp aliases { 26279377Simp pinctrl0 = &pinctrl_0; 27279377Simp pinctrl1 = &pinctrl_1; 28279377Simp pinctrl2 = &pinctrl_2; 29279377Simp pinctrl3 = &pinctrl_3; 30279377Simp fimc-lite0 = &fimc_lite_0; 31279377Simp fimc-lite1 = &fimc_lite_1; 32279377Simp mshc0 = &mshc_0; 33279377Simp }; 34279377Simp 35279377Simp sysram@02020000 { 36279377Simp compatible = "mmio-sram"; 37279377Simp reg = <0x02020000 0x40000>; 38279377Simp #address-cells = <1>; 39279377Simp #size-cells = <1>; 40279377Simp ranges = <0 0x02020000 0x40000>; 41279377Simp 42279377Simp smp-sysram@0 { 43279377Simp compatible = "samsung,exynos4210-sysram"; 44279377Simp reg = <0x0 0x1000>; 45279377Simp }; 46279377Simp 47279377Simp smp-sysram@2f000 { 48279377Simp compatible = "samsung,exynos4210-sysram-ns"; 49279377Simp reg = <0x2f000 0x1000>; 50279377Simp }; 51279377Simp }; 52279377Simp 53279377Simp pd_isp: isp-power-domain@10023CA0 { 54279377Simp compatible = "samsung,exynos4210-pd"; 55279377Simp reg = <0x10023CA0 0x20>; 56279377Simp #power-domain-cells = <0>; 57279377Simp }; 58279377Simp 59279377Simp l2c: l2-cache-controller@10502000 { 60279377Simp compatible = "arm,pl310-cache"; 61279377Simp reg = <0x10502000 0x1000>; 62279377Simp cache-unified; 63279377Simp cache-level = <2>; 64279377Simp arm,tag-latency = <2 2 1>; 65279377Simp arm,data-latency = <3 2 1>; 66279377Simp arm,double-linefill = <1>; 67279377Simp arm,double-linefill-incr = <0>; 68279377Simp arm,double-linefill-wrap = <1>; 69279377Simp arm,prefetch-drop = <1>; 70279377Simp arm,prefetch-offset = <7>; 71279377Simp }; 72279377Simp 73279377Simp clock: clock-controller@10030000 { 74279377Simp compatible = "samsung,exynos4412-clock"; 75279377Simp reg = <0x10030000 0x20000>; 76279377Simp #clock-cells = <1>; 77279377Simp }; 78279377Simp 79279377Simp mct@10050000 { 80279377Simp compatible = "samsung,exynos4412-mct"; 81279377Simp reg = <0x10050000 0x800>; 82279377Simp interrupt-parent = <&mct_map>; 83279377Simp interrupts = <0>, <1>, <2>, <3>, <4>; 84279377Simp clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 85279377Simp clock-names = "fin_pll", "mct"; 86279377Simp 87279377Simp mct_map: mct-map { 88279377Simp #interrupt-cells = <1>; 89279377Simp #address-cells = <0>; 90279377Simp #size-cells = <0>; 91279377Simp interrupt-map = <0 &gic 0 57 0>, 92279377Simp <1 &combiner 12 5>, 93279377Simp <2 &combiner 12 6>, 94279377Simp <3 &combiner 12 7>, 95279377Simp <4 &gic 1 12 0>; 96279377Simp }; 97279377Simp }; 98279377Simp 99279377Simp adc: adc@126C0000 { 100279377Simp compatible = "samsung,exynos-adc-v1"; 101279377Simp reg = <0x126C0000 0x100>; 102279377Simp interrupt-parent = <&combiner>; 103279377Simp interrupts = <10 3>; 104279377Simp clocks = <&clock CLK_TSADC>; 105279377Simp clock-names = "adc"; 106279377Simp #io-channel-cells = <1>; 107279377Simp io-channel-ranges; 108279377Simp samsung,syscon-phandle = <&pmu_system_controller>; 109279377Simp status = "disabled"; 110279377Simp }; 111279377Simp 112295436Sandrew g2d: g2d@10800000 { 113279377Simp compatible = "samsung,exynos4212-g2d"; 114279377Simp reg = <0x10800000 0x1000>; 115279377Simp interrupts = <0 89 0>; 116279377Simp clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; 117279377Simp clock-names = "sclk_fimg2d", "fimg2d"; 118295436Sandrew iommus = <&sysmmu_g2d>; 119279377Simp }; 120279377Simp 121279377Simp camera { 122279377Simp clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, 123279377Simp <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; 124279377Simp clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 125279377Simp 126295436Sandrew /* fimc_[0-3] are configured outside, under phandles */ 127279377Simp fimc_lite_0: fimc-lite@12390000 { 128279377Simp compatible = "samsung,exynos4212-fimc-lite"; 129279377Simp reg = <0x12390000 0x1000>; 130279377Simp interrupts = <0 105 0>; 131279377Simp power-domains = <&pd_isp>; 132279377Simp clocks = <&clock CLK_FIMC_LITE0>; 133279377Simp clock-names = "flite"; 134295436Sandrew iommus = <&sysmmu_fimc_lite0>; 135279377Simp status = "disabled"; 136279377Simp }; 137279377Simp 138279377Simp fimc_lite_1: fimc-lite@123A0000 { 139279377Simp compatible = "samsung,exynos4212-fimc-lite"; 140279377Simp reg = <0x123A0000 0x1000>; 141279377Simp interrupts = <0 106 0>; 142279377Simp power-domains = <&pd_isp>; 143279377Simp clocks = <&clock CLK_FIMC_LITE1>; 144279377Simp clock-names = "flite"; 145295436Sandrew iommus = <&sysmmu_fimc_lite1>; 146279377Simp status = "disabled"; 147279377Simp }; 148279377Simp 149279377Simp fimc_is: fimc-is@12000000 { 150279377Simp compatible = "samsung,exynos4212-fimc-is", "simple-bus"; 151279377Simp reg = <0x12000000 0x260000>; 152279377Simp interrupts = <0 90 0>, <0 95 0>; 153279377Simp power-domains = <&pd_isp>; 154279377Simp clocks = <&clock CLK_FIMC_LITE0>, 155279377Simp <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, 156279377Simp <&clock CLK_PPMUISPMX>, 157279377Simp <&clock CLK_MOUT_MPLL_USER_T>, 158279377Simp <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, 159279377Simp <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, 160279377Simp <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>, 161279377Simp <&clock CLK_DIV_MCUISP0>, 162279377Simp <&clock CLK_DIV_MCUISP1>, 163279377Simp <&clock CLK_UART_ISP_SCLK>, 164279377Simp <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>, 165279377Simp <&clock CLK_ACLK400_MCUISP>, 166279377Simp <&clock CLK_DIV_ACLK400_MCUISP>; 167279377Simp clock-names = "lite0", "lite1", "ppmuispx", 168279377Simp "ppmuispmx", "mpll", "isp", 169279377Simp "drc", "fd", "mcuisp", 170279377Simp "ispdiv0", "ispdiv1", "mcuispdiv0", 171279377Simp "mcuispdiv1", "uart", "aclk200", 172279377Simp "div_aclk200", "aclk400mcuisp", 173279377Simp "div_aclk400mcuisp"; 174295436Sandrew iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, 175295436Sandrew <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; 176295436Sandrew iommu-names = "isp", "drc", "fd", "mcuctl"; 177279377Simp #address-cells = <1>; 178279377Simp #size-cells = <1>; 179279377Simp ranges; 180279377Simp status = "disabled"; 181279377Simp 182279377Simp pmu { 183279377Simp reg = <0x10020000 0x3000>; 184279377Simp }; 185279377Simp 186279377Simp i2c1_isp: i2c-isp@12140000 { 187279377Simp compatible = "samsung,exynos4212-i2c-isp"; 188279377Simp reg = <0x12140000 0x100>; 189279377Simp clocks = <&clock CLK_I2C1_ISP>; 190279377Simp clock-names = "i2c_isp"; 191279377Simp #address-cells = <1>; 192279377Simp #size-cells = <0>; 193279377Simp }; 194279377Simp }; 195279377Simp }; 196279377Simp 197279377Simp mshc_0: mmc@12550000 { 198279377Simp compatible = "samsung,exynos4412-dw-mshc"; 199279377Simp reg = <0x12550000 0x1000>; 200279377Simp interrupts = <0 77 0>; 201279377Simp #address-cells = <1>; 202279377Simp #size-cells = <0>; 203279377Simp fifo-depth = <0x80>; 204279377Simp clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; 205279377Simp clock-names = "biu", "ciu"; 206279377Simp status = "disabled"; 207279377Simp }; 208279377Simp 209295436Sandrew sysmmu_g2d: sysmmu@10A40000{ 210295436Sandrew compatible = "samsung,exynos-sysmmu"; 211295436Sandrew reg = <0x10A40000 0x1000>; 212295436Sandrew interrupt-parent = <&combiner>; 213295436Sandrew interrupts = <4 7>; 214295436Sandrew clock-names = "sysmmu", "master"; 215295436Sandrew clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 216295436Sandrew #iommu-cells = <0>; 217279377Simp }; 218279377Simp 219295436Sandrew sysmmu_fimc_isp: sysmmu@12260000 { 220295436Sandrew compatible = "samsung,exynos-sysmmu"; 221295436Sandrew reg = <0x12260000 0x1000>; 222279377Simp interrupt-parent = <&combiner>; 223295436Sandrew interrupts = <16 2>; 224295436Sandrew power-domains = <&pd_isp>; 225295436Sandrew clock-names = "sysmmu"; 226295436Sandrew clocks = <&clock CLK_SMMU_ISP>; 227295436Sandrew #iommu-cells = <0>; 228279377Simp }; 229295436Sandrew 230295436Sandrew sysmmu_fimc_drc: sysmmu@12270000 { 231295436Sandrew compatible = "samsung,exynos-sysmmu"; 232295436Sandrew reg = <0x12270000 0x1000>; 233295436Sandrew interrupt-parent = <&combiner>; 234295436Sandrew interrupts = <16 3>; 235295436Sandrew power-domains = <&pd_isp>; 236295436Sandrew clock-names = "sysmmu"; 237295436Sandrew clocks = <&clock CLK_SMMU_DRC>; 238295436Sandrew #iommu-cells = <0>; 239295436Sandrew }; 240295436Sandrew 241295436Sandrew sysmmu_fimc_fd: sysmmu@122A0000 { 242295436Sandrew compatible = "samsung,exynos-sysmmu"; 243295436Sandrew reg = <0x122A0000 0x1000>; 244295436Sandrew interrupt-parent = <&combiner>; 245295436Sandrew interrupts = <16 4>; 246295436Sandrew power-domains = <&pd_isp>; 247295436Sandrew clock-names = "sysmmu"; 248295436Sandrew clocks = <&clock CLK_SMMU_FD>; 249295436Sandrew #iommu-cells = <0>; 250295436Sandrew }; 251295436Sandrew 252295436Sandrew sysmmu_fimc_mcuctl: sysmmu@122B0000 { 253295436Sandrew compatible = "samsung,exynos-sysmmu"; 254295436Sandrew reg = <0x122B0000 0x1000>; 255295436Sandrew interrupt-parent = <&combiner>; 256295436Sandrew interrupts = <16 5>; 257295436Sandrew power-domains = <&pd_isp>; 258295436Sandrew clock-names = "sysmmu"; 259295436Sandrew clocks = <&clock CLK_SMMU_ISPCX>; 260295436Sandrew #iommu-cells = <0>; 261295436Sandrew }; 262295436Sandrew 263295436Sandrew sysmmu_fimc_lite0: sysmmu@123B0000 { 264295436Sandrew compatible = "samsung,exynos-sysmmu"; 265295436Sandrew reg = <0x123B0000 0x1000>; 266295436Sandrew interrupt-parent = <&combiner>; 267295436Sandrew interrupts = <16 0>; 268295436Sandrew power-domains = <&pd_isp>; 269295436Sandrew clock-names = "sysmmu", "master"; 270295436Sandrew clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>; 271295436Sandrew #iommu-cells = <0>; 272295436Sandrew }; 273295436Sandrew 274295436Sandrew sysmmu_fimc_lite1: sysmmu@123C0000 { 275295436Sandrew compatible = "samsung,exynos-sysmmu"; 276295436Sandrew reg = <0x123C0000 0x1000>; 277295436Sandrew interrupt-parent = <&combiner>; 278295436Sandrew interrupts = <16 1>; 279295436Sandrew power-domains = <&pd_isp>; 280295436Sandrew clock-names = "sysmmu", "master"; 281295436Sandrew clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>; 282295436Sandrew #iommu-cells = <0>; 283295436Sandrew }; 284279377Simp}; 285295436Sandrew 286295436Sandrew&combiner { 287295436Sandrew interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, 288295436Sandrew <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, 289295436Sandrew <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, 290295436Sandrew <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, 291295436Sandrew <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; 292295436Sandrew}; 293295436Sandrew 294295436Sandrew&exynos_usbphy { 295295436Sandrew compatible = "samsung,exynos4x12-usb2-phy"; 296295436Sandrew samsung,sysreg-phandle = <&sys_reg>; 297295436Sandrew}; 298295436Sandrew 299295436Sandrew&fimc_0 { 300295436Sandrew compatible = "samsung,exynos4212-fimc"; 301295436Sandrew samsung,pix-limits = <4224 8192 1920 4224>; 302295436Sandrew samsung,mainscaler-ext; 303295436Sandrew samsung,isp-wb; 304295436Sandrew samsung,cam-if; 305295436Sandrew}; 306295436Sandrew 307295436Sandrew&fimc_1 { 308295436Sandrew compatible = "samsung,exynos4212-fimc"; 309295436Sandrew samsung,pix-limits = <4224 8192 1920 4224>; 310295436Sandrew samsung,mainscaler-ext; 311295436Sandrew samsung,isp-wb; 312295436Sandrew samsung,cam-if; 313295436Sandrew}; 314295436Sandrew 315295436Sandrew&fimc_2 { 316295436Sandrew compatible = "samsung,exynos4212-fimc"; 317295436Sandrew samsung,pix-limits = <4224 8192 1920 4224>; 318295436Sandrew samsung,mainscaler-ext; 319295436Sandrew samsung,isp-wb; 320295436Sandrew samsung,lcd-wb; 321295436Sandrew samsung,cam-if; 322295436Sandrew}; 323295436Sandrew 324295436Sandrew&fimc_3 { 325295436Sandrew compatible = "samsung,exynos4212-fimc"; 326295436Sandrew samsung,pix-limits = <1920 8192 1366 1920>; 327295436Sandrew samsung,rotators = <0>; 328295436Sandrew samsung,mainscaler-ext; 329295436Sandrew samsung,isp-wb; 330295436Sandrew samsung,lcd-wb; 331295436Sandrew}; 332295436Sandrew 333295436Sandrew&hdmi { 334295436Sandrew compatible = "samsung,exynos4212-hdmi"; 335295436Sandrew}; 336295436Sandrew 337295436Sandrew&jpeg_codec { 338295436Sandrew compatible = "samsung,exynos4212-jpeg"; 339295436Sandrew}; 340295436Sandrew 341295436Sandrew&rotator { 342295436Sandrew compatible = "samsung,exynos4212-rotator"; 343295436Sandrew}; 344295436Sandrew 345295436Sandrew&mixer { 346295436Sandrew compatible = "samsung,exynos4212-mixer"; 347295436Sandrew clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; 348295436Sandrew clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 349295436Sandrew <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; 350295436Sandrew}; 351295436Sandrew 352295436Sandrew&pinctrl_0 { 353295436Sandrew compatible = "samsung,exynos4x12-pinctrl"; 354295436Sandrew reg = <0x11400000 0x1000>; 355295436Sandrew interrupts = <0 47 0>; 356295436Sandrew}; 357295436Sandrew 358295436Sandrew&pinctrl_1 { 359295436Sandrew compatible = "samsung,exynos4x12-pinctrl"; 360295436Sandrew reg = <0x11000000 0x1000>; 361295436Sandrew interrupts = <0 46 0>; 362295436Sandrew 363295436Sandrew wakup_eint: wakeup-interrupt-controller { 364295436Sandrew compatible = "samsung,exynos4210-wakeup-eint"; 365295436Sandrew interrupt-parent = <&gic>; 366295436Sandrew interrupts = <0 32 0>; 367295436Sandrew }; 368295436Sandrew}; 369295436Sandrew 370295436Sandrew&pinctrl_2 { 371295436Sandrew compatible = "samsung,exynos4x12-pinctrl"; 372295436Sandrew reg = <0x03860000 0x1000>; 373295436Sandrew interrupt-parent = <&combiner>; 374295436Sandrew interrupts = <10 0>; 375295436Sandrew}; 376295436Sandrew 377295436Sandrew&pinctrl_3 { 378295436Sandrew compatible = "samsung,exynos4x12-pinctrl"; 379295436Sandrew reg = <0x106E0000 0x1000>; 380295436Sandrew interrupts = <0 72 0>; 381295436Sandrew}; 382295436Sandrew 383295436Sandrew&pmu_system_controller { 384295436Sandrew compatible = "samsung,exynos4212-pmu", "syscon"; 385295436Sandrew clock-names = "clkout0", "clkout1", "clkout2", "clkout3", 386295436Sandrew "clkout4", "clkout8", "clkout9"; 387295436Sandrew clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, 388295436Sandrew <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, 389295436Sandrew <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; 390295436Sandrew #clock-cells = <1>; 391295436Sandrew}; 392295436Sandrew 393295436Sandrew&tmu { 394295436Sandrew compatible = "samsung,exynos4412-tmu"; 395295436Sandrew interrupt-parent = <&combiner>; 396295436Sandrew interrupts = <2 4>; 397295436Sandrew reg = <0x100C0000 0x100>; 398295436Sandrew clocks = <&clock 383>; 399295436Sandrew clock-names = "tmu_apbif"; 400295436Sandrew status = "disabled"; 401295436Sandrew}; 402