exynos4415.dtsi revision 279377
1/* 2 * Samsung's Exynos4415 SoC device tree source 3 * 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 5 * 6 * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 7 * based board files can include this file and provide values for board 8 * specific bindings. 9 * 10 * Note: This file does not include device nodes for all the controllers in 11 * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional 12 * nodes can be added to this file. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 */ 18 19#include "skeleton.dtsi" 20#include <dt-bindings/clock/exynos4415.h> 21#include <dt-bindings/clock/exynos-audss-clk.h> 22 23/ { 24 compatible = "samsung,exynos4415"; 25 interrupt-parent = <&gic>; 26 27 aliases { 28 pinctrl0 = &pinctrl_0; 29 pinctrl1 = &pinctrl_1; 30 pinctrl2 = &pinctrl_2; 31 mshc0 = &mshc_0; 32 mshc1 = &mshc_1; 33 mshc2 = &mshc_2; 34 spi0 = &spi_0; 35 spi1 = &spi_1; 36 spi2 = &spi_2; 37 i2c0 = &i2c_0; 38 i2c1 = &i2c_1; 39 i2c2 = &i2c_2; 40 i2c3 = &i2c_3; 41 i2c4 = &i2c_4; 42 i2c5 = &i2c_5; 43 i2c6 = &i2c_6; 44 i2c7 = &i2c_7; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 cpu0: cpu@a00 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a9"; 54 reg = <0xa00>; 55 clock-frequency = <1600000000>; 56 }; 57 58 cpu1: cpu@a01 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a9"; 61 reg = <0xa01>; 62 clock-frequency = <1600000000>; 63 }; 64 65 cpu2: cpu@a02 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a9"; 68 reg = <0xa02>; 69 clock-frequency = <1600000000>; 70 }; 71 72 cpu3: cpu@a03 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a9"; 75 reg = <0xa03>; 76 clock-frequency = <1600000000>; 77 }; 78 }; 79 80 soc: soc { 81 compatible = "simple-bus"; 82 #address-cells = <1>; 83 #size-cells = <1>; 84 ranges; 85 86 sysram@02020000 { 87 compatible = "mmio-sram"; 88 reg = <0x02020000 0x50000>; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 ranges = <0 0x02020000 0x50000>; 92 93 smp-sysram@0 { 94 compatible = "samsung,exynos4210-sysram"; 95 reg = <0x0 0x1000>; 96 }; 97 98 smp-sysram@4f000 { 99 compatible = "samsung,exynos4210-sysram-ns"; 100 reg = <0x4f000 0x1000>; 101 }; 102 }; 103 104 pinctrl_2: pinctrl@03860000 { 105 compatible = "samsung,exynos4415-pinctrl"; 106 reg = <0x03860000 0x1000>; 107 interrupts = <0 242 0>; 108 }; 109 110 chipid@10000000 { 111 compatible = "samsung,exynos4210-chipid"; 112 reg = <0x10000000 0x100>; 113 }; 114 115 sysreg_system_controller: syscon@10010000 { 116 compatible = "samsung,exynos4-sysreg", "syscon"; 117 reg = <0x10010000 0x400>; 118 }; 119 120 pmu_system_controller: system-controller@10020000 { 121 compatible = "samsung,exynos4415-pmu", "syscon"; 122 reg = <0x10020000 0x4000>; 123 }; 124 125 mipi_phy: video-phy@10020710 { 126 compatible = "samsung,s5pv210-mipi-video-phy"; 127 reg = <0x10020710 8>; 128 #phy-cells = <1>; 129 }; 130 131 pd_cam: cam-power-domain@10024000 { 132 compatible = "samsung,exynos4210-pd"; 133 reg = <0x10024000 0x20>; 134 #power-domain-cells = <0>; 135 }; 136 137 pd_tv: tv-power-domain@10024020 { 138 compatible = "samsung,exynos4210-pd"; 139 reg = <0x10024020 0x20>; 140 #power-domain-cells = <0>; 141 }; 142 143 pd_mfc: mfc-power-domain@10024040 { 144 compatible = "samsung,exynos4210-pd"; 145 reg = <0x10024040 0x20>; 146 #power-domain-cells = <0>; 147 }; 148 149 pd_g3d: g3d-power-domain@10024060 { 150 compatible = "samsung,exynos4210-pd"; 151 reg = <0x10024060 0x20>; 152 #power-domain-cells = <0>; 153 }; 154 155 pd_lcd0: lcd0-power-domain@10024080 { 156 compatible = "samsung,exynos4210-pd"; 157 reg = <0x10024080 0x20>; 158 #power-domain-cells = <0>; 159 }; 160 161 pd_isp0: isp0-power-domain@100240A0 { 162 compatible = "samsung,exynos4210-pd"; 163 reg = <0x100240A0 0x20>; 164 #power-domain-cells = <0>; 165 }; 166 167 pd_isp1: isp1-power-domain@100240E0 { 168 compatible = "samsung,exynos4210-pd"; 169 reg = <0x100240E0 0x20>; 170 #power-domain-cells = <0>; 171 }; 172 173 cmu: clock-controller@10030000 { 174 compatible = "samsung,exynos4415-cmu"; 175 reg = <0x10030000 0x18000>; 176 #clock-cells = <1>; 177 }; 178 179 rtc: rtc@10070000 { 180 compatible = "samsung,exynos3250-rtc"; 181 reg = <0x10070000 0x100>; 182 interrupts = <0 73 0>, <0 74 0>; 183 status = "disabled"; 184 }; 185 186 mct@10050000 { 187 compatible = "samsung,exynos4210-mct"; 188 reg = <0x10050000 0x800>; 189 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, 190 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; 191 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; 192 clock-names = "fin_pll", "mct"; 193 }; 194 195 gic: interrupt-controller@10481000 { 196 compatible = "arm,cortex-a9-gic"; 197 #interrupt-cells = <3>; 198 interrupt-controller; 199 reg = <0x10481000 0x1000>, 200 <0x10482000 0x1000>, 201 <0x10484000 0x2000>, 202 <0x10486000 0x2000>; 203 interrupts = <1 9 0xf04>; 204 }; 205 206 l2c: l2-cache-controller@10502000 { 207 compatible = "arm,pl310-cache"; 208 reg = <0x10502000 0x1000>; 209 cache-unified; 210 cache-level = <2>; 211 arm,tag-latency = <2 2 1>; 212 arm,data-latency = <3 2 1>; 213 arm,double-linefill = <1>; 214 arm,double-linefill-incr = <0>; 215 arm,double-linefill-wrap = <1>; 216 arm,prefetch-drop = <1>; 217 arm,prefetch-offset = <7>; 218 }; 219 220 cmu_dmc: clock-controller@105C0000 { 221 compatible = "samsung,exynos4415-cmu-dmc"; 222 reg = <0x105C0000 0x3000>; 223 #clock-cells = <1>; 224 }; 225 226 pinctrl_1: pinctrl@11000000 { 227 compatible = "samsung,exynos4415-pinctrl"; 228 reg = <0x11000000 0x1000>; 229 interrupts = <0 225 0>; 230 231 wakeup-interrupt-controller { 232 compatible = "samsung,exynos4210-wakeup-eint"; 233 interrupt-parent = <&gic>; 234 interrupts = <0 48 0>; 235 }; 236 }; 237 238 pinctrl_0: pinctrl@11400000 { 239 compatible = "samsung,exynos4415-pinctrl"; 240 reg = <0x11400000 0x1000>; 241 interrupts = <0 240 0>; 242 }; 243 244 fimd: fimd@11C00000 { 245 compatible = "samsung,exynos4415-fimd"; 246 reg = <0x11C00000 0x30000>; 247 interrupt-names = "fifo", "vsync", "lcd_sys"; 248 interrupts = <0 84 0>, <0 85 0>, <0 86 0>; 249 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; 250 clock-names = "sclk_fimd", "fimd"; 251 samsung,power-domain = <&pd_lcd0>; 252 samsung,sysreg = <&sysreg_system_controller>; 253 status = "disabled"; 254 }; 255 256 dsi_0: dsi@11C80000 { 257 compatible = "samsung,exynos4415-mipi-dsi"; 258 reg = <0x11C80000 0x10000>; 259 interrupts = <0 83 0>; 260 samsung,phy-type = <0>; 261 samsung,power-domain = <&pd_lcd0>; 262 phys = <&mipi_phy 1>; 263 phy-names = "dsim"; 264 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; 265 clock-names = "bus_clk", "pll_clk"; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 status = "disabled"; 269 }; 270 271 hsotg: hsotg@12480000 { 272 compatible = "samsung,s3c6400-hsotg"; 273 reg = <0x12480000 0x20000>; 274 interrupts = <0 141 0>; 275 clocks = <&cmu CLK_USBDEVICE>; 276 clock-names = "otg"; 277 phys = <&exynos_usbphy 0>; 278 phy-names = "usb2-phy"; 279 status = "disabled"; 280 }; 281 282 mshc_0: mshc@12510000 { 283 compatible = "samsung,exynos5250-dw-mshc"; 284 reg = <0x12510000 0x1000>; 285 interrupts = <0 142 0>; 286 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; 287 clock-names = "biu", "ciu"; 288 fifo-depth = <0x80>; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 status = "disabled"; 292 }; 293 294 mshc_1: mshc@12520000 { 295 compatible = "samsung,exynos5250-dw-mshc"; 296 reg = <0x12520000 0x1000>; 297 interrupts = <0 143 0>; 298 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; 299 clock-names = "biu", "ciu"; 300 fifo-depth = <0x80>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 status = "disabled"; 304 }; 305 306 mshc_2: mshc@12530000 { 307 compatible = "samsung,exynos5250-dw-mshc"; 308 reg = <0x12530000 0x1000>; 309 interrupts = <0 144 0>; 310 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; 311 clock-names = "biu", "ciu"; 312 fifo-depth = <0x80>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 status = "disabled"; 316 }; 317 318 ehci: ehci@12580000 { 319 compatible = "samsung,exynos4210-ehci"; 320 reg = <0x12580000 0x100>; 321 interrupts = <0 140 0>; 322 clocks = <&cmu CLK_USBHOST>; 323 clock-names = "usbhost"; 324 status = "disabled"; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 port@0 { 328 reg = <0>; 329 phys = <&exynos_usbphy 1>; 330 status = "disabled"; 331 }; 332 port@1 { 333 reg = <1>; 334 phys = <&exynos_usbphy 2>; 335 status = "disabled"; 336 }; 337 port@2 { 338 reg = <2>; 339 phys = <&exynos_usbphy 3>; 340 status = "disabled"; 341 }; 342 }; 343 344 ohci: ohci@12590000 { 345 compatible = "samsung,exynos4210-ohci"; 346 reg = <0x12590000 0x100>; 347 interrupts = <0 140 0>; 348 clocks = <&cmu CLK_USBHOST>; 349 clock-names = "usbhost"; 350 status = "disabled"; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 port@0 { 354 reg = <0>; 355 phys = <&exynos_usbphy 1>; 356 status = "disabled"; 357 }; 358 }; 359 360 exynos_usbphy: exynos-usbphy@125B0000 { 361 compatible = "samsung,exynos4x12-usb2-phy"; 362 reg = <0x125B0000 0x100>; 363 samsung,pmureg-phandle = <&pmu_system_controller>; 364 samsung,sysreg-phandle = <&sysreg_system_controller>; 365 clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>; 366 clock-names = "phy", "ref"; 367 #phy-cells = <1>; 368 status = "disabled"; 369 }; 370 371 amba { 372 compatible = "arm,amba-bus"; 373 #address-cells = <1>; 374 #size-cells = <1>; 375 interrupt-parent = <&gic>; 376 ranges; 377 378 pdma0: pdma@12680000 { 379 compatible = "arm,pl330", "arm,primecell"; 380 reg = <0x12680000 0x1000>; 381 interrupts = <0 138 0>; 382 clocks = <&cmu CLK_PDMA0>; 383 clock-names = "apb_pclk"; 384 #dma-cells = <1>; 385 #dma-channels = <8>; 386 #dma-requests = <32>; 387 }; 388 389 pdma1: pdma@12690000 { 390 compatible = "arm,pl330", "arm,primecell"; 391 reg = <0x12690000 0x1000>; 392 interrupts = <0 139 0>; 393 clocks = <&cmu CLK_PDMA1>; 394 clock-names = "apb_pclk"; 395 #dma-cells = <1>; 396 #dma-channels = <8>; 397 #dma-requests = <32>; 398 }; 399 }; 400 401 adc: adc@126C0000 { 402 compatible = "samsung,exynos3250-adc", 403 "samsung,exynos-adc-v2"; 404 reg = <0x126C0000 0x100>, <0x10020718 0x4>; 405 interrupts = <0 137 0>; 406 clock-names = "adc", "sclk"; 407 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; 408 #io-channel-cells = <1>; 409 io-channel-ranges; 410 status = "disabled"; 411 }; 412 413 serial_0: serial@13800000 { 414 compatible = "samsung,exynos4210-uart"; 415 reg = <0x13800000 0x100>; 416 interrupts = <0 109 0>; 417 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; 418 clock-names = "uart", "clk_uart_baud0"; 419 status = "disabled"; 420 }; 421 422 serial_1: serial@13810000 { 423 compatible = "samsung,exynos4210-uart"; 424 reg = <0x13810000 0x100>; 425 interrupts = <0 110 0>; 426 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; 427 clock-names = "uart", "clk_uart_baud0"; 428 status = "disabled"; 429 }; 430 431 serial_2: serial@13820000 { 432 compatible = "samsung,exynos4210-uart"; 433 reg = <0x13820000 0x100>; 434 interrupts = <0 111 0>; 435 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; 436 clock-names = "uart", "clk_uart_baud0"; 437 status = "disabled"; 438 }; 439 440 serial_3: serial@13830000 { 441 compatible = "samsung,exynos4210-uart"; 442 reg = <0x13830000 0x100>; 443 interrupts = <0 112 0>; 444 clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>; 445 clock-names = "uart", "clk_uart_baud0"; 446 status = "disabled"; 447 }; 448 449 i2c_0: i2c@13860000 { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 compatible = "samsung,s3c2440-i2c"; 453 reg = <0x13860000 0x100>; 454 interrupts = <0 113 0>; 455 clocks = <&cmu CLK_I2C0>; 456 clock-names = "i2c"; 457 pinctrl-names = "default"; 458 pinctrl-0 = <&i2c0_bus>; 459 status = "disabled"; 460 }; 461 462 i2c_1: i2c@13870000 { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 compatible = "samsung,s3c2440-i2c"; 466 reg = <0x13870000 0x100>; 467 interrupts = <0 114 0>; 468 clocks = <&cmu CLK_I2C1>; 469 clock-names = "i2c"; 470 pinctrl-names = "default"; 471 pinctrl-0 = <&i2c1_bus>; 472 status = "disabled"; 473 }; 474 475 i2c_2: i2c@13880000 { 476 #address-cells = <1>; 477 #size-cells = <0>; 478 compatible = "samsung,s3c2440-i2c"; 479 reg = <0x13880000 0x100>; 480 interrupts = <0 115 0>; 481 clocks = <&cmu CLK_I2C2>; 482 clock-names = "i2c"; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&i2c2_bus>; 485 status = "disabled"; 486 }; 487 488 i2c_3: i2c@13890000 { 489 #address-cells = <1>; 490 #size-cells = <0>; 491 compatible = "samsung,s3c2440-i2c"; 492 reg = <0x13890000 0x100>; 493 interrupts = <0 116 0>; 494 clocks = <&cmu CLK_I2C3>; 495 clock-names = "i2c"; 496 pinctrl-names = "default"; 497 pinctrl-0 = <&i2c3_bus>; 498 status = "disabled"; 499 }; 500 501 i2c_4: i2c@138A0000 { 502 #address-cells = <1>; 503 #size-cells = <0>; 504 compatible = "samsung,s3c2440-i2c"; 505 reg = <0x138A0000 0x100>; 506 interrupts = <0 117 0>; 507 clocks = <&cmu CLK_I2C4>; 508 clock-names = "i2c"; 509 pinctrl-names = "default"; 510 pinctrl-0 = <&i2c4_bus>; 511 status = "disabled"; 512 }; 513 514 i2c_5: i2c@138B0000 { 515 #address-cells = <1>; 516 #size-cells = <0>; 517 compatible = "samsung,s3c2440-i2c"; 518 reg = <0x138B0000 0x100>; 519 interrupts = <0 118 0>; 520 clocks = <&cmu CLK_I2C5>; 521 clock-names = "i2c"; 522 pinctrl-names = "default"; 523 pinctrl-0 = <&i2c5_bus>; 524 status = "disabled"; 525 }; 526 527 i2c_6: i2c@138C0000 { 528 #address-cells = <1>; 529 #size-cells = <0>; 530 compatible = "samsung,s3c2440-i2c"; 531 reg = <0x138C0000 0x100>; 532 interrupts = <0 119 0>; 533 clocks = <&cmu CLK_I2C6>; 534 clock-names = "i2c"; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&i2c6_bus>; 537 status = "disabled"; 538 }; 539 540 i2c_7: i2c@138D0000 { 541 #address-cells = <1>; 542 #size-cells = <0>; 543 compatible = "samsung,s3c2440-i2c"; 544 reg = <0x138D0000 0x100>; 545 interrupts = <0 120 0>; 546 clocks = <&cmu CLK_I2C7>; 547 clock-names = "i2c"; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&i2c7_bus>; 550 status = "disabled"; 551 }; 552 553 spi_0: spi@13920000 { 554 compatible = "samsung,exynos4210-spi"; 555 reg = <0x13920000 0x100>; 556 interrupts = <0 121 0>; 557 dmas = <&pdma0 7>, <&pdma0 6>; 558 dma-names = "tx", "rx"; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; 562 clock-names = "spi", "spi_busclk0"; 563 samsung,spi-src-clk = <0>; 564 pinctrl-names = "default"; 565 pinctrl-0 = <&spi0_bus>; 566 status = "disabled"; 567 }; 568 569 spi_1: spi@13930000 { 570 compatible = "samsung,exynos4210-spi"; 571 reg = <0x13930000 0x100>; 572 interrupts = <0 122 0>; 573 dmas = <&pdma1 7>, <&pdma1 6>; 574 dma-names = "tx", "rx"; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; 578 clock-names = "spi", "spi_busclk0"; 579 samsung,spi-src-clk = <0>; 580 pinctrl-names = "default"; 581 pinctrl-0 = <&spi1_bus>; 582 status = "disabled"; 583 }; 584 585 spi_2: spi@13940000 { 586 compatible = "samsung,exynos4210-spi"; 587 reg = <0x13940000 0x100>; 588 interrupts = <0 123 0>; 589 dmas = <&pdma0 9>, <&pdma0 8>; 590 dma-names = "tx", "rx"; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>; 594 clock-names = "spi", "spi_busclk0"; 595 samsung,spi-src-clk = <0>; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&spi2_bus>; 598 status = "disabled"; 599 }; 600 601 clock_audss: clock-controller@03810000 { 602 compatible = "samsung,exynos4210-audss-clock"; 603 reg = <0x03810000 0x0C>; 604 #clock-cells = <1>; 605 }; 606 607 i2s0: i2s@3830000 { 608 compatible = "samsung,s5pv210-i2s"; 609 reg = <0x03830000 0x100>; 610 interrupts = <0 124 0>; 611 clocks = <&clock_audss EXYNOS_I2S_BUS>, 612 <&clock_audss EXYNOS_SCLK_I2S>; 613 clock-names = "iis", "i2s_opclk0"; 614 dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>; 615 dma-names = "tx", "rx", "tx-sec"; 616 pinctrl-names = "default"; 617 pinctrl-0 = <&i2s0_bus>; 618 samsung,idma-addr = <0x03000000>; 619 status = "disabled"; 620 }; 621 622 pwm: pwm@139D0000 { 623 compatible = "samsung,exynos4210-pwm"; 624 reg = <0x139D0000 0x1000>; 625 interrupts = <0 104 0>, <0 105 0>, <0 106 0>, 626 <0 107 0>, <0 108 0>; 627 #pwm-cells = <3>; 628 status = "disabled"; 629 }; 630 631 pmu { 632 compatible = "arm,cortex-a9-pmu"; 633 interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>; 634 }; 635 }; 636}; 637 638#include "exynos4415-pinctrl.dtsi" 639