efm32gg.dtsi revision 279377
1279377Simp/* 2279377Simp * Device tree for Energy Micro EFM32 Giant Gecko SoC. 3279377Simp * 4279377Simp * Documentation available from 5279377Simp * http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32GG-RM.pdf 6279377Simp */ 7279377Simp#include "armv7-m.dtsi" 8279377Simp#include "dt-bindings/clock/efm32-cmu.h" 9279377Simp 10279377Simp/ { 11279377Simp aliases { 12279377Simp i2c0 = &i2c0; 13279377Simp i2c1 = &i2c1; 14279377Simp serial0 = &uart0; 15279377Simp serial1 = &uart1; 16279377Simp serial2 = &uart2; 17279377Simp serial3 = &uart3; 18279377Simp serial4 = &uart4; 19279377Simp spi0 = &spi0; 20279377Simp spi1 = &spi1; 21279377Simp spi2 = &spi2; 22279377Simp }; 23279377Simp 24279377Simp soc { 25279377Simp adc: adc@40002000 { 26279377Simp compatible = "efm32,adc"; 27279377Simp reg = <0x40002000 0x400>; 28279377Simp interrupts = <7>; 29279377Simp clocks = <&cmu clk_HFPERCLKADC0>; 30279377Simp status = "disabled"; 31279377Simp }; 32279377Simp 33279377Simp gpio: gpio@40006000 { 34279377Simp compatible = "efm32,gpio"; 35279377Simp reg = <0x40006000 0x1000>; 36279377Simp interrupts = <1 11>; 37279377Simp gpio-controller; 38279377Simp #gpio-cells = <2>; 39279377Simp interrupt-controller; 40279377Simp #interrupt-cells = <1>; 41279377Simp clocks = <&cmu clk_HFPERCLKGPIO>; 42279377Simp status = "ok"; 43279377Simp }; 44279377Simp 45279377Simp i2c0: i2c@4000a000 { 46279377Simp #address-cells = <1>; 47279377Simp #size-cells = <0>; 48279377Simp compatible = "efm32,i2c"; 49279377Simp reg = <0x4000a000 0x400>; 50279377Simp interrupts = <9>; 51279377Simp clocks = <&cmu clk_HFPERCLKI2C0>; 52279377Simp clock-frequency = <100000>; 53279377Simp status = "disabled"; 54279377Simp }; 55279377Simp 56279377Simp i2c1: i2c@4000a400 { 57279377Simp #address-cells = <1>; 58279377Simp #size-cells = <0>; 59279377Simp compatible = "efm32,i2c"; 60279377Simp reg = <0x4000a400 0x400>; 61279377Simp interrupts = <10>; 62279377Simp clocks = <&cmu clk_HFPERCLKI2C1>; 63279377Simp clock-frequency = <100000>; 64279377Simp status = "disabled"; 65279377Simp }; 66279377Simp 67279377Simp spi0: spi@4000c000 { /* USART0 */ 68279377Simp #address-cells = <1>; 69279377Simp #size-cells = <0>; 70279377Simp compatible = "efm32,spi"; 71279377Simp reg = <0x4000c000 0x400>; 72279377Simp interrupts = <3 4>; 73279377Simp clocks = <&cmu clk_HFPERCLKUSART0>; 74279377Simp status = "disabled"; 75279377Simp }; 76279377Simp 77279377Simp spi1: spi@4000c400 { /* USART1 */ 78279377Simp #address-cells = <1>; 79279377Simp #size-cells = <0>; 80279377Simp compatible = "efm32,spi"; 81279377Simp reg = <0x4000c400 0x400>; 82279377Simp interrupts = <15 16>; 83279377Simp clocks = <&cmu clk_HFPERCLKUSART1>; 84279377Simp status = "disabled"; 85279377Simp }; 86279377Simp 87279377Simp spi2: spi@4000c800 { /* USART2 */ 88279377Simp #address-cells = <1>; 89279377Simp #size-cells = <0>; 90279377Simp compatible = "efm32,spi"; 91279377Simp reg = <0x4000c800 0x400>; 92279377Simp interrupts = <18 19>; 93279377Simp clocks = <&cmu clk_HFPERCLKUSART2>; 94279377Simp status = "disabled"; 95279377Simp }; 96279377Simp 97279377Simp uart0: uart@4000c000 { /* USART0 */ 98279377Simp compatible = "efm32,uart"; 99279377Simp reg = <0x4000c000 0x400>; 100279377Simp interrupts = <3 4>; 101279377Simp clocks = <&cmu clk_HFPERCLKUSART0>; 102279377Simp status = "disabled"; 103279377Simp }; 104279377Simp 105279377Simp uart1: uart@4000c400 { /* USART1 */ 106279377Simp compatible = "efm32,uart"; 107279377Simp reg = <0x4000c400 0x400>; 108279377Simp interrupts = <15 16>; 109279377Simp clocks = <&cmu clk_HFPERCLKUSART1>; 110279377Simp status = "disabled"; 111279377Simp }; 112279377Simp 113279377Simp uart2: uart@4000c800 { /* USART2 */ 114279377Simp compatible = "efm32,uart"; 115279377Simp reg = <0x4000c800 0x400>; 116279377Simp interrupts = <18 19>; 117279377Simp clocks = <&cmu clk_HFPERCLKUSART2>; 118279377Simp status = "disabled"; 119279377Simp }; 120279377Simp 121279377Simp uart3: uart@4000e000 { /* UART0 */ 122279377Simp compatible = "efm32,uart"; 123279377Simp reg = <0x4000e000 0x400>; 124279377Simp interrupts = <20 21>; 125279377Simp clocks = <&cmu clk_HFPERCLKUART0>; 126279377Simp status = "disabled"; 127279377Simp }; 128279377Simp 129279377Simp uart4: uart@4000e400 { /* UART1 */ 130279377Simp compatible = "efm32,uart"; 131279377Simp reg = <0x4000e400 0x400>; 132279377Simp interrupts = <22 23>; 133279377Simp clocks = <&cmu clk_HFPERCLKUART1>; 134279377Simp status = "disabled"; 135279377Simp }; 136279377Simp 137279377Simp timer0: timer@40010000 { 138279377Simp compatible = "efm32,timer"; 139279377Simp reg = <0x40010000 0x400>; 140279377Simp interrupts = <2>; 141279377Simp clocks = <&cmu clk_HFPERCLKTIMER0>; 142279377Simp }; 143279377Simp 144279377Simp timer1: timer@40010400 { 145279377Simp compatible = "efm32,timer"; 146279377Simp reg = <0x40010400 0x400>; 147279377Simp interrupts = <12>; 148279377Simp clocks = <&cmu clk_HFPERCLKTIMER1>; 149279377Simp }; 150279377Simp 151279377Simp timer2: timer@40010800 { 152279377Simp compatible = "efm32,timer"; 153279377Simp reg = <0x40010800 0x400>; 154279377Simp interrupts = <13>; 155279377Simp clocks = <&cmu clk_HFPERCLKTIMER2>; 156279377Simp }; 157279377Simp 158279377Simp timer3: timer@40010c00 { 159279377Simp compatible = "efm32,timer"; 160279377Simp reg = <0x40010c00 0x400>; 161279377Simp interrupts = <14>; 162279377Simp clocks = <&cmu clk_HFPERCLKTIMER3>; 163279377Simp }; 164279377Simp 165279377Simp cmu: cmu@400c8000 { 166279377Simp compatible = "efm32gg,cmu"; 167279377Simp reg = <0x400c8000 0x400>; 168279377Simp interrupts = <32>; 169279377Simp #clock-cells = <1>; 170279377Simp }; 171279377Simp }; 172279377Simp}; 173