dra74x.dtsi revision 302408
1256124Sjhb/* 2256124Sjhb * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 3283927Sjhb * 4256124Sjhb * This program is free software; you can redistribute it and/or modify 5256124Sjhb * it under the terms of the GNU General Public License version 2 as 6256124Sjhb * published by the Free Software Foundation. 7256124Sjhb * Based on "omap4.dtsi" 8256124Sjhb */ 9256124Sjhb 10256124Sjhb#include "dra7.dtsi" 11256124Sjhb 12256124Sjhb/ { 13256124Sjhb compatible = "ti,dra742", "ti,dra74", "ti,dra7"; 14256124Sjhb 15256124Sjhb cpus { 16256124Sjhb #address-cells = <1>; 17256124Sjhb #size-cells = <0>; 18256124Sjhb 19256124Sjhb cpu0: cpu@0 { 20256124Sjhb device_type = "cpu"; 21256124Sjhb compatible = "arm,cortex-a15"; 22256124Sjhb reg = <0>; 23256124Sjhb 24256124Sjhb operating-points = < 25256124Sjhb /* kHz uV */ 26256124Sjhb 1000000 1060000 27256124Sjhb 1176000 1160000 28256124Sjhb >; 29256124Sjhb 30256124Sjhb clocks = <&dpll_mpu_ck>; 31256124Sjhb clock-names = "cpu"; 32256124Sjhb 33256124Sjhb clock-latency = <300000>; /* From omap-cpufreq driver */ 34256124Sjhb 35256124Sjhb /* cooling options */ 36256124Sjhb cooling-min-level = <0>; 37256124Sjhb cooling-max-level = <2>; 38256124Sjhb #cooling-cells = <2>; /* min followed by max */ 39256124Sjhb }; 40256124Sjhb cpu@1 { 41256124Sjhb device_type = "cpu"; 42256124Sjhb compatible = "arm,cortex-a15"; 43256124Sjhb reg = <1>; 44256124Sjhb }; 45256124Sjhb }; 46256124Sjhb 47256124Sjhb pmu { 48256124Sjhb compatible = "arm,cortex-a15-pmu"; 49256124Sjhb interrupt-parent = <&wakeupgen>; 50256124Sjhb interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 51256124Sjhb <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 52256124Sjhb }; 53256124Sjhb 54256124Sjhb ocp { 55256124Sjhb dsp2_system: dsp_system@41500000 { 56256124Sjhb compatible = "syscon"; 57256124Sjhb reg = <0x41500000 0x100>; 58256124Sjhb }; 59256124Sjhb 60256124Sjhb omap_dwc3_4: omap_dwc3_4@48940000 { 61256124Sjhb compatible = "ti,dwc3"; 62256124Sjhb ti,hwmods = "usb_otg_ss4"; 63256124Sjhb reg = <0x48940000 0x10000>; 64256124Sjhb interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 65256124Sjhb #address-cells = <1>; 66256124Sjhb #size-cells = <1>; 67256124Sjhb utmi-mode = <2>; 68256124Sjhb ranges; 69256124Sjhb status = "disabled"; 70256124Sjhb usb4: usb@48950000 { 71256124Sjhb compatible = "snps,dwc3"; 72256124Sjhb reg = <0x48950000 0x17000>; 73256124Sjhb interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 74256124Sjhb <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 75256124Sjhb <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 76256124Sjhb interrupt-names = "peripheral", 77256124Sjhb "host", 78256124Sjhb "otg"; 79256124Sjhb tx-fifo-resize; 80256124Sjhb maximum-speed = "high-speed"; 81256124Sjhb dr_mode = "otg"; 82256124Sjhb }; 83256124Sjhb }; 84256124Sjhb 85 mmu0_dsp2: mmu@41501000 { 86 compatible = "ti,dra7-dsp-iommu"; 87 reg = <0x41501000 0x100>; 88 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 89 ti,hwmods = "mmu0_dsp2"; 90 #iommu-cells = <0>; 91 ti,syscon-mmuconfig = <&dsp2_system 0x0>; 92 status = "disabled"; 93 }; 94 95 mmu1_dsp2: mmu@41502000 { 96 compatible = "ti,dra7-dsp-iommu"; 97 reg = <0x41502000 0x100>; 98 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 99 ti,hwmods = "mmu1_dsp2"; 100 #iommu-cells = <0>; 101 ti,syscon-mmuconfig = <&dsp2_system 0x1>; 102 status = "disabled"; 103 }; 104 }; 105}; 106 107&dss { 108 reg = <0x58000000 0x80>, 109 <0x58004054 0x4>, 110 <0x58004300 0x20>, 111 <0x58005054 0x4>, 112 <0x58005300 0x20>; 113 reg-names = "dss", "pll1_clkctrl", "pll1", 114 "pll2_clkctrl", "pll2"; 115 116 clocks = <&dss_dss_clk>, 117 <&dss_video1_clk>, 118 <&dss_video2_clk>; 119 clock-names = "fck", "video1_clk", "video2_clk"; 120}; 121 122&mailbox5 { 123 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { 124 ti,mbox-tx = <6 2 2>; 125 ti,mbox-rx = <4 2 2>; 126 status = "disabled"; 127 }; 128 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { 129 ti,mbox-tx = <5 2 2>; 130 ti,mbox-rx = <1 2 2>; 131 status = "disabled"; 132 }; 133}; 134 135&mailbox6 { 136 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { 137 ti,mbox-tx = <6 2 2>; 138 ti,mbox-rx = <4 2 2>; 139 status = "disabled"; 140 }; 141 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { 142 ti,mbox-tx = <5 2 2>; 143 ti,mbox-rx = <1 2 2>; 144 status = "disabled"; 145 }; 146}; 147