dra74x.dtsi revision 295436
1279377Simp/* 2279377Simp * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 3279377Simp * 4279377Simp * This program is free software; you can redistribute it and/or modify 5279377Simp * it under the terms of the GNU General Public License version 2 as 6279377Simp * published by the Free Software Foundation. 7279377Simp * Based on "omap4.dtsi" 8279377Simp */ 9279377Simp 10279377Simp#include "dra7.dtsi" 11279377Simp 12279377Simp/ { 13279377Simp compatible = "ti,dra742", "ti,dra74", "ti,dra7"; 14279377Simp 15279377Simp cpus { 16279377Simp #address-cells = <1>; 17279377Simp #size-cells = <0>; 18279377Simp 19279377Simp cpu0: cpu@0 { 20279377Simp device_type = "cpu"; 21279377Simp compatible = "arm,cortex-a15"; 22279377Simp reg = <0>; 23279377Simp 24279377Simp operating-points = < 25279377Simp /* kHz uV */ 26279377Simp 1000000 1060000 27279377Simp 1176000 1160000 28279377Simp >; 29279377Simp 30279377Simp clocks = <&dpll_mpu_ck>; 31279377Simp clock-names = "cpu"; 32279377Simp 33279377Simp clock-latency = <300000>; /* From omap-cpufreq driver */ 34295436Sandrew 35295436Sandrew /* cooling options */ 36295436Sandrew cooling-min-level = <0>; 37295436Sandrew cooling-max-level = <2>; 38295436Sandrew #cooling-cells = <2>; /* min followed by max */ 39279377Simp }; 40279377Simp cpu@1 { 41279377Simp device_type = "cpu"; 42279377Simp compatible = "arm,cortex-a15"; 43279377Simp reg = <1>; 44279377Simp }; 45279377Simp }; 46279377Simp 47279377Simp pmu { 48279377Simp compatible = "arm,cortex-a15-pmu"; 49295436Sandrew interrupt-parent = <&wakeupgen>; 50295436Sandrew interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 51295436Sandrew <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 52279377Simp }; 53279377Simp 54279377Simp ocp { 55295436Sandrew dsp2_system: dsp_system@41500000 { 56295436Sandrew compatible = "syscon"; 57295436Sandrew reg = <0x41500000 0x100>; 58295436Sandrew }; 59295436Sandrew 60279377Simp omap_dwc3_4: omap_dwc3_4@48940000 { 61279377Simp compatible = "ti,dwc3"; 62279377Simp ti,hwmods = "usb_otg_ss4"; 63279377Simp reg = <0x48940000 0x10000>; 64279377Simp interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 65279377Simp #address-cells = <1>; 66279377Simp #size-cells = <1>; 67279377Simp utmi-mode = <2>; 68279377Simp ranges; 69279377Simp status = "disabled"; 70279377Simp usb4: usb@48950000 { 71279377Simp compatible = "snps,dwc3"; 72279377Simp reg = <0x48950000 0x17000>; 73295436Sandrew interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 74295436Sandrew <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 75295436Sandrew <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 76295436Sandrew interrupt-names = "peripheral", 77295436Sandrew "host", 78295436Sandrew "otg"; 79279377Simp tx-fifo-resize; 80279377Simp maximum-speed = "high-speed"; 81279377Simp dr_mode = "otg"; 82279377Simp }; 83279377Simp }; 84295436Sandrew 85295436Sandrew mmu0_dsp2: mmu@41501000 { 86295436Sandrew compatible = "ti,dra7-dsp-iommu"; 87295436Sandrew reg = <0x41501000 0x100>; 88295436Sandrew interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 89295436Sandrew ti,hwmods = "mmu0_dsp2"; 90295436Sandrew #iommu-cells = <0>; 91295436Sandrew ti,syscon-mmuconfig = <&dsp2_system 0x0>; 92295436Sandrew status = "disabled"; 93295436Sandrew }; 94295436Sandrew 95295436Sandrew mmu1_dsp2: mmu@41502000 { 96295436Sandrew compatible = "ti,dra7-dsp-iommu"; 97295436Sandrew reg = <0x41502000 0x100>; 98295436Sandrew interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 99295436Sandrew ti,hwmods = "mmu1_dsp2"; 100295436Sandrew #iommu-cells = <0>; 101295436Sandrew ti,syscon-mmuconfig = <&dsp2_system 0x1>; 102295436Sandrew status = "disabled"; 103295436Sandrew }; 104279377Simp }; 105279377Simp}; 106295436Sandrew 107295436Sandrew&dss { 108295436Sandrew reg = <0x58000000 0x80>, 109295436Sandrew <0x58004054 0x4>, 110295436Sandrew <0x58004300 0x20>, 111295436Sandrew <0x58005054 0x4>, 112295436Sandrew <0x58005300 0x20>; 113295436Sandrew reg-names = "dss", "pll1_clkctrl", "pll1", 114295436Sandrew "pll2_clkctrl", "pll2"; 115295436Sandrew 116295436Sandrew clocks = <&dss_dss_clk>, 117295436Sandrew <&dss_video1_clk>, 118295436Sandrew <&dss_video2_clk>; 119295436Sandrew clock-names = "fck", "video1_clk", "video2_clk"; 120295436Sandrew}; 121295436Sandrew 122295436Sandrew&mailbox5 { 123295436Sandrew mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { 124295436Sandrew ti,mbox-tx = <6 2 2>; 125295436Sandrew ti,mbox-rx = <4 2 2>; 126295436Sandrew status = "disabled"; 127295436Sandrew }; 128295436Sandrew mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { 129295436Sandrew ti,mbox-tx = <5 2 2>; 130295436Sandrew ti,mbox-rx = <1 2 2>; 131295436Sandrew status = "disabled"; 132295436Sandrew }; 133295436Sandrew}; 134295436Sandrew 135295436Sandrew&mailbox6 { 136295436Sandrew mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { 137295436Sandrew ti,mbox-tx = <6 2 2>; 138295436Sandrew ti,mbox-rx = <4 2 2>; 139295436Sandrew status = "disabled"; 140295436Sandrew }; 141295436Sandrew mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { 142295436Sandrew ti,mbox-tx = <5 2 2>; 143295436Sandrew ti,mbox-rx = <1 2 2>; 144295436Sandrew status = "disabled"; 145295436Sandrew }; 146295436Sandrew}; 147