dra7.dtsi revision 279377
1279377Simp/* 2279377Simp * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3279377Simp * 4279377Simp * This program is free software; you can redistribute it and/or modify 5279377Simp * it under the terms of the GNU General Public License version 2 as 6279377Simp * published by the Free Software Foundation. 7279377Simp * Based on "omap4.dtsi" 8279377Simp */ 9279377Simp 10279377Simp#include <dt-bindings/interrupt-controller/arm-gic.h> 11279377Simp#include <dt-bindings/pinctrl/dra.h> 12279377Simp 13279377Simp#include "skeleton.dtsi" 14279377Simp 15279377Simp#define MAX_SOURCES 400 16279377Simp#define DIRECT_IRQ(irq) (MAX_SOURCES + irq) 17279377Simp 18279377Simp/ { 19279377Simp #address-cells = <1>; 20279377Simp #size-cells = <1>; 21279377Simp 22279377Simp compatible = "ti,dra7xx"; 23279377Simp interrupt-parent = <&gic>; 24279377Simp 25279377Simp aliases { 26279377Simp i2c0 = &i2c1; 27279377Simp i2c1 = &i2c2; 28279377Simp i2c2 = &i2c3; 29279377Simp i2c3 = &i2c4; 30279377Simp i2c4 = &i2c5; 31279377Simp serial0 = &uart1; 32279377Simp serial1 = &uart2; 33279377Simp serial2 = &uart3; 34279377Simp serial3 = &uart4; 35279377Simp serial4 = &uart5; 36279377Simp serial5 = &uart6; 37279377Simp serial6 = &uart7; 38279377Simp serial7 = &uart8; 39279377Simp serial8 = &uart9; 40279377Simp serial9 = &uart10; 41279377Simp ethernet0 = &cpsw_emac0; 42279377Simp ethernet1 = &cpsw_emac1; 43279377Simp d_can0 = &dcan1; 44279377Simp d_can1 = &dcan2; 45279377Simp }; 46279377Simp 47279377Simp timer { 48279377Simp compatible = "arm,armv7-timer"; 49279377Simp interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 50279377Simp <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 51279377Simp <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 52279377Simp <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 53279377Simp }; 54279377Simp 55279377Simp gic: interrupt-controller@48211000 { 56279377Simp compatible = "arm,cortex-a15-gic"; 57279377Simp interrupt-controller; 58279377Simp #interrupt-cells = <3>; 59279377Simp arm,routable-irqs = <192>; 60279377Simp reg = <0x48211000 0x1000>, 61279377Simp <0x48212000 0x1000>, 62279377Simp <0x48214000 0x2000>, 63279377Simp <0x48216000 0x2000>; 64279377Simp interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 65279377Simp }; 66279377Simp 67279377Simp /* 68279377Simp * The soc node represents the soc top level view. It is used for IPs 69279377Simp * that are not memory mapped in the MPU view or for the MPU itself. 70279377Simp */ 71279377Simp soc { 72279377Simp compatible = "ti,omap-infra"; 73279377Simp mpu { 74279377Simp compatible = "ti,omap5-mpu"; 75279377Simp ti,hwmods = "mpu"; 76279377Simp }; 77279377Simp }; 78279377Simp 79279377Simp /* 80279377Simp * XXX: Use a flat representation of the SOC interconnect. 81279377Simp * The real OMAP interconnect network is quite complex. 82279377Simp * Since it will not bring real advantage to represent that in DT for 83279377Simp * the moment, just use a fake OCP bus entry to represent the whole bus 84279377Simp * hierarchy. 85279377Simp */ 86279377Simp ocp { 87279377Simp compatible = "ti,dra7-l3-noc", "simple-bus"; 88279377Simp #address-cells = <1>; 89279377Simp #size-cells = <1>; 90279377Simp ranges; 91279377Simp ti,hwmods = "l3_main_1", "l3_main_2"; 92279377Simp reg = <0x44000000 0x1000000>, 93279377Simp <0x45000000 0x1000>; 94279377Simp interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 95279377Simp <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; 96279377Simp 97279377Simp prm: prm@4ae06000 { 98279377Simp compatible = "ti,dra7-prm"; 99279377Simp reg = <0x4ae06000 0x3000>; 100279377Simp interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 101279377Simp 102279377Simp prm_clocks: clocks { 103279377Simp #address-cells = <1>; 104279377Simp #size-cells = <0>; 105279377Simp }; 106279377Simp 107279377Simp prm_clockdomains: clockdomains { 108279377Simp }; 109279377Simp }; 110279377Simp 111279377Simp axi@0 { 112279377Simp compatible = "simple-bus"; 113279377Simp #size-cells = <1>; 114279377Simp #address-cells = <1>; 115279377Simp ranges = <0x51000000 0x51000000 0x3000 116279377Simp 0x0 0x20000000 0x10000000>; 117279377Simp pcie@51000000 { 118279377Simp compatible = "ti,dra7-pcie"; 119279377Simp reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; 120279377Simp reg-names = "rc_dbics", "ti_conf", "config"; 121279377Simp interrupts = <0 232 0x4>, <0 233 0x4>; 122279377Simp #address-cells = <3>; 123279377Simp #size-cells = <2>; 124279377Simp device_type = "pci"; 125279377Simp ranges = <0x81000000 0 0 0x03000 0 0x00010000 126279377Simp 0x82000000 0 0x20013000 0x13000 0 0xffed000>; 127279377Simp #interrupt-cells = <1>; 128279377Simp num-lanes = <1>; 129279377Simp ti,hwmods = "pcie1"; 130279377Simp phys = <&pcie1_phy>; 131279377Simp phy-names = "pcie-phy0"; 132279377Simp interrupt-map-mask = <0 0 0 7>; 133279377Simp interrupt-map = <0 0 0 1 &pcie1_intc 1>, 134279377Simp <0 0 0 2 &pcie1_intc 2>, 135279377Simp <0 0 0 3 &pcie1_intc 3>, 136279377Simp <0 0 0 4 &pcie1_intc 4>; 137279377Simp pcie1_intc: interrupt-controller { 138279377Simp interrupt-controller; 139279377Simp #address-cells = <0>; 140279377Simp #interrupt-cells = <1>; 141279377Simp }; 142279377Simp }; 143279377Simp }; 144279377Simp 145279377Simp axi@1 { 146279377Simp compatible = "simple-bus"; 147279377Simp #size-cells = <1>; 148279377Simp #address-cells = <1>; 149279377Simp ranges = <0x51800000 0x51800000 0x3000 150279377Simp 0x0 0x30000000 0x10000000>; 151279377Simp status = "disabled"; 152279377Simp pcie@51000000 { 153279377Simp compatible = "ti,dra7-pcie"; 154279377Simp reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; 155279377Simp reg-names = "rc_dbics", "ti_conf", "config"; 156279377Simp interrupts = <0 355 0x4>, <0 356 0x4>; 157279377Simp #address-cells = <3>; 158279377Simp #size-cells = <2>; 159279377Simp device_type = "pci"; 160279377Simp ranges = <0x81000000 0 0 0x03000 0 0x00010000 161279377Simp 0x82000000 0 0x30013000 0x13000 0 0xffed000>; 162279377Simp #interrupt-cells = <1>; 163279377Simp num-lanes = <1>; 164279377Simp ti,hwmods = "pcie2"; 165279377Simp phys = <&pcie2_phy>; 166279377Simp phy-names = "pcie-phy0"; 167279377Simp interrupt-map-mask = <0 0 0 7>; 168279377Simp interrupt-map = <0 0 0 1 &pcie2_intc 1>, 169279377Simp <0 0 0 2 &pcie2_intc 2>, 170279377Simp <0 0 0 3 &pcie2_intc 3>, 171279377Simp <0 0 0 4 &pcie2_intc 4>; 172279377Simp pcie2_intc: interrupt-controller { 173279377Simp interrupt-controller; 174279377Simp #address-cells = <0>; 175279377Simp #interrupt-cells = <1>; 176279377Simp }; 177279377Simp }; 178279377Simp }; 179279377Simp 180279377Simp cm_core_aon: cm_core_aon@4a005000 { 181279377Simp compatible = "ti,dra7-cm-core-aon"; 182279377Simp reg = <0x4a005000 0x2000>; 183279377Simp 184279377Simp cm_core_aon_clocks: clocks { 185279377Simp #address-cells = <1>; 186279377Simp #size-cells = <0>; 187279377Simp }; 188279377Simp 189279377Simp cm_core_aon_clockdomains: clockdomains { 190279377Simp }; 191279377Simp }; 192279377Simp 193279377Simp cm_core: cm_core@4a008000 { 194279377Simp compatible = "ti,dra7-cm-core"; 195279377Simp reg = <0x4a008000 0x3000>; 196279377Simp 197279377Simp cm_core_clocks: clocks { 198279377Simp #address-cells = <1>; 199279377Simp #size-cells = <0>; 200279377Simp }; 201279377Simp 202279377Simp cm_core_clockdomains: clockdomains { 203279377Simp }; 204279377Simp }; 205279377Simp 206279377Simp counter32k: counter@4ae04000 { 207279377Simp compatible = "ti,omap-counter32k"; 208279377Simp reg = <0x4ae04000 0x40>; 209279377Simp ti,hwmods = "counter_32k"; 210279377Simp }; 211279377Simp 212279377Simp dra7_ctrl_core: ctrl_core@4a002000 { 213279377Simp compatible = "syscon"; 214279377Simp reg = <0x4a002000 0x6d0>; 215279377Simp }; 216279377Simp 217279377Simp dra7_ctrl_general: tisyscon@4a002e00 { 218279377Simp compatible = "syscon"; 219279377Simp reg = <0x4a002e00 0x7c>; 220279377Simp }; 221279377Simp 222279377Simp pbias_regulator: pbias_regulator { 223279377Simp compatible = "ti,pbias-omap"; 224279377Simp reg = <0 0x4>; 225279377Simp syscon = <&dra7_ctrl_general>; 226279377Simp pbias_mmc_reg: pbias_mmc_omap5 { 227279377Simp regulator-name = "pbias_mmc_omap5"; 228279377Simp regulator-min-microvolt = <1800000>; 229279377Simp regulator-max-microvolt = <3000000>; 230279377Simp }; 231279377Simp }; 232279377Simp 233279377Simp dra7_pmx_core: pinmux@4a003400 { 234279377Simp compatible = "ti,dra7-padconf", "pinctrl-single"; 235279377Simp reg = <0x4a003400 0x0464>; 236279377Simp #address-cells = <1>; 237279377Simp #size-cells = <0>; 238279377Simp #interrupt-cells = <1>; 239279377Simp interrupt-controller; 240279377Simp pinctrl-single,register-width = <32>; 241279377Simp pinctrl-single,function-mask = <0x3fffffff>; 242279377Simp }; 243279377Simp 244279377Simp sdma: dma-controller@4a056000 { 245279377Simp compatible = "ti,omap4430-sdma"; 246279377Simp reg = <0x4a056000 0x1000>; 247279377Simp interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 248279377Simp <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 249279377Simp <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 250279377Simp <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 251279377Simp #dma-cells = <1>; 252279377Simp #dma-channels = <32>; 253279377Simp #dma-requests = <127>; 254279377Simp }; 255279377Simp 256279377Simp gpio1: gpio@4ae10000 { 257279377Simp compatible = "ti,omap4-gpio"; 258279377Simp reg = <0x4ae10000 0x200>; 259279377Simp interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 260279377Simp ti,hwmods = "gpio1"; 261279377Simp gpio-controller; 262279377Simp #gpio-cells = <2>; 263279377Simp interrupt-controller; 264279377Simp #interrupt-cells = <2>; 265279377Simp }; 266279377Simp 267279377Simp gpio2: gpio@48055000 { 268279377Simp compatible = "ti,omap4-gpio"; 269279377Simp reg = <0x48055000 0x200>; 270279377Simp interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 271279377Simp ti,hwmods = "gpio2"; 272279377Simp gpio-controller; 273279377Simp #gpio-cells = <2>; 274279377Simp interrupt-controller; 275279377Simp #interrupt-cells = <2>; 276279377Simp }; 277279377Simp 278279377Simp gpio3: gpio@48057000 { 279279377Simp compatible = "ti,omap4-gpio"; 280279377Simp reg = <0x48057000 0x200>; 281279377Simp interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 282279377Simp ti,hwmods = "gpio3"; 283279377Simp gpio-controller; 284279377Simp #gpio-cells = <2>; 285279377Simp interrupt-controller; 286279377Simp #interrupt-cells = <2>; 287279377Simp }; 288279377Simp 289279377Simp gpio4: gpio@48059000 { 290279377Simp compatible = "ti,omap4-gpio"; 291279377Simp reg = <0x48059000 0x200>; 292279377Simp interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 293279377Simp ti,hwmods = "gpio4"; 294279377Simp gpio-controller; 295279377Simp #gpio-cells = <2>; 296279377Simp interrupt-controller; 297279377Simp #interrupt-cells = <2>; 298279377Simp }; 299279377Simp 300279377Simp gpio5: gpio@4805b000 { 301279377Simp compatible = "ti,omap4-gpio"; 302279377Simp reg = <0x4805b000 0x200>; 303279377Simp interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 304279377Simp ti,hwmods = "gpio5"; 305279377Simp gpio-controller; 306279377Simp #gpio-cells = <2>; 307279377Simp interrupt-controller; 308279377Simp #interrupt-cells = <2>; 309279377Simp }; 310279377Simp 311279377Simp gpio6: gpio@4805d000 { 312279377Simp compatible = "ti,omap4-gpio"; 313279377Simp reg = <0x4805d000 0x200>; 314279377Simp interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 315279377Simp ti,hwmods = "gpio6"; 316279377Simp gpio-controller; 317279377Simp #gpio-cells = <2>; 318279377Simp interrupt-controller; 319279377Simp #interrupt-cells = <2>; 320279377Simp }; 321279377Simp 322279377Simp gpio7: gpio@48051000 { 323279377Simp compatible = "ti,omap4-gpio"; 324279377Simp reg = <0x48051000 0x200>; 325279377Simp interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 326279377Simp ti,hwmods = "gpio7"; 327279377Simp gpio-controller; 328279377Simp #gpio-cells = <2>; 329279377Simp interrupt-controller; 330279377Simp #interrupt-cells = <2>; 331279377Simp }; 332279377Simp 333279377Simp gpio8: gpio@48053000 { 334279377Simp compatible = "ti,omap4-gpio"; 335279377Simp reg = <0x48053000 0x200>; 336279377Simp interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 337279377Simp ti,hwmods = "gpio8"; 338279377Simp gpio-controller; 339279377Simp #gpio-cells = <2>; 340279377Simp interrupt-controller; 341279377Simp #interrupt-cells = <2>; 342279377Simp }; 343279377Simp 344279377Simp uart1: serial@4806a000 { 345279377Simp compatible = "ti,omap4-uart"; 346279377Simp reg = <0x4806a000 0x100>; 347279377Simp interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 348279377Simp ti,hwmods = "uart1"; 349279377Simp clock-frequency = <48000000>; 350279377Simp status = "disabled"; 351279377Simp dmas = <&sdma 49>, <&sdma 50>; 352279377Simp dma-names = "tx", "rx"; 353279377Simp }; 354279377Simp 355279377Simp uart2: serial@4806c000 { 356279377Simp compatible = "ti,omap4-uart"; 357279377Simp reg = <0x4806c000 0x100>; 358279377Simp interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 359279377Simp ti,hwmods = "uart2"; 360279377Simp clock-frequency = <48000000>; 361279377Simp status = "disabled"; 362279377Simp dmas = <&sdma 51>, <&sdma 52>; 363279377Simp dma-names = "tx", "rx"; 364279377Simp }; 365279377Simp 366279377Simp uart3: serial@48020000 { 367279377Simp compatible = "ti,omap4-uart"; 368279377Simp reg = <0x48020000 0x100>; 369279377Simp interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 370279377Simp ti,hwmods = "uart3"; 371279377Simp clock-frequency = <48000000>; 372279377Simp status = "disabled"; 373279377Simp dmas = <&sdma 53>, <&sdma 54>; 374279377Simp dma-names = "tx", "rx"; 375279377Simp }; 376279377Simp 377279377Simp uart4: serial@4806e000 { 378279377Simp compatible = "ti,omap4-uart"; 379279377Simp reg = <0x4806e000 0x100>; 380279377Simp interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 381279377Simp ti,hwmods = "uart4"; 382279377Simp clock-frequency = <48000000>; 383279377Simp status = "disabled"; 384279377Simp dmas = <&sdma 55>, <&sdma 56>; 385279377Simp dma-names = "tx", "rx"; 386279377Simp }; 387279377Simp 388279377Simp uart5: serial@48066000 { 389279377Simp compatible = "ti,omap4-uart"; 390279377Simp reg = <0x48066000 0x100>; 391279377Simp interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 392279377Simp ti,hwmods = "uart5"; 393279377Simp clock-frequency = <48000000>; 394279377Simp status = "disabled"; 395279377Simp dmas = <&sdma 63>, <&sdma 64>; 396279377Simp dma-names = "tx", "rx"; 397279377Simp }; 398279377Simp 399279377Simp uart6: serial@48068000 { 400279377Simp compatible = "ti,omap4-uart"; 401279377Simp reg = <0x48068000 0x100>; 402279377Simp interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 403279377Simp ti,hwmods = "uart6"; 404279377Simp clock-frequency = <48000000>; 405279377Simp status = "disabled"; 406279377Simp dmas = <&sdma 79>, <&sdma 80>; 407279377Simp dma-names = "tx", "rx"; 408279377Simp }; 409279377Simp 410279377Simp uart7: serial@48420000 { 411279377Simp compatible = "ti,omap4-uart"; 412279377Simp reg = <0x48420000 0x100>; 413279377Simp interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 414279377Simp ti,hwmods = "uart7"; 415279377Simp clock-frequency = <48000000>; 416279377Simp status = "disabled"; 417279377Simp }; 418279377Simp 419279377Simp uart8: serial@48422000 { 420279377Simp compatible = "ti,omap4-uart"; 421279377Simp reg = <0x48422000 0x100>; 422279377Simp interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 423279377Simp ti,hwmods = "uart8"; 424279377Simp clock-frequency = <48000000>; 425279377Simp status = "disabled"; 426279377Simp }; 427279377Simp 428279377Simp uart9: serial@48424000 { 429279377Simp compatible = "ti,omap4-uart"; 430279377Simp reg = <0x48424000 0x100>; 431279377Simp interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 432279377Simp ti,hwmods = "uart9"; 433279377Simp clock-frequency = <48000000>; 434279377Simp status = "disabled"; 435279377Simp }; 436279377Simp 437279377Simp uart10: serial@4ae2b000 { 438279377Simp compatible = "ti,omap4-uart"; 439279377Simp reg = <0x4ae2b000 0x100>; 440279377Simp interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 441279377Simp ti,hwmods = "uart10"; 442279377Simp clock-frequency = <48000000>; 443279377Simp status = "disabled"; 444279377Simp }; 445279377Simp 446279377Simp mailbox1: mailbox@4a0f4000 { 447279377Simp compatible = "ti,omap4-mailbox"; 448279377Simp reg = <0x4a0f4000 0x200>; 449279377Simp interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 450279377Simp <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 451279377Simp <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 452279377Simp ti,hwmods = "mailbox1"; 453279377Simp #mbox-cells = <1>; 454279377Simp ti,mbox-num-users = <3>; 455279377Simp ti,mbox-num-fifos = <8>; 456279377Simp status = "disabled"; 457279377Simp }; 458279377Simp 459279377Simp mailbox2: mailbox@4883a000 { 460279377Simp compatible = "ti,omap4-mailbox"; 461279377Simp reg = <0x4883a000 0x200>; 462279377Simp interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 463279377Simp <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 464279377Simp <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 465279377Simp <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 466279377Simp ti,hwmods = "mailbox2"; 467279377Simp #mbox-cells = <1>; 468279377Simp ti,mbox-num-users = <4>; 469279377Simp ti,mbox-num-fifos = <12>; 470279377Simp status = "disabled"; 471279377Simp }; 472279377Simp 473279377Simp mailbox3: mailbox@4883c000 { 474279377Simp compatible = "ti,omap4-mailbox"; 475279377Simp reg = <0x4883c000 0x200>; 476279377Simp interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 477279377Simp <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 478279377Simp <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 479279377Simp <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 480279377Simp ti,hwmods = "mailbox3"; 481279377Simp #mbox-cells = <1>; 482279377Simp ti,mbox-num-users = <4>; 483279377Simp ti,mbox-num-fifos = <12>; 484279377Simp status = "disabled"; 485279377Simp }; 486279377Simp 487279377Simp mailbox4: mailbox@4883e000 { 488279377Simp compatible = "ti,omap4-mailbox"; 489279377Simp reg = <0x4883e000 0x200>; 490279377Simp interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 491279377Simp <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 492279377Simp <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 493279377Simp <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 494279377Simp ti,hwmods = "mailbox4"; 495279377Simp #mbox-cells = <1>; 496279377Simp ti,mbox-num-users = <4>; 497279377Simp ti,mbox-num-fifos = <12>; 498279377Simp status = "disabled"; 499279377Simp }; 500279377Simp 501279377Simp mailbox5: mailbox@48840000 { 502279377Simp compatible = "ti,omap4-mailbox"; 503279377Simp reg = <0x48840000 0x200>; 504279377Simp interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 505279377Simp <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 506279377Simp <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 507279377Simp <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 508279377Simp ti,hwmods = "mailbox5"; 509279377Simp #mbox-cells = <1>; 510279377Simp ti,mbox-num-users = <4>; 511279377Simp ti,mbox-num-fifos = <12>; 512279377Simp status = "disabled"; 513279377Simp }; 514279377Simp 515279377Simp mailbox6: mailbox@48842000 { 516279377Simp compatible = "ti,omap4-mailbox"; 517279377Simp reg = <0x48842000 0x200>; 518279377Simp interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 519279377Simp <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 520279377Simp <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 521279377Simp <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 522279377Simp ti,hwmods = "mailbox6"; 523279377Simp #mbox-cells = <1>; 524279377Simp ti,mbox-num-users = <4>; 525279377Simp ti,mbox-num-fifos = <12>; 526279377Simp status = "disabled"; 527279377Simp }; 528279377Simp 529279377Simp mailbox7: mailbox@48844000 { 530279377Simp compatible = "ti,omap4-mailbox"; 531279377Simp reg = <0x48844000 0x200>; 532279377Simp interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 533279377Simp <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 534279377Simp <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 535279377Simp <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 536279377Simp ti,hwmods = "mailbox7"; 537279377Simp #mbox-cells = <1>; 538279377Simp ti,mbox-num-users = <4>; 539279377Simp ti,mbox-num-fifos = <12>; 540279377Simp status = "disabled"; 541279377Simp }; 542279377Simp 543279377Simp mailbox8: mailbox@48846000 { 544279377Simp compatible = "ti,omap4-mailbox"; 545279377Simp reg = <0x48846000 0x200>; 546279377Simp interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 547279377Simp <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 548279377Simp <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 549279377Simp <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 550279377Simp ti,hwmods = "mailbox8"; 551279377Simp #mbox-cells = <1>; 552279377Simp ti,mbox-num-users = <4>; 553279377Simp ti,mbox-num-fifos = <12>; 554279377Simp status = "disabled"; 555279377Simp }; 556279377Simp 557279377Simp mailbox9: mailbox@4885e000 { 558279377Simp compatible = "ti,omap4-mailbox"; 559279377Simp reg = <0x4885e000 0x200>; 560279377Simp interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 561279377Simp <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 562279377Simp <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 563279377Simp <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 564279377Simp ti,hwmods = "mailbox9"; 565279377Simp #mbox-cells = <1>; 566279377Simp ti,mbox-num-users = <4>; 567279377Simp ti,mbox-num-fifos = <12>; 568279377Simp status = "disabled"; 569279377Simp }; 570279377Simp 571279377Simp mailbox10: mailbox@48860000 { 572279377Simp compatible = "ti,omap4-mailbox"; 573279377Simp reg = <0x48860000 0x200>; 574279377Simp interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 575279377Simp <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 576279377Simp <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 577279377Simp <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 578279377Simp ti,hwmods = "mailbox10"; 579279377Simp #mbox-cells = <1>; 580279377Simp ti,mbox-num-users = <4>; 581279377Simp ti,mbox-num-fifos = <12>; 582279377Simp status = "disabled"; 583279377Simp }; 584279377Simp 585279377Simp mailbox11: mailbox@48862000 { 586279377Simp compatible = "ti,omap4-mailbox"; 587279377Simp reg = <0x48862000 0x200>; 588279377Simp interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 589279377Simp <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 590279377Simp <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 591279377Simp <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 592279377Simp ti,hwmods = "mailbox11"; 593279377Simp #mbox-cells = <1>; 594279377Simp ti,mbox-num-users = <4>; 595279377Simp ti,mbox-num-fifos = <12>; 596279377Simp status = "disabled"; 597279377Simp }; 598279377Simp 599279377Simp mailbox12: mailbox@48864000 { 600279377Simp compatible = "ti,omap4-mailbox"; 601279377Simp reg = <0x48864000 0x200>; 602279377Simp interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 603279377Simp <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 604279377Simp <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 605279377Simp <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 606279377Simp ti,hwmods = "mailbox12"; 607279377Simp #mbox-cells = <1>; 608279377Simp ti,mbox-num-users = <4>; 609279377Simp ti,mbox-num-fifos = <12>; 610279377Simp status = "disabled"; 611279377Simp }; 612279377Simp 613279377Simp mailbox13: mailbox@48802000 { 614279377Simp compatible = "ti,omap4-mailbox"; 615279377Simp reg = <0x48802000 0x200>; 616279377Simp interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 617279377Simp <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 618279377Simp <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 619279377Simp <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; 620279377Simp ti,hwmods = "mailbox13"; 621279377Simp #mbox-cells = <1>; 622279377Simp ti,mbox-num-users = <4>; 623279377Simp ti,mbox-num-fifos = <12>; 624279377Simp status = "disabled"; 625279377Simp }; 626279377Simp 627279377Simp timer1: timer@4ae18000 { 628279377Simp compatible = "ti,omap5430-timer"; 629279377Simp reg = <0x4ae18000 0x80>; 630279377Simp interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 631279377Simp ti,hwmods = "timer1"; 632279377Simp ti,timer-alwon; 633279377Simp }; 634279377Simp 635279377Simp timer2: timer@48032000 { 636279377Simp compatible = "ti,omap5430-timer"; 637279377Simp reg = <0x48032000 0x80>; 638279377Simp interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 639279377Simp ti,hwmods = "timer2"; 640279377Simp }; 641279377Simp 642279377Simp timer3: timer@48034000 { 643279377Simp compatible = "ti,omap5430-timer"; 644279377Simp reg = <0x48034000 0x80>; 645279377Simp interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 646279377Simp ti,hwmods = "timer3"; 647279377Simp }; 648279377Simp 649279377Simp timer4: timer@48036000 { 650279377Simp compatible = "ti,omap5430-timer"; 651279377Simp reg = <0x48036000 0x80>; 652279377Simp interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 653279377Simp ti,hwmods = "timer4"; 654279377Simp }; 655279377Simp 656279377Simp timer5: timer@48820000 { 657279377Simp compatible = "ti,omap5430-timer"; 658279377Simp reg = <0x48820000 0x80>; 659279377Simp interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 660279377Simp ti,hwmods = "timer5"; 661279377Simp ti,timer-dsp; 662279377Simp }; 663279377Simp 664279377Simp timer6: timer@48822000 { 665279377Simp compatible = "ti,omap5430-timer"; 666279377Simp reg = <0x48822000 0x80>; 667279377Simp interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 668279377Simp ti,hwmods = "timer6"; 669279377Simp ti,timer-dsp; 670279377Simp ti,timer-pwm; 671279377Simp }; 672279377Simp 673279377Simp timer7: timer@48824000 { 674279377Simp compatible = "ti,omap5430-timer"; 675279377Simp reg = <0x48824000 0x80>; 676279377Simp interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 677279377Simp ti,hwmods = "timer7"; 678279377Simp ti,timer-dsp; 679279377Simp }; 680279377Simp 681279377Simp timer8: timer@48826000 { 682279377Simp compatible = "ti,omap5430-timer"; 683279377Simp reg = <0x48826000 0x80>; 684279377Simp interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 685279377Simp ti,hwmods = "timer8"; 686279377Simp ti,timer-dsp; 687279377Simp ti,timer-pwm; 688279377Simp }; 689279377Simp 690279377Simp timer9: timer@4803e000 { 691279377Simp compatible = "ti,omap5430-timer"; 692279377Simp reg = <0x4803e000 0x80>; 693279377Simp interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 694279377Simp ti,hwmods = "timer9"; 695279377Simp }; 696279377Simp 697279377Simp timer10: timer@48086000 { 698279377Simp compatible = "ti,omap5430-timer"; 699279377Simp reg = <0x48086000 0x80>; 700279377Simp interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 701279377Simp ti,hwmods = "timer10"; 702279377Simp }; 703279377Simp 704279377Simp timer11: timer@48088000 { 705279377Simp compatible = "ti,omap5430-timer"; 706279377Simp reg = <0x48088000 0x80>; 707279377Simp interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 708279377Simp ti,hwmods = "timer11"; 709279377Simp ti,timer-pwm; 710279377Simp }; 711279377Simp 712279377Simp timer13: timer@48828000 { 713279377Simp compatible = "ti,omap5430-timer"; 714279377Simp reg = <0x48828000 0x80>; 715279377Simp interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 716279377Simp ti,hwmods = "timer13"; 717279377Simp status = "disabled"; 718279377Simp }; 719279377Simp 720279377Simp timer14: timer@4882a000 { 721279377Simp compatible = "ti,omap5430-timer"; 722279377Simp reg = <0x4882a000 0x80>; 723279377Simp interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 724279377Simp ti,hwmods = "timer14"; 725279377Simp status = "disabled"; 726279377Simp }; 727279377Simp 728279377Simp timer15: timer@4882c000 { 729279377Simp compatible = "ti,omap5430-timer"; 730279377Simp reg = <0x4882c000 0x80>; 731279377Simp interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 732279377Simp ti,hwmods = "timer15"; 733279377Simp status = "disabled"; 734279377Simp }; 735279377Simp 736279377Simp timer16: timer@4882e000 { 737279377Simp compatible = "ti,omap5430-timer"; 738279377Simp reg = <0x4882e000 0x80>; 739279377Simp interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 740279377Simp ti,hwmods = "timer16"; 741279377Simp status = "disabled"; 742279377Simp }; 743279377Simp 744279377Simp wdt2: wdt@4ae14000 { 745279377Simp compatible = "ti,omap3-wdt"; 746279377Simp reg = <0x4ae14000 0x80>; 747279377Simp interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 748279377Simp ti,hwmods = "wd_timer2"; 749279377Simp }; 750279377Simp 751279377Simp hwspinlock: spinlock@4a0f6000 { 752279377Simp compatible = "ti,omap4-hwspinlock"; 753279377Simp reg = <0x4a0f6000 0x1000>; 754279377Simp ti,hwmods = "spinlock"; 755279377Simp #hwlock-cells = <1>; 756279377Simp }; 757279377Simp 758279377Simp dmm@4e000000 { 759279377Simp compatible = "ti,omap5-dmm"; 760279377Simp reg = <0x4e000000 0x800>; 761279377Simp interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 762279377Simp ti,hwmods = "dmm"; 763279377Simp }; 764279377Simp 765279377Simp i2c1: i2c@48070000 { 766279377Simp compatible = "ti,omap4-i2c"; 767279377Simp reg = <0x48070000 0x100>; 768279377Simp interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 769279377Simp #address-cells = <1>; 770279377Simp #size-cells = <0>; 771279377Simp ti,hwmods = "i2c1"; 772279377Simp status = "disabled"; 773279377Simp }; 774279377Simp 775279377Simp i2c2: i2c@48072000 { 776279377Simp compatible = "ti,omap4-i2c"; 777279377Simp reg = <0x48072000 0x100>; 778279377Simp interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 779279377Simp #address-cells = <1>; 780279377Simp #size-cells = <0>; 781279377Simp ti,hwmods = "i2c2"; 782279377Simp status = "disabled"; 783279377Simp }; 784279377Simp 785279377Simp i2c3: i2c@48060000 { 786279377Simp compatible = "ti,omap4-i2c"; 787279377Simp reg = <0x48060000 0x100>; 788279377Simp interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 789279377Simp #address-cells = <1>; 790279377Simp #size-cells = <0>; 791279377Simp ti,hwmods = "i2c3"; 792279377Simp status = "disabled"; 793279377Simp }; 794279377Simp 795279377Simp i2c4: i2c@4807a000 { 796279377Simp compatible = "ti,omap4-i2c"; 797279377Simp reg = <0x4807a000 0x100>; 798279377Simp interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 799279377Simp #address-cells = <1>; 800279377Simp #size-cells = <0>; 801279377Simp ti,hwmods = "i2c4"; 802279377Simp status = "disabled"; 803279377Simp }; 804279377Simp 805279377Simp i2c5: i2c@4807c000 { 806279377Simp compatible = "ti,omap4-i2c"; 807279377Simp reg = <0x4807c000 0x100>; 808279377Simp interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 809279377Simp #address-cells = <1>; 810279377Simp #size-cells = <0>; 811279377Simp ti,hwmods = "i2c5"; 812279377Simp status = "disabled"; 813279377Simp }; 814279377Simp 815279377Simp mmc1: mmc@4809c000 { 816279377Simp compatible = "ti,omap4-hsmmc"; 817279377Simp reg = <0x4809c000 0x400>; 818279377Simp interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 819279377Simp ti,hwmods = "mmc1"; 820279377Simp ti,dual-volt; 821279377Simp ti,needs-special-reset; 822279377Simp dmas = <&sdma 61>, <&sdma 62>; 823279377Simp dma-names = "tx", "rx"; 824279377Simp status = "disabled"; 825279377Simp pbias-supply = <&pbias_mmc_reg>; 826279377Simp }; 827279377Simp 828279377Simp mmc2: mmc@480b4000 { 829279377Simp compatible = "ti,omap4-hsmmc"; 830279377Simp reg = <0x480b4000 0x400>; 831279377Simp interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 832279377Simp ti,hwmods = "mmc2"; 833279377Simp ti,needs-special-reset; 834279377Simp dmas = <&sdma 47>, <&sdma 48>; 835279377Simp dma-names = "tx", "rx"; 836279377Simp status = "disabled"; 837279377Simp }; 838279377Simp 839279377Simp mmc3: mmc@480ad000 { 840279377Simp compatible = "ti,omap4-hsmmc"; 841279377Simp reg = <0x480ad000 0x400>; 842279377Simp interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 843279377Simp ti,hwmods = "mmc3"; 844279377Simp ti,needs-special-reset; 845279377Simp dmas = <&sdma 77>, <&sdma 78>; 846279377Simp dma-names = "tx", "rx"; 847279377Simp status = "disabled"; 848279377Simp }; 849279377Simp 850279377Simp mmc4: mmc@480d1000 { 851279377Simp compatible = "ti,omap4-hsmmc"; 852279377Simp reg = <0x480d1000 0x400>; 853279377Simp interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 854279377Simp ti,hwmods = "mmc4"; 855279377Simp ti,needs-special-reset; 856279377Simp dmas = <&sdma 57>, <&sdma 58>; 857279377Simp dma-names = "tx", "rx"; 858279377Simp status = "disabled"; 859279377Simp }; 860279377Simp 861279377Simp abb_mpu: regulator-abb-mpu { 862279377Simp compatible = "ti,abb-v3"; 863279377Simp regulator-name = "abb_mpu"; 864279377Simp #address-cells = <0>; 865279377Simp #size-cells = <0>; 866279377Simp clocks = <&sys_clkin1>; 867279377Simp ti,settling-time = <50>; 868279377Simp ti,clock-cycles = <16>; 869279377Simp 870279377Simp reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, 871279377Simp <0x4ae06014 0x4>, <0x4a003b20 0x8>, 872279377Simp <0x4ae0c158 0x4>; 873279377Simp reg-names = "setup-address", "control-address", 874279377Simp "int-address", "efuse-address", 875279377Simp "ldo-address"; 876279377Simp ti,tranxdone-status-mask = <0x80>; 877279377Simp /* LDOVBBMPU_FBB_MUX_CTRL */ 878279377Simp ti,ldovbb-override-mask = <0x400>; 879279377Simp /* LDOVBBMPU_FBB_VSET_OUT */ 880279377Simp ti,ldovbb-vset-mask = <0x1F>; 881279377Simp 882279377Simp /* 883279377Simp * NOTE: only FBB mode used but actual vset will 884279377Simp * determine final biasing 885279377Simp */ 886279377Simp ti,abb_info = < 887279377Simp /*uV ABB efuse rbb_m fbb_m vset_m*/ 888279377Simp 1060000 0 0x0 0 0x02000000 0x01F00000 889279377Simp 1160000 0 0x4 0 0x02000000 0x01F00000 890279377Simp 1210000 0 0x8 0 0x02000000 0x01F00000 891279377Simp >; 892279377Simp }; 893279377Simp 894279377Simp abb_ivahd: regulator-abb-ivahd { 895279377Simp compatible = "ti,abb-v3"; 896279377Simp regulator-name = "abb_ivahd"; 897279377Simp #address-cells = <0>; 898279377Simp #size-cells = <0>; 899279377Simp clocks = <&sys_clkin1>; 900279377Simp ti,settling-time = <50>; 901279377Simp ti,clock-cycles = <16>; 902279377Simp 903279377Simp reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, 904279377Simp <0x4ae06010 0x4>, <0x4a0025cc 0x8>, 905279377Simp <0x4a002470 0x4>; 906279377Simp reg-names = "setup-address", "control-address", 907279377Simp "int-address", "efuse-address", 908279377Simp "ldo-address"; 909279377Simp ti,tranxdone-status-mask = <0x40000000>; 910279377Simp /* LDOVBBIVA_FBB_MUX_CTRL */ 911279377Simp ti,ldovbb-override-mask = <0x400>; 912279377Simp /* LDOVBBIVA_FBB_VSET_OUT */ 913279377Simp ti,ldovbb-vset-mask = <0x1F>; 914279377Simp 915279377Simp /* 916279377Simp * NOTE: only FBB mode used but actual vset will 917279377Simp * determine final biasing 918279377Simp */ 919279377Simp ti,abb_info = < 920279377Simp /*uV ABB efuse rbb_m fbb_m vset_m*/ 921279377Simp 1055000 0 0x0 0 0x02000000 0x01F00000 922279377Simp 1150000 0 0x4 0 0x02000000 0x01F00000 923279377Simp 1250000 0 0x8 0 0x02000000 0x01F00000 924279377Simp >; 925279377Simp }; 926279377Simp 927279377Simp abb_dspeve: regulator-abb-dspeve { 928279377Simp compatible = "ti,abb-v3"; 929279377Simp regulator-name = "abb_dspeve"; 930279377Simp #address-cells = <0>; 931279377Simp #size-cells = <0>; 932279377Simp clocks = <&sys_clkin1>; 933279377Simp ti,settling-time = <50>; 934279377Simp ti,clock-cycles = <16>; 935279377Simp 936279377Simp reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, 937279377Simp <0x4ae06010 0x4>, <0x4a0025e0 0x8>, 938279377Simp <0x4a00246c 0x4>; 939279377Simp reg-names = "setup-address", "control-address", 940279377Simp "int-address", "efuse-address", 941279377Simp "ldo-address"; 942279377Simp ti,tranxdone-status-mask = <0x20000000>; 943279377Simp /* LDOVBBDSPEVE_FBB_MUX_CTRL */ 944279377Simp ti,ldovbb-override-mask = <0x400>; 945279377Simp /* LDOVBBDSPEVE_FBB_VSET_OUT */ 946279377Simp ti,ldovbb-vset-mask = <0x1F>; 947279377Simp 948279377Simp /* 949279377Simp * NOTE: only FBB mode used but actual vset will 950279377Simp * determine final biasing 951279377Simp */ 952279377Simp ti,abb_info = < 953279377Simp /*uV ABB efuse rbb_m fbb_m vset_m*/ 954279377Simp 1055000 0 0x0 0 0x02000000 0x01F00000 955279377Simp 1150000 0 0x4 0 0x02000000 0x01F00000 956279377Simp 1250000 0 0x8 0 0x02000000 0x01F00000 957279377Simp >; 958279377Simp }; 959279377Simp 960279377Simp abb_gpu: regulator-abb-gpu { 961279377Simp compatible = "ti,abb-v3"; 962279377Simp regulator-name = "abb_gpu"; 963279377Simp #address-cells = <0>; 964279377Simp #size-cells = <0>; 965279377Simp clocks = <&sys_clkin1>; 966279377Simp ti,settling-time = <50>; 967279377Simp ti,clock-cycles = <16>; 968279377Simp 969279377Simp reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, 970279377Simp <0x4ae06010 0x4>, <0x4a003b08 0x8>, 971279377Simp <0x4ae0c154 0x4>; 972279377Simp reg-names = "setup-address", "control-address", 973279377Simp "int-address", "efuse-address", 974279377Simp "ldo-address"; 975279377Simp ti,tranxdone-status-mask = <0x10000000>; 976279377Simp /* LDOVBBGPU_FBB_MUX_CTRL */ 977279377Simp ti,ldovbb-override-mask = <0x400>; 978279377Simp /* LDOVBBGPU_FBB_VSET_OUT */ 979279377Simp ti,ldovbb-vset-mask = <0x1F>; 980279377Simp 981279377Simp /* 982279377Simp * NOTE: only FBB mode used but actual vset will 983279377Simp * determine final biasing 984279377Simp */ 985279377Simp ti,abb_info = < 986279377Simp /*uV ABB efuse rbb_m fbb_m vset_m*/ 987279377Simp 1090000 0 0x0 0 0x02000000 0x01F00000 988279377Simp 1210000 0 0x4 0 0x02000000 0x01F00000 989279377Simp 1280000 0 0x8 0 0x02000000 0x01F00000 990279377Simp >; 991279377Simp }; 992279377Simp 993279377Simp mcspi1: spi@48098000 { 994279377Simp compatible = "ti,omap4-mcspi"; 995279377Simp reg = <0x48098000 0x200>; 996279377Simp interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 997279377Simp #address-cells = <1>; 998279377Simp #size-cells = <0>; 999279377Simp ti,hwmods = "mcspi1"; 1000279377Simp ti,spi-num-cs = <4>; 1001279377Simp dmas = <&sdma 35>, 1002279377Simp <&sdma 36>, 1003279377Simp <&sdma 37>, 1004279377Simp <&sdma 38>, 1005279377Simp <&sdma 39>, 1006279377Simp <&sdma 40>, 1007279377Simp <&sdma 41>, 1008279377Simp <&sdma 42>; 1009279377Simp dma-names = "tx0", "rx0", "tx1", "rx1", 1010279377Simp "tx2", "rx2", "tx3", "rx3"; 1011279377Simp status = "disabled"; 1012279377Simp }; 1013279377Simp 1014279377Simp mcspi2: spi@4809a000 { 1015279377Simp compatible = "ti,omap4-mcspi"; 1016279377Simp reg = <0x4809a000 0x200>; 1017279377Simp interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1018279377Simp #address-cells = <1>; 1019279377Simp #size-cells = <0>; 1020279377Simp ti,hwmods = "mcspi2"; 1021279377Simp ti,spi-num-cs = <2>; 1022279377Simp dmas = <&sdma 43>, 1023279377Simp <&sdma 44>, 1024279377Simp <&sdma 45>, 1025279377Simp <&sdma 46>; 1026279377Simp dma-names = "tx0", "rx0", "tx1", "rx1"; 1027279377Simp status = "disabled"; 1028279377Simp }; 1029279377Simp 1030279377Simp mcspi3: spi@480b8000 { 1031279377Simp compatible = "ti,omap4-mcspi"; 1032279377Simp reg = <0x480b8000 0x200>; 1033279377Simp interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1034279377Simp #address-cells = <1>; 1035279377Simp #size-cells = <0>; 1036279377Simp ti,hwmods = "mcspi3"; 1037279377Simp ti,spi-num-cs = <2>; 1038279377Simp dmas = <&sdma 15>, <&sdma 16>; 1039279377Simp dma-names = "tx0", "rx0"; 1040279377Simp status = "disabled"; 1041279377Simp }; 1042279377Simp 1043279377Simp mcspi4: spi@480ba000 { 1044279377Simp compatible = "ti,omap4-mcspi"; 1045279377Simp reg = <0x480ba000 0x200>; 1046279377Simp interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1047279377Simp #address-cells = <1>; 1048279377Simp #size-cells = <0>; 1049279377Simp ti,hwmods = "mcspi4"; 1050279377Simp ti,spi-num-cs = <1>; 1051279377Simp dmas = <&sdma 70>, <&sdma 71>; 1052279377Simp dma-names = "tx0", "rx0"; 1053279377Simp status = "disabled"; 1054279377Simp }; 1055279377Simp 1056279377Simp qspi: qspi@4b300000 { 1057279377Simp compatible = "ti,dra7xxx-qspi"; 1058279377Simp reg = <0x4b300000 0x100>; 1059279377Simp reg-names = "qspi_base"; 1060279377Simp #address-cells = <1>; 1061279377Simp #size-cells = <0>; 1062279377Simp ti,hwmods = "qspi"; 1063279377Simp clocks = <&qspi_gfclk_div>; 1064279377Simp clock-names = "fck"; 1065279377Simp num-cs = <4>; 1066279377Simp interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1067279377Simp status = "disabled"; 1068279377Simp }; 1069279377Simp 1070279377Simp omap_control_sata: control-phy@4a002374 { 1071279377Simp compatible = "ti,control-phy-pipe3"; 1072279377Simp reg = <0x4a002374 0x4>; 1073279377Simp reg-names = "power"; 1074279377Simp clocks = <&sys_clkin1>; 1075279377Simp clock-names = "sysclk"; 1076279377Simp }; 1077279377Simp 1078279377Simp /* OCP2SCP3 */ 1079279377Simp ocp2scp@4a090000 { 1080279377Simp compatible = "ti,omap-ocp2scp"; 1081279377Simp #address-cells = <1>; 1082279377Simp #size-cells = <1>; 1083279377Simp ranges; 1084279377Simp reg = <0x4a090000 0x20>; 1085279377Simp ti,hwmods = "ocp2scp3"; 1086279377Simp sata_phy: phy@4A096000 { 1087279377Simp compatible = "ti,phy-pipe3-sata"; 1088279377Simp reg = <0x4A096000 0x80>, /* phy_rx */ 1089279377Simp <0x4A096400 0x64>, /* phy_tx */ 1090279377Simp <0x4A096800 0x40>; /* pll_ctrl */ 1091279377Simp reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1092279377Simp ctrl-module = <&omap_control_sata>; 1093279377Simp clocks = <&sys_clkin1>; 1094279377Simp clock-names = "sysclk"; 1095279377Simp #phy-cells = <0>; 1096279377Simp }; 1097279377Simp 1098279377Simp pcie1_phy: pciephy@4a094000 { 1099279377Simp compatible = "ti,phy-pipe3-pcie"; 1100279377Simp reg = <0x4a094000 0x80>, /* phy_rx */ 1101279377Simp <0x4a094400 0x64>; /* phy_tx */ 1102279377Simp reg-names = "phy_rx", "phy_tx"; 1103279377Simp ctrl-module = <&omap_control_pcie1phy>; 1104279377Simp clocks = <&dpll_pcie_ref_ck>, 1105279377Simp <&dpll_pcie_ref_m2ldo_ck>, 1106279377Simp <&optfclk_pciephy1_32khz>, 1107279377Simp <&optfclk_pciephy1_clk>, 1108279377Simp <&optfclk_pciephy1_div_clk>, 1109279377Simp <&optfclk_pciephy_div>; 1110279377Simp clock-names = "dpll_ref", "dpll_ref_m2", 1111279377Simp "wkupclk", "refclk", 1112279377Simp "div-clk", "phy-div"; 1113279377Simp #phy-cells = <0>; 1114279377Simp ti,hwmods = "pcie1-phy"; 1115279377Simp }; 1116279377Simp 1117279377Simp pcie2_phy: pciephy@4a095000 { 1118279377Simp compatible = "ti,phy-pipe3-pcie"; 1119279377Simp reg = <0x4a095000 0x80>, /* phy_rx */ 1120279377Simp <0x4a095400 0x64>; /* phy_tx */ 1121279377Simp reg-names = "phy_rx", "phy_tx"; 1122279377Simp ctrl-module = <&omap_control_pcie2phy>; 1123279377Simp clocks = <&dpll_pcie_ref_ck>, 1124279377Simp <&dpll_pcie_ref_m2ldo_ck>, 1125279377Simp <&optfclk_pciephy2_32khz>, 1126279377Simp <&optfclk_pciephy2_clk>, 1127279377Simp <&optfclk_pciephy2_div_clk>, 1128279377Simp <&optfclk_pciephy_div>; 1129279377Simp clock-names = "dpll_ref", "dpll_ref_m2", 1130279377Simp "wkupclk", "refclk", 1131279377Simp "div-clk", "phy-div"; 1132279377Simp #phy-cells = <0>; 1133279377Simp ti,hwmods = "pcie2-phy"; 1134279377Simp status = "disabled"; 1135279377Simp }; 1136279377Simp }; 1137279377Simp 1138279377Simp sata: sata@4a141100 { 1139279377Simp compatible = "snps,dwc-ahci"; 1140279377Simp reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; 1141279377Simp interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1142279377Simp phys = <&sata_phy>; 1143279377Simp phy-names = "sata-phy"; 1144279377Simp clocks = <&sata_ref_clk>; 1145279377Simp ti,hwmods = "sata"; 1146279377Simp }; 1147279377Simp 1148279377Simp omap_control_pcie1phy: control-phy@0x4a003c40 { 1149279377Simp compatible = "ti,control-phy-pcie"; 1150279377Simp reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; 1151279377Simp reg-names = "power", "control_sma", "pcie_pcs"; 1152279377Simp clocks = <&sys_clkin1>; 1153279377Simp clock-names = "sysclk"; 1154279377Simp }; 1155279377Simp 1156279377Simp omap_control_pcie2phy: control-pcie@0x4a003c44 { 1157279377Simp compatible = "ti,control-phy-pcie"; 1158279377Simp reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; 1159279377Simp reg-names = "power", "control_sma", "pcie_pcs"; 1160279377Simp clocks = <&sys_clkin1>; 1161279377Simp clock-names = "sysclk"; 1162279377Simp status = "disabled"; 1163279377Simp }; 1164279377Simp 1165279377Simp rtc@48838000 { 1166279377Simp compatible = "ti,am3352-rtc"; 1167279377Simp reg = <0x48838000 0x100>; 1168279377Simp interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1169279377Simp <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 1170279377Simp ti,hwmods = "rtcss"; 1171279377Simp clocks = <&sys_32k_ck>; 1172279377Simp }; 1173279377Simp 1174279377Simp omap_control_usb2phy1: control-phy@4a002300 { 1175279377Simp compatible = "ti,control-phy-usb2"; 1176279377Simp reg = <0x4a002300 0x4>; 1177279377Simp reg-names = "power"; 1178279377Simp }; 1179279377Simp 1180279377Simp omap_control_usb3phy1: control-phy@4a002370 { 1181279377Simp compatible = "ti,control-phy-pipe3"; 1182279377Simp reg = <0x4a002370 0x4>; 1183279377Simp reg-names = "power"; 1184279377Simp }; 1185279377Simp 1186279377Simp omap_control_usb2phy2: control-phy@0x4a002e74 { 1187279377Simp compatible = "ti,control-phy-usb2-dra7"; 1188279377Simp reg = <0x4a002e74 0x4>; 1189279377Simp reg-names = "power"; 1190279377Simp }; 1191279377Simp 1192279377Simp /* OCP2SCP1 */ 1193279377Simp ocp2scp@4a080000 { 1194279377Simp compatible = "ti,omap-ocp2scp"; 1195279377Simp #address-cells = <1>; 1196279377Simp #size-cells = <1>; 1197279377Simp ranges; 1198279377Simp reg = <0x4a080000 0x20>; 1199279377Simp ti,hwmods = "ocp2scp1"; 1200279377Simp 1201279377Simp usb2_phy1: phy@4a084000 { 1202279377Simp compatible = "ti,omap-usb2"; 1203279377Simp reg = <0x4a084000 0x400>; 1204279377Simp ctrl-module = <&omap_control_usb2phy1>; 1205279377Simp clocks = <&usb_phy1_always_on_clk32k>, 1206279377Simp <&usb_otg_ss1_refclk960m>; 1207279377Simp clock-names = "wkupclk", 1208279377Simp "refclk"; 1209279377Simp #phy-cells = <0>; 1210279377Simp }; 1211279377Simp 1212279377Simp usb2_phy2: phy@4a085000 { 1213279377Simp compatible = "ti,omap-usb2"; 1214279377Simp reg = <0x4a085000 0x400>; 1215279377Simp ctrl-module = <&omap_control_usb2phy2>; 1216279377Simp clocks = <&usb_phy2_always_on_clk32k>, 1217279377Simp <&usb_otg_ss2_refclk960m>; 1218279377Simp clock-names = "wkupclk", 1219279377Simp "refclk"; 1220279377Simp #phy-cells = <0>; 1221279377Simp }; 1222279377Simp 1223279377Simp usb3_phy1: phy@4a084400 { 1224279377Simp compatible = "ti,omap-usb3"; 1225279377Simp reg = <0x4a084400 0x80>, 1226279377Simp <0x4a084800 0x64>, 1227279377Simp <0x4a084c00 0x40>; 1228279377Simp reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1229279377Simp ctrl-module = <&omap_control_usb3phy1>; 1230279377Simp clocks = <&usb_phy3_always_on_clk32k>, 1231279377Simp <&sys_clkin1>, 1232279377Simp <&usb_otg_ss1_refclk960m>; 1233279377Simp clock-names = "wkupclk", 1234279377Simp "sysclk", 1235279377Simp "refclk"; 1236279377Simp #phy-cells = <0>; 1237279377Simp }; 1238279377Simp }; 1239279377Simp 1240279377Simp omap_dwc3_1: omap_dwc3_1@48880000 { 1241279377Simp compatible = "ti,dwc3"; 1242279377Simp ti,hwmods = "usb_otg_ss1"; 1243279377Simp reg = <0x48880000 0x10000>; 1244279377Simp interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1245279377Simp #address-cells = <1>; 1246279377Simp #size-cells = <1>; 1247279377Simp utmi-mode = <2>; 1248279377Simp ranges; 1249279377Simp usb1: usb@48890000 { 1250279377Simp compatible = "snps,dwc3"; 1251279377Simp reg = <0x48890000 0x17000>; 1252279377Simp interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1253279377Simp phys = <&usb2_phy1>, <&usb3_phy1>; 1254279377Simp phy-names = "usb2-phy", "usb3-phy"; 1255279377Simp tx-fifo-resize; 1256279377Simp maximum-speed = "super-speed"; 1257279377Simp dr_mode = "otg"; 1258279377Simp snps,dis_u3_susphy_quirk; 1259279377Simp snps,dis_u2_susphy_quirk; 1260279377Simp }; 1261279377Simp }; 1262279377Simp 1263279377Simp omap_dwc3_2: omap_dwc3_2@488c0000 { 1264279377Simp compatible = "ti,dwc3"; 1265279377Simp ti,hwmods = "usb_otg_ss2"; 1266279377Simp reg = <0x488c0000 0x10000>; 1267279377Simp interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1268279377Simp #address-cells = <1>; 1269279377Simp #size-cells = <1>; 1270279377Simp utmi-mode = <2>; 1271279377Simp ranges; 1272279377Simp usb2: usb@488d0000 { 1273279377Simp compatible = "snps,dwc3"; 1274279377Simp reg = <0x488d0000 0x17000>; 1275279377Simp interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1276279377Simp phys = <&usb2_phy2>; 1277279377Simp phy-names = "usb2-phy"; 1278279377Simp tx-fifo-resize; 1279279377Simp maximum-speed = "high-speed"; 1280279377Simp dr_mode = "otg"; 1281279377Simp snps,dis_u3_susphy_quirk; 1282279377Simp snps,dis_u2_susphy_quirk; 1283279377Simp }; 1284279377Simp }; 1285279377Simp 1286279377Simp /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ 1287279377Simp omap_dwc3_3: omap_dwc3_3@48900000 { 1288279377Simp compatible = "ti,dwc3"; 1289279377Simp ti,hwmods = "usb_otg_ss3"; 1290279377Simp reg = <0x48900000 0x10000>; 1291279377Simp interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1292279377Simp #address-cells = <1>; 1293279377Simp #size-cells = <1>; 1294279377Simp utmi-mode = <2>; 1295279377Simp ranges; 1296279377Simp status = "disabled"; 1297279377Simp usb3: usb@48910000 { 1298279377Simp compatible = "snps,dwc3"; 1299279377Simp reg = <0x48910000 0x17000>; 1300279377Simp interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1301279377Simp tx-fifo-resize; 1302279377Simp maximum-speed = "high-speed"; 1303279377Simp dr_mode = "otg"; 1304279377Simp snps,dis_u3_susphy_quirk; 1305279377Simp snps,dis_u2_susphy_quirk; 1306279377Simp }; 1307279377Simp }; 1308279377Simp 1309279377Simp elm: elm@48078000 { 1310279377Simp compatible = "ti,am3352-elm"; 1311279377Simp reg = <0x48078000 0xfc0>; /* device IO registers */ 1312279377Simp interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1313279377Simp ti,hwmods = "elm"; 1314279377Simp status = "disabled"; 1315279377Simp }; 1316279377Simp 1317279377Simp gpmc: gpmc@50000000 { 1318279377Simp compatible = "ti,am3352-gpmc"; 1319279377Simp ti,hwmods = "gpmc"; 1320279377Simp reg = <0x50000000 0x37c>; /* device IO registers */ 1321279377Simp interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1322279377Simp gpmc,num-cs = <8>; 1323279377Simp gpmc,num-waitpins = <2>; 1324279377Simp #address-cells = <2>; 1325279377Simp #size-cells = <1>; 1326279377Simp status = "disabled"; 1327279377Simp }; 1328279377Simp 1329279377Simp atl: atl@4843c000 { 1330279377Simp compatible = "ti,dra7-atl"; 1331279377Simp reg = <0x4843c000 0x3ff>; 1332279377Simp ti,hwmods = "atl"; 1333279377Simp ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, 1334279377Simp <&atl_clkin2_ck>, <&atl_clkin3_ck>; 1335279377Simp clocks = <&atl_gfclk_mux>; 1336279377Simp clock-names = "fck"; 1337279377Simp status = "disabled"; 1338279377Simp }; 1339279377Simp 1340279377Simp crossbar_mpu: crossbar@4a020000 { 1341279377Simp compatible = "ti,irq-crossbar"; 1342279377Simp reg = <0x4a002a48 0x130>; 1343279377Simp ti,max-irqs = <160>; 1344279377Simp ti,max-crossbar-sources = <MAX_SOURCES>; 1345279377Simp ti,reg-size = <2>; 1346279377Simp ti,irqs-reserved = <0 1 2 3 5 6 131 132>; 1347279377Simp ti,irqs-skip = <10 133 139 140>; 1348279377Simp ti,irqs-safe-map = <0>; 1349279377Simp }; 1350279377Simp 1351279377Simp mac: ethernet@4a100000 { 1352279377Simp compatible = "ti,cpsw"; 1353279377Simp ti,hwmods = "gmac"; 1354279377Simp clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; 1355279377Simp clock-names = "fck", "cpts"; 1356279377Simp cpdma_channels = <8>; 1357279377Simp ale_entries = <1024>; 1358279377Simp bd_ram_size = <0x2000>; 1359279377Simp no_bd_ram = <0>; 1360279377Simp rx_descs = <64>; 1361279377Simp mac_control = <0x20>; 1362279377Simp slaves = <2>; 1363279377Simp active_slave = <0>; 1364279377Simp cpts_clock_mult = <0x80000000>; 1365279377Simp cpts_clock_shift = <29>; 1366279377Simp reg = <0x48484000 0x1000 1367279377Simp 0x48485200 0x2E00>; 1368279377Simp #address-cells = <1>; 1369279377Simp #size-cells = <1>; 1370279377Simp /* 1371279377Simp * rx_thresh_pend 1372279377Simp * rx_pend 1373279377Simp * tx_pend 1374279377Simp * misc_pend 1375279377Simp */ 1376279377Simp interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1377279377Simp <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1378279377Simp <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1379279377Simp <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 1380279377Simp ranges; 1381279377Simp status = "disabled"; 1382279377Simp 1383279377Simp davinci_mdio: mdio@48485000 { 1384279377Simp compatible = "ti,davinci_mdio"; 1385279377Simp #address-cells = <1>; 1386279377Simp #size-cells = <0>; 1387279377Simp ti,hwmods = "davinci_mdio"; 1388279377Simp bus_freq = <1000000>; 1389279377Simp reg = <0x48485000 0x100>; 1390279377Simp }; 1391279377Simp 1392279377Simp cpsw_emac0: slave@48480200 { 1393279377Simp /* Filled in by U-Boot */ 1394279377Simp mac-address = [ 00 00 00 00 00 00 ]; 1395279377Simp }; 1396279377Simp 1397279377Simp cpsw_emac1: slave@48480300 { 1398279377Simp /* Filled in by U-Boot */ 1399279377Simp mac-address = [ 00 00 00 00 00 00 ]; 1400279377Simp }; 1401279377Simp 1402279377Simp phy_sel: cpsw-phy-sel@4a002554 { 1403279377Simp compatible = "ti,dra7xx-cpsw-phy-sel"; 1404279377Simp reg= <0x4a002554 0x4>; 1405279377Simp reg-names = "gmii-sel"; 1406279377Simp }; 1407279377Simp }; 1408279377Simp 1409279377Simp dcan1: can@481cc000 { 1410279377Simp compatible = "ti,dra7-d_can"; 1411279377Simp ti,hwmods = "dcan1"; 1412279377Simp reg = <0x4ae3c000 0x2000>; 1413279377Simp syscon-raminit = <&dra7_ctrl_core 0x558 0>; 1414279377Simp interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1415279377Simp clocks = <&dcan1_sys_clk_mux>; 1416279377Simp status = "disabled"; 1417279377Simp }; 1418279377Simp 1419279377Simp dcan2: can@481d0000 { 1420279377Simp compatible = "ti,dra7-d_can"; 1421279377Simp ti,hwmods = "dcan2"; 1422279377Simp reg = <0x48480000 0x2000>; 1423279377Simp syscon-raminit = <&dra7_ctrl_core 0x558 1>; 1424279377Simp interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1425279377Simp clocks = <&sys_clkin1>; 1426279377Simp status = "disabled"; 1427279377Simp }; 1428279377Simp }; 1429279377Simp}; 1430279377Simp 1431279377Simp/include/ "dra7xx-clocks.dtsi" 1432