1279377Simp/* 2279377Simp * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3279377Simp * 4279377Simp * This program is free software; you can redistribute it and/or modify 5279377Simp * it under the terms of the GNU General Public License version 2 as 6279377Simp * published by the Free Software Foundation. 7279377Simp * Based on "omap4.dtsi" 8279377Simp */ 9279377Simp 10279377Simp#include <dt-bindings/interrupt-controller/arm-gic.h> 11279377Simp#include <dt-bindings/pinctrl/dra.h> 12279377Simp 13279377Simp#include "skeleton.dtsi" 14279377Simp 15279377Simp#define MAX_SOURCES 400 16279377Simp 17279377Simp/ { 18279377Simp #address-cells = <1>; 19279377Simp #size-cells = <1>; 20279377Simp 21279377Simp compatible = "ti,dra7xx"; 22295436Sandrew interrupt-parent = <&crossbar_mpu>; 23279377Simp 24279377Simp aliases { 25279377Simp i2c0 = &i2c1; 26279377Simp i2c1 = &i2c2; 27279377Simp i2c2 = &i2c3; 28279377Simp i2c3 = &i2c4; 29279377Simp i2c4 = &i2c5; 30279377Simp serial0 = &uart1; 31279377Simp serial1 = &uart2; 32279377Simp serial2 = &uart3; 33279377Simp serial3 = &uart4; 34279377Simp serial4 = &uart5; 35279377Simp serial5 = &uart6; 36279377Simp serial6 = &uart7; 37279377Simp serial7 = &uart8; 38279377Simp serial8 = &uart9; 39279377Simp serial9 = &uart10; 40279377Simp ethernet0 = &cpsw_emac0; 41279377Simp ethernet1 = &cpsw_emac1; 42279377Simp d_can0 = &dcan1; 43279377Simp d_can1 = &dcan2; 44295436Sandrew spi0 = &qspi; 45279377Simp }; 46279377Simp 47279377Simp timer { 48279377Simp compatible = "arm,armv7-timer"; 49279377Simp interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 50279377Simp <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 51279377Simp <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 52279377Simp <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 53295436Sandrew interrupt-parent = <&gic>; 54279377Simp }; 55279377Simp 56279377Simp gic: interrupt-controller@48211000 { 57279377Simp compatible = "arm,cortex-a15-gic"; 58279377Simp interrupt-controller; 59279377Simp #interrupt-cells = <3>; 60279377Simp reg = <0x48211000 0x1000>, 61279377Simp <0x48212000 0x1000>, 62279377Simp <0x48214000 0x2000>, 63279377Simp <0x48216000 0x2000>; 64279377Simp interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 65295436Sandrew interrupt-parent = <&gic>; 66279377Simp }; 67279377Simp 68295436Sandrew wakeupgen: interrupt-controller@48281000 { 69295436Sandrew compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 70295436Sandrew interrupt-controller; 71295436Sandrew #interrupt-cells = <3>; 72295436Sandrew reg = <0x48281000 0x1000>; 73295436Sandrew interrupt-parent = <&gic>; 74295436Sandrew }; 75295436Sandrew 76279377Simp /* 77279377Simp * The soc node represents the soc top level view. It is used for IPs 78279377Simp * that are not memory mapped in the MPU view or for the MPU itself. 79279377Simp */ 80279377Simp soc { 81279377Simp compatible = "ti,omap-infra"; 82279377Simp mpu { 83279377Simp compatible = "ti,omap5-mpu"; 84279377Simp ti,hwmods = "mpu"; 85279377Simp }; 86279377Simp }; 87279377Simp 88279377Simp /* 89279377Simp * XXX: Use a flat representation of the SOC interconnect. 90279377Simp * The real OMAP interconnect network is quite complex. 91279377Simp * Since it will not bring real advantage to represent that in DT for 92279377Simp * the moment, just use a fake OCP bus entry to represent the whole bus 93279377Simp * hierarchy. 94279377Simp */ 95279377Simp ocp { 96279377Simp compatible = "ti,dra7-l3-noc", "simple-bus"; 97279377Simp #address-cells = <1>; 98279377Simp #size-cells = <1>; 99279377Simp ranges; 100279377Simp ti,hwmods = "l3_main_1", "l3_main_2"; 101279377Simp reg = <0x44000000 0x1000000>, 102279377Simp <0x45000000 0x1000>; 103295436Sandrew interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 104295436Sandrew <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 105279377Simp 106295436Sandrew l4_cfg: l4@4a000000 { 107295436Sandrew compatible = "ti,dra7-l4-cfg", "simple-bus"; 108295436Sandrew #address-cells = <1>; 109295436Sandrew #size-cells = <1>; 110295436Sandrew ranges = <0 0x4a000000 0x22c000>; 111279377Simp 112295436Sandrew scm: scm@2000 { 113295436Sandrew compatible = "ti,dra7-scm-core", "simple-bus"; 114295436Sandrew reg = <0x2000 0x2000>; 115279377Simp #address-cells = <1>; 116295436Sandrew #size-cells = <1>; 117295436Sandrew ranges = <0 0x2000 0x2000>; 118295436Sandrew 119295436Sandrew scm_conf: scm_conf@0 { 120295436Sandrew compatible = "syscon", "simple-bus"; 121295436Sandrew reg = <0x0 0x1400>; 122295436Sandrew #address-cells = <1>; 123295436Sandrew #size-cells = <1>; 124295436Sandrew ranges = <0 0x0 0x1400>; 125295436Sandrew 126295436Sandrew pbias_regulator: pbias_regulator { 127295436Sandrew compatible = "ti,pbias-dra7", "ti,pbias-omap"; 128295436Sandrew reg = <0xe00 0x4>; 129295436Sandrew syscon = <&scm_conf>; 130295436Sandrew pbias_mmc_reg: pbias_mmc_omap5 { 131295436Sandrew regulator-name = "pbias_mmc_omap5"; 132295436Sandrew regulator-min-microvolt = <1800000>; 133295436Sandrew regulator-max-microvolt = <3000000>; 134295436Sandrew }; 135295436Sandrew }; 136295436Sandrew 137295436Sandrew scm_conf_clocks: clocks { 138295436Sandrew #address-cells = <1>; 139295436Sandrew #size-cells = <0>; 140295436Sandrew }; 141295436Sandrew }; 142295436Sandrew 143295436Sandrew dra7_pmx_core: pinmux@1400 { 144295436Sandrew compatible = "ti,dra7-padconf", 145295436Sandrew "pinctrl-single"; 146295436Sandrew reg = <0x1400 0x0468>; 147295436Sandrew #address-cells = <1>; 148295436Sandrew #size-cells = <0>; 149295436Sandrew #interrupt-cells = <1>; 150295436Sandrew interrupt-controller; 151295436Sandrew pinctrl-single,register-width = <32>; 152295436Sandrew pinctrl-single,function-mask = <0x3fffffff>; 153295436Sandrew }; 154295436Sandrew 155295436Sandrew scm_conf1: scm_conf@1c04 { 156295436Sandrew compatible = "syscon"; 157295436Sandrew reg = <0x1c04 0x0020>; 158295436Sandrew }; 159279377Simp }; 160279377Simp 161295436Sandrew cm_core_aon: cm_core_aon@5000 { 162295436Sandrew compatible = "ti,dra7-cm-core-aon"; 163295436Sandrew reg = <0x5000 0x2000>; 164295436Sandrew 165295436Sandrew cm_core_aon_clocks: clocks { 166295436Sandrew #address-cells = <1>; 167295436Sandrew #size-cells = <0>; 168295436Sandrew }; 169295436Sandrew 170295436Sandrew cm_core_aon_clockdomains: clockdomains { 171295436Sandrew }; 172279377Simp }; 173295436Sandrew 174295436Sandrew cm_core: cm_core@8000 { 175295436Sandrew compatible = "ti,dra7-cm-core"; 176295436Sandrew reg = <0x8000 0x3000>; 177295436Sandrew 178295436Sandrew cm_core_clocks: clocks { 179295436Sandrew #address-cells = <1>; 180295436Sandrew #size-cells = <0>; 181295436Sandrew }; 182295436Sandrew 183295436Sandrew cm_core_clockdomains: clockdomains { 184295436Sandrew }; 185295436Sandrew }; 186279377Simp }; 187279377Simp 188295436Sandrew l4_wkup: l4@4ae00000 { 189295436Sandrew compatible = "ti,dra7-l4-wkup", "simple-bus"; 190295436Sandrew #address-cells = <1>; 191295436Sandrew #size-cells = <1>; 192295436Sandrew ranges = <0 0x4ae00000 0x3f000>; 193295436Sandrew 194295436Sandrew counter32k: counter@4000 { 195295436Sandrew compatible = "ti,omap-counter32k"; 196295436Sandrew reg = <0x4000 0x40>; 197295436Sandrew ti,hwmods = "counter_32k"; 198295436Sandrew }; 199295436Sandrew 200295436Sandrew prm: prm@6000 { 201295436Sandrew compatible = "ti,dra7-prm"; 202295436Sandrew reg = <0x6000 0x3000>; 203295436Sandrew interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 204295436Sandrew 205295436Sandrew prm_clocks: clocks { 206295436Sandrew #address-cells = <1>; 207295436Sandrew #size-cells = <0>; 208295436Sandrew }; 209295436Sandrew 210295436Sandrew prm_clockdomains: clockdomains { 211295436Sandrew }; 212295436Sandrew }; 213295436Sandrew }; 214295436Sandrew 215279377Simp axi@0 { 216279377Simp compatible = "simple-bus"; 217279377Simp #size-cells = <1>; 218279377Simp #address-cells = <1>; 219279377Simp ranges = <0x51000000 0x51000000 0x3000 220279377Simp 0x0 0x20000000 0x10000000>; 221295436Sandrew pcie1: pcie@51000000 { 222279377Simp compatible = "ti,dra7-pcie"; 223279377Simp reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; 224279377Simp reg-names = "rc_dbics", "ti_conf", "config"; 225279377Simp interrupts = <0 232 0x4>, <0 233 0x4>; 226279377Simp #address-cells = <3>; 227279377Simp #size-cells = <2>; 228279377Simp device_type = "pci"; 229279377Simp ranges = <0x81000000 0 0 0x03000 0 0x00010000 230279377Simp 0x82000000 0 0x20013000 0x13000 0 0xffed000>; 231279377Simp #interrupt-cells = <1>; 232279377Simp num-lanes = <1>; 233279377Simp ti,hwmods = "pcie1"; 234279377Simp phys = <&pcie1_phy>; 235279377Simp phy-names = "pcie-phy0"; 236279377Simp interrupt-map-mask = <0 0 0 7>; 237279377Simp interrupt-map = <0 0 0 1 &pcie1_intc 1>, 238279377Simp <0 0 0 2 &pcie1_intc 2>, 239279377Simp <0 0 0 3 &pcie1_intc 3>, 240279377Simp <0 0 0 4 &pcie1_intc 4>; 241279377Simp pcie1_intc: interrupt-controller { 242279377Simp interrupt-controller; 243279377Simp #address-cells = <0>; 244279377Simp #interrupt-cells = <1>; 245279377Simp }; 246279377Simp }; 247279377Simp }; 248279377Simp 249279377Simp axi@1 { 250279377Simp compatible = "simple-bus"; 251279377Simp #size-cells = <1>; 252279377Simp #address-cells = <1>; 253279377Simp ranges = <0x51800000 0x51800000 0x3000 254279377Simp 0x0 0x30000000 0x10000000>; 255279377Simp status = "disabled"; 256279377Simp pcie@51000000 { 257279377Simp compatible = "ti,dra7-pcie"; 258279377Simp reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; 259279377Simp reg-names = "rc_dbics", "ti_conf", "config"; 260279377Simp interrupts = <0 355 0x4>, <0 356 0x4>; 261279377Simp #address-cells = <3>; 262279377Simp #size-cells = <2>; 263279377Simp device_type = "pci"; 264279377Simp ranges = <0x81000000 0 0 0x03000 0 0x00010000 265279377Simp 0x82000000 0 0x30013000 0x13000 0 0xffed000>; 266279377Simp #interrupt-cells = <1>; 267279377Simp num-lanes = <1>; 268279377Simp ti,hwmods = "pcie2"; 269279377Simp phys = <&pcie2_phy>; 270279377Simp phy-names = "pcie-phy0"; 271279377Simp interrupt-map-mask = <0 0 0 7>; 272279377Simp interrupt-map = <0 0 0 1 &pcie2_intc 1>, 273279377Simp <0 0 0 2 &pcie2_intc 2>, 274279377Simp <0 0 0 3 &pcie2_intc 3>, 275279377Simp <0 0 0 4 &pcie2_intc 4>; 276279377Simp pcie2_intc: interrupt-controller { 277279377Simp interrupt-controller; 278279377Simp #address-cells = <0>; 279279377Simp #interrupt-cells = <1>; 280279377Simp }; 281279377Simp }; 282279377Simp }; 283279377Simp 284295436Sandrew bandgap: bandgap@4a0021e0 { 285295436Sandrew reg = <0x4a0021e0 0xc 286295436Sandrew 0x4a00232c 0xc 287295436Sandrew 0x4a002380 0x2c 288295436Sandrew 0x4a0023C0 0x3c 289295436Sandrew 0x4a002564 0x8 290295436Sandrew 0x4a002574 0x50>; 291295436Sandrew compatible = "ti,dra752-bandgap"; 292295436Sandrew interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 293295436Sandrew #thermal-sensor-cells = <1>; 294279377Simp }; 295279377Simp 296295436Sandrew dsp1_system: dsp_system@40d00000 { 297279377Simp compatible = "syscon"; 298295436Sandrew reg = <0x40d00000 0x100>; 299279377Simp }; 300279377Simp 301279377Simp sdma: dma-controller@4a056000 { 302279377Simp compatible = "ti,omap4430-sdma"; 303279377Simp reg = <0x4a056000 0x1000>; 304279377Simp interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 305279377Simp <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 306279377Simp <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 307279377Simp <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 308279377Simp #dma-cells = <1>; 309295436Sandrew dma-channels = <32>; 310295436Sandrew dma-requests = <127>; 311279377Simp }; 312279377Simp 313295436Sandrew sdma_xbar: dma-router@4a002b78 { 314295436Sandrew compatible = "ti,dra7-dma-crossbar"; 315295436Sandrew reg = <0x4a002b78 0xfc>; 316295436Sandrew #dma-cells = <1>; 317295436Sandrew dma-requests = <205>; 318295436Sandrew ti,dma-safe-map = <0>; 319295436Sandrew dma-masters = <&sdma>; 320295436Sandrew }; 321295436Sandrew 322279377Simp gpio1: gpio@4ae10000 { 323279377Simp compatible = "ti,omap4-gpio"; 324279377Simp reg = <0x4ae10000 0x200>; 325279377Simp interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 326279377Simp ti,hwmods = "gpio1"; 327279377Simp gpio-controller; 328279377Simp #gpio-cells = <2>; 329279377Simp interrupt-controller; 330279377Simp #interrupt-cells = <2>; 331279377Simp }; 332279377Simp 333279377Simp gpio2: gpio@48055000 { 334279377Simp compatible = "ti,omap4-gpio"; 335279377Simp reg = <0x48055000 0x200>; 336279377Simp interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 337279377Simp ti,hwmods = "gpio2"; 338279377Simp gpio-controller; 339279377Simp #gpio-cells = <2>; 340279377Simp interrupt-controller; 341279377Simp #interrupt-cells = <2>; 342279377Simp }; 343279377Simp 344279377Simp gpio3: gpio@48057000 { 345279377Simp compatible = "ti,omap4-gpio"; 346279377Simp reg = <0x48057000 0x200>; 347279377Simp interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 348279377Simp ti,hwmods = "gpio3"; 349279377Simp gpio-controller; 350279377Simp #gpio-cells = <2>; 351279377Simp interrupt-controller; 352279377Simp #interrupt-cells = <2>; 353279377Simp }; 354279377Simp 355279377Simp gpio4: gpio@48059000 { 356279377Simp compatible = "ti,omap4-gpio"; 357279377Simp reg = <0x48059000 0x200>; 358279377Simp interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 359279377Simp ti,hwmods = "gpio4"; 360279377Simp gpio-controller; 361279377Simp #gpio-cells = <2>; 362279377Simp interrupt-controller; 363279377Simp #interrupt-cells = <2>; 364279377Simp }; 365279377Simp 366279377Simp gpio5: gpio@4805b000 { 367279377Simp compatible = "ti,omap4-gpio"; 368279377Simp reg = <0x4805b000 0x200>; 369279377Simp interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 370279377Simp ti,hwmods = "gpio5"; 371279377Simp gpio-controller; 372279377Simp #gpio-cells = <2>; 373279377Simp interrupt-controller; 374279377Simp #interrupt-cells = <2>; 375279377Simp }; 376279377Simp 377279377Simp gpio6: gpio@4805d000 { 378279377Simp compatible = "ti,omap4-gpio"; 379279377Simp reg = <0x4805d000 0x200>; 380279377Simp interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 381279377Simp ti,hwmods = "gpio6"; 382279377Simp gpio-controller; 383279377Simp #gpio-cells = <2>; 384279377Simp interrupt-controller; 385279377Simp #interrupt-cells = <2>; 386279377Simp }; 387279377Simp 388279377Simp gpio7: gpio@48051000 { 389279377Simp compatible = "ti,omap4-gpio"; 390279377Simp reg = <0x48051000 0x200>; 391279377Simp interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 392279377Simp ti,hwmods = "gpio7"; 393279377Simp gpio-controller; 394279377Simp #gpio-cells = <2>; 395279377Simp interrupt-controller; 396279377Simp #interrupt-cells = <2>; 397279377Simp }; 398279377Simp 399279377Simp gpio8: gpio@48053000 { 400279377Simp compatible = "ti,omap4-gpio"; 401279377Simp reg = <0x48053000 0x200>; 402279377Simp interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 403279377Simp ti,hwmods = "gpio8"; 404279377Simp gpio-controller; 405279377Simp #gpio-cells = <2>; 406279377Simp interrupt-controller; 407279377Simp #interrupt-cells = <2>; 408279377Simp }; 409279377Simp 410279377Simp uart1: serial@4806a000 { 411295436Sandrew compatible = "ti,dra742-uart", "ti,omap4-uart"; 412279377Simp reg = <0x4806a000 0x100>; 413295436Sandrew interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 414279377Simp ti,hwmods = "uart1"; 415279377Simp clock-frequency = <48000000>; 416279377Simp status = "disabled"; 417295436Sandrew dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; 418279377Simp dma-names = "tx", "rx"; 419279377Simp }; 420279377Simp 421279377Simp uart2: serial@4806c000 { 422295436Sandrew compatible = "ti,dra742-uart", "ti,omap4-uart"; 423279377Simp reg = <0x4806c000 0x100>; 424295436Sandrew interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 425279377Simp ti,hwmods = "uart2"; 426279377Simp clock-frequency = <48000000>; 427279377Simp status = "disabled"; 428295436Sandrew dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; 429279377Simp dma-names = "tx", "rx"; 430279377Simp }; 431279377Simp 432279377Simp uart3: serial@48020000 { 433295436Sandrew compatible = "ti,dra742-uart", "ti,omap4-uart"; 434279377Simp reg = <0x48020000 0x100>; 435295436Sandrew interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 436279377Simp ti,hwmods = "uart3"; 437279377Simp clock-frequency = <48000000>; 438279377Simp status = "disabled"; 439295436Sandrew dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; 440279377Simp dma-names = "tx", "rx"; 441279377Simp }; 442279377Simp 443279377Simp uart4: serial@4806e000 { 444295436Sandrew compatible = "ti,dra742-uart", "ti,omap4-uart"; 445279377Simp reg = <0x4806e000 0x100>; 446295436Sandrew interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 447279377Simp ti,hwmods = "uart4"; 448279377Simp clock-frequency = <48000000>; 449279377Simp status = "disabled"; 450295436Sandrew dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; 451279377Simp dma-names = "tx", "rx"; 452279377Simp }; 453279377Simp 454279377Simp uart5: serial@48066000 { 455295436Sandrew compatible = "ti,dra742-uart", "ti,omap4-uart"; 456279377Simp reg = <0x48066000 0x100>; 457295436Sandrew interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 458279377Simp ti,hwmods = "uart5"; 459279377Simp clock-frequency = <48000000>; 460279377Simp status = "disabled"; 461295436Sandrew dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; 462279377Simp dma-names = "tx", "rx"; 463279377Simp }; 464279377Simp 465279377Simp uart6: serial@48068000 { 466295436Sandrew compatible = "ti,dra742-uart", "ti,omap4-uart"; 467279377Simp reg = <0x48068000 0x100>; 468295436Sandrew interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 469279377Simp ti,hwmods = "uart6"; 470279377Simp clock-frequency = <48000000>; 471279377Simp status = "disabled"; 472295436Sandrew dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; 473279377Simp dma-names = "tx", "rx"; 474279377Simp }; 475279377Simp 476279377Simp uart7: serial@48420000 { 477295436Sandrew compatible = "ti,dra742-uart", "ti,omap4-uart"; 478279377Simp reg = <0x48420000 0x100>; 479295436Sandrew interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 480279377Simp ti,hwmods = "uart7"; 481279377Simp clock-frequency = <48000000>; 482279377Simp status = "disabled"; 483279377Simp }; 484279377Simp 485279377Simp uart8: serial@48422000 { 486295436Sandrew compatible = "ti,dra742-uart", "ti,omap4-uart"; 487279377Simp reg = <0x48422000 0x100>; 488295436Sandrew interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 489279377Simp ti,hwmods = "uart8"; 490279377Simp clock-frequency = <48000000>; 491279377Simp status = "disabled"; 492279377Simp }; 493279377Simp 494279377Simp uart9: serial@48424000 { 495295436Sandrew compatible = "ti,dra742-uart", "ti,omap4-uart"; 496279377Simp reg = <0x48424000 0x100>; 497295436Sandrew interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 498279377Simp ti,hwmods = "uart9"; 499279377Simp clock-frequency = <48000000>; 500279377Simp status = "disabled"; 501279377Simp }; 502279377Simp 503279377Simp uart10: serial@4ae2b000 { 504295436Sandrew compatible = "ti,dra742-uart", "ti,omap4-uart"; 505279377Simp reg = <0x4ae2b000 0x100>; 506295436Sandrew interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 507279377Simp ti,hwmods = "uart10"; 508279377Simp clock-frequency = <48000000>; 509279377Simp status = "disabled"; 510279377Simp }; 511279377Simp 512279377Simp mailbox1: mailbox@4a0f4000 { 513279377Simp compatible = "ti,omap4-mailbox"; 514279377Simp reg = <0x4a0f4000 0x200>; 515279377Simp interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 516279377Simp <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 517279377Simp <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 518279377Simp ti,hwmods = "mailbox1"; 519279377Simp #mbox-cells = <1>; 520279377Simp ti,mbox-num-users = <3>; 521279377Simp ti,mbox-num-fifos = <8>; 522279377Simp status = "disabled"; 523279377Simp }; 524279377Simp 525279377Simp mailbox2: mailbox@4883a000 { 526279377Simp compatible = "ti,omap4-mailbox"; 527279377Simp reg = <0x4883a000 0x200>; 528279377Simp interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 529279377Simp <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 530279377Simp <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 531279377Simp <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 532279377Simp ti,hwmods = "mailbox2"; 533279377Simp #mbox-cells = <1>; 534279377Simp ti,mbox-num-users = <4>; 535279377Simp ti,mbox-num-fifos = <12>; 536279377Simp status = "disabled"; 537279377Simp }; 538279377Simp 539279377Simp mailbox3: mailbox@4883c000 { 540279377Simp compatible = "ti,omap4-mailbox"; 541279377Simp reg = <0x4883c000 0x200>; 542279377Simp interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 543279377Simp <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 544279377Simp <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 545279377Simp <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 546279377Simp ti,hwmods = "mailbox3"; 547279377Simp #mbox-cells = <1>; 548279377Simp ti,mbox-num-users = <4>; 549279377Simp ti,mbox-num-fifos = <12>; 550279377Simp status = "disabled"; 551279377Simp }; 552279377Simp 553279377Simp mailbox4: mailbox@4883e000 { 554279377Simp compatible = "ti,omap4-mailbox"; 555279377Simp reg = <0x4883e000 0x200>; 556279377Simp interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 557279377Simp <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 558279377Simp <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 559279377Simp <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 560279377Simp ti,hwmods = "mailbox4"; 561279377Simp #mbox-cells = <1>; 562279377Simp ti,mbox-num-users = <4>; 563279377Simp ti,mbox-num-fifos = <12>; 564279377Simp status = "disabled"; 565279377Simp }; 566279377Simp 567279377Simp mailbox5: mailbox@48840000 { 568279377Simp compatible = "ti,omap4-mailbox"; 569279377Simp reg = <0x48840000 0x200>; 570279377Simp interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 571279377Simp <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 572279377Simp <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 573279377Simp <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 574279377Simp ti,hwmods = "mailbox5"; 575279377Simp #mbox-cells = <1>; 576279377Simp ti,mbox-num-users = <4>; 577279377Simp ti,mbox-num-fifos = <12>; 578279377Simp status = "disabled"; 579279377Simp }; 580279377Simp 581279377Simp mailbox6: mailbox@48842000 { 582279377Simp compatible = "ti,omap4-mailbox"; 583279377Simp reg = <0x48842000 0x200>; 584279377Simp interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 585279377Simp <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 586279377Simp <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 587279377Simp <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 588279377Simp ti,hwmods = "mailbox6"; 589279377Simp #mbox-cells = <1>; 590279377Simp ti,mbox-num-users = <4>; 591279377Simp ti,mbox-num-fifos = <12>; 592279377Simp status = "disabled"; 593279377Simp }; 594279377Simp 595279377Simp mailbox7: mailbox@48844000 { 596279377Simp compatible = "ti,omap4-mailbox"; 597279377Simp reg = <0x48844000 0x200>; 598279377Simp interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 599279377Simp <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 600279377Simp <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 601279377Simp <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 602279377Simp ti,hwmods = "mailbox7"; 603279377Simp #mbox-cells = <1>; 604279377Simp ti,mbox-num-users = <4>; 605279377Simp ti,mbox-num-fifos = <12>; 606279377Simp status = "disabled"; 607279377Simp }; 608279377Simp 609279377Simp mailbox8: mailbox@48846000 { 610279377Simp compatible = "ti,omap4-mailbox"; 611279377Simp reg = <0x48846000 0x200>; 612279377Simp interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 613279377Simp <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 614279377Simp <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 615279377Simp <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 616279377Simp ti,hwmods = "mailbox8"; 617279377Simp #mbox-cells = <1>; 618279377Simp ti,mbox-num-users = <4>; 619279377Simp ti,mbox-num-fifos = <12>; 620279377Simp status = "disabled"; 621279377Simp }; 622279377Simp 623279377Simp mailbox9: mailbox@4885e000 { 624279377Simp compatible = "ti,omap4-mailbox"; 625279377Simp reg = <0x4885e000 0x200>; 626279377Simp interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 627279377Simp <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 628279377Simp <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 629279377Simp <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 630279377Simp ti,hwmods = "mailbox9"; 631279377Simp #mbox-cells = <1>; 632279377Simp ti,mbox-num-users = <4>; 633279377Simp ti,mbox-num-fifos = <12>; 634279377Simp status = "disabled"; 635279377Simp }; 636279377Simp 637279377Simp mailbox10: mailbox@48860000 { 638279377Simp compatible = "ti,omap4-mailbox"; 639279377Simp reg = <0x48860000 0x200>; 640279377Simp interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 641279377Simp <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 642279377Simp <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 643279377Simp <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 644279377Simp ti,hwmods = "mailbox10"; 645279377Simp #mbox-cells = <1>; 646279377Simp ti,mbox-num-users = <4>; 647279377Simp ti,mbox-num-fifos = <12>; 648279377Simp status = "disabled"; 649279377Simp }; 650279377Simp 651279377Simp mailbox11: mailbox@48862000 { 652279377Simp compatible = "ti,omap4-mailbox"; 653279377Simp reg = <0x48862000 0x200>; 654279377Simp interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 655279377Simp <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 656279377Simp <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 657279377Simp <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 658279377Simp ti,hwmods = "mailbox11"; 659279377Simp #mbox-cells = <1>; 660279377Simp ti,mbox-num-users = <4>; 661279377Simp ti,mbox-num-fifos = <12>; 662279377Simp status = "disabled"; 663279377Simp }; 664279377Simp 665279377Simp mailbox12: mailbox@48864000 { 666279377Simp compatible = "ti,omap4-mailbox"; 667279377Simp reg = <0x48864000 0x200>; 668279377Simp interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 669279377Simp <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 670279377Simp <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 671279377Simp <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 672279377Simp ti,hwmods = "mailbox12"; 673279377Simp #mbox-cells = <1>; 674279377Simp ti,mbox-num-users = <4>; 675279377Simp ti,mbox-num-fifos = <12>; 676279377Simp status = "disabled"; 677279377Simp }; 678279377Simp 679279377Simp mailbox13: mailbox@48802000 { 680279377Simp compatible = "ti,omap4-mailbox"; 681279377Simp reg = <0x48802000 0x200>; 682279377Simp interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 683279377Simp <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 684279377Simp <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 685279377Simp <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; 686279377Simp ti,hwmods = "mailbox13"; 687279377Simp #mbox-cells = <1>; 688279377Simp ti,mbox-num-users = <4>; 689279377Simp ti,mbox-num-fifos = <12>; 690279377Simp status = "disabled"; 691279377Simp }; 692279377Simp 693279377Simp timer1: timer@4ae18000 { 694279377Simp compatible = "ti,omap5430-timer"; 695279377Simp reg = <0x4ae18000 0x80>; 696279377Simp interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 697279377Simp ti,hwmods = "timer1"; 698279377Simp ti,timer-alwon; 699279377Simp }; 700279377Simp 701279377Simp timer2: timer@48032000 { 702279377Simp compatible = "ti,omap5430-timer"; 703279377Simp reg = <0x48032000 0x80>; 704279377Simp interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 705279377Simp ti,hwmods = "timer2"; 706279377Simp }; 707279377Simp 708279377Simp timer3: timer@48034000 { 709279377Simp compatible = "ti,omap5430-timer"; 710279377Simp reg = <0x48034000 0x80>; 711279377Simp interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 712279377Simp ti,hwmods = "timer3"; 713279377Simp }; 714279377Simp 715279377Simp timer4: timer@48036000 { 716279377Simp compatible = "ti,omap5430-timer"; 717279377Simp reg = <0x48036000 0x80>; 718279377Simp interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 719279377Simp ti,hwmods = "timer4"; 720279377Simp }; 721279377Simp 722279377Simp timer5: timer@48820000 { 723279377Simp compatible = "ti,omap5430-timer"; 724279377Simp reg = <0x48820000 0x80>; 725279377Simp interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 726279377Simp ti,hwmods = "timer5"; 727279377Simp }; 728279377Simp 729279377Simp timer6: timer@48822000 { 730279377Simp compatible = "ti,omap5430-timer"; 731279377Simp reg = <0x48822000 0x80>; 732279377Simp interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 733279377Simp ti,hwmods = "timer6"; 734279377Simp }; 735279377Simp 736279377Simp timer7: timer@48824000 { 737279377Simp compatible = "ti,omap5430-timer"; 738279377Simp reg = <0x48824000 0x80>; 739279377Simp interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 740279377Simp ti,hwmods = "timer7"; 741279377Simp }; 742279377Simp 743279377Simp timer8: timer@48826000 { 744279377Simp compatible = "ti,omap5430-timer"; 745279377Simp reg = <0x48826000 0x80>; 746279377Simp interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 747279377Simp ti,hwmods = "timer8"; 748279377Simp }; 749279377Simp 750279377Simp timer9: timer@4803e000 { 751279377Simp compatible = "ti,omap5430-timer"; 752279377Simp reg = <0x4803e000 0x80>; 753279377Simp interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 754279377Simp ti,hwmods = "timer9"; 755279377Simp }; 756279377Simp 757279377Simp timer10: timer@48086000 { 758279377Simp compatible = "ti,omap5430-timer"; 759279377Simp reg = <0x48086000 0x80>; 760279377Simp interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 761279377Simp ti,hwmods = "timer10"; 762279377Simp }; 763279377Simp 764279377Simp timer11: timer@48088000 { 765279377Simp compatible = "ti,omap5430-timer"; 766279377Simp reg = <0x48088000 0x80>; 767279377Simp interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 768279377Simp ti,hwmods = "timer11"; 769279377Simp }; 770279377Simp 771279377Simp timer13: timer@48828000 { 772279377Simp compatible = "ti,omap5430-timer"; 773279377Simp reg = <0x48828000 0x80>; 774279377Simp interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 775279377Simp ti,hwmods = "timer13"; 776279377Simp status = "disabled"; 777279377Simp }; 778279377Simp 779279377Simp timer14: timer@4882a000 { 780279377Simp compatible = "ti,omap5430-timer"; 781279377Simp reg = <0x4882a000 0x80>; 782279377Simp interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 783279377Simp ti,hwmods = "timer14"; 784279377Simp status = "disabled"; 785279377Simp }; 786279377Simp 787279377Simp timer15: timer@4882c000 { 788279377Simp compatible = "ti,omap5430-timer"; 789279377Simp reg = <0x4882c000 0x80>; 790279377Simp interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 791279377Simp ti,hwmods = "timer15"; 792279377Simp status = "disabled"; 793279377Simp }; 794279377Simp 795279377Simp timer16: timer@4882e000 { 796279377Simp compatible = "ti,omap5430-timer"; 797279377Simp reg = <0x4882e000 0x80>; 798279377Simp interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 799279377Simp ti,hwmods = "timer16"; 800279377Simp status = "disabled"; 801279377Simp }; 802279377Simp 803279377Simp wdt2: wdt@4ae14000 { 804279377Simp compatible = "ti,omap3-wdt"; 805279377Simp reg = <0x4ae14000 0x80>; 806279377Simp interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 807279377Simp ti,hwmods = "wd_timer2"; 808279377Simp }; 809279377Simp 810279377Simp hwspinlock: spinlock@4a0f6000 { 811279377Simp compatible = "ti,omap4-hwspinlock"; 812279377Simp reg = <0x4a0f6000 0x1000>; 813279377Simp ti,hwmods = "spinlock"; 814279377Simp #hwlock-cells = <1>; 815279377Simp }; 816279377Simp 817279377Simp dmm@4e000000 { 818279377Simp compatible = "ti,omap5-dmm"; 819279377Simp reg = <0x4e000000 0x800>; 820279377Simp interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 821279377Simp ti,hwmods = "dmm"; 822279377Simp }; 823279377Simp 824279377Simp i2c1: i2c@48070000 { 825279377Simp compatible = "ti,omap4-i2c"; 826279377Simp reg = <0x48070000 0x100>; 827279377Simp interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 828279377Simp #address-cells = <1>; 829279377Simp #size-cells = <0>; 830279377Simp ti,hwmods = "i2c1"; 831279377Simp status = "disabled"; 832279377Simp }; 833279377Simp 834279377Simp i2c2: i2c@48072000 { 835279377Simp compatible = "ti,omap4-i2c"; 836279377Simp reg = <0x48072000 0x100>; 837279377Simp interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 838279377Simp #address-cells = <1>; 839279377Simp #size-cells = <0>; 840279377Simp ti,hwmods = "i2c2"; 841279377Simp status = "disabled"; 842279377Simp }; 843279377Simp 844279377Simp i2c3: i2c@48060000 { 845279377Simp compatible = "ti,omap4-i2c"; 846279377Simp reg = <0x48060000 0x100>; 847279377Simp interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 848279377Simp #address-cells = <1>; 849279377Simp #size-cells = <0>; 850279377Simp ti,hwmods = "i2c3"; 851279377Simp status = "disabled"; 852279377Simp }; 853279377Simp 854279377Simp i2c4: i2c@4807a000 { 855279377Simp compatible = "ti,omap4-i2c"; 856279377Simp reg = <0x4807a000 0x100>; 857279377Simp interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 858279377Simp #address-cells = <1>; 859279377Simp #size-cells = <0>; 860279377Simp ti,hwmods = "i2c4"; 861279377Simp status = "disabled"; 862279377Simp }; 863279377Simp 864279377Simp i2c5: i2c@4807c000 { 865279377Simp compatible = "ti,omap4-i2c"; 866279377Simp reg = <0x4807c000 0x100>; 867279377Simp interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 868279377Simp #address-cells = <1>; 869279377Simp #size-cells = <0>; 870279377Simp ti,hwmods = "i2c5"; 871279377Simp status = "disabled"; 872279377Simp }; 873279377Simp 874279377Simp mmc1: mmc@4809c000 { 875279377Simp compatible = "ti,omap4-hsmmc"; 876279377Simp reg = <0x4809c000 0x400>; 877279377Simp interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 878279377Simp ti,hwmods = "mmc1"; 879279377Simp ti,dual-volt; 880279377Simp ti,needs-special-reset; 881295436Sandrew dmas = <&sdma_xbar 61>, <&sdma_xbar 62>; 882279377Simp dma-names = "tx", "rx"; 883279377Simp status = "disabled"; 884279377Simp pbias-supply = <&pbias_mmc_reg>; 885279377Simp }; 886279377Simp 887279377Simp mmc2: mmc@480b4000 { 888279377Simp compatible = "ti,omap4-hsmmc"; 889279377Simp reg = <0x480b4000 0x400>; 890279377Simp interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 891279377Simp ti,hwmods = "mmc2"; 892279377Simp ti,needs-special-reset; 893295436Sandrew dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; 894279377Simp dma-names = "tx", "rx"; 895279377Simp status = "disabled"; 896279377Simp }; 897279377Simp 898279377Simp mmc3: mmc@480ad000 { 899279377Simp compatible = "ti,omap4-hsmmc"; 900279377Simp reg = <0x480ad000 0x400>; 901279377Simp interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 902279377Simp ti,hwmods = "mmc3"; 903279377Simp ti,needs-special-reset; 904295436Sandrew dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; 905279377Simp dma-names = "tx", "rx"; 906279377Simp status = "disabled"; 907279377Simp }; 908279377Simp 909279377Simp mmc4: mmc@480d1000 { 910279377Simp compatible = "ti,omap4-hsmmc"; 911279377Simp reg = <0x480d1000 0x400>; 912279377Simp interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 913279377Simp ti,hwmods = "mmc4"; 914279377Simp ti,needs-special-reset; 915295436Sandrew dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; 916279377Simp dma-names = "tx", "rx"; 917279377Simp status = "disabled"; 918279377Simp }; 919279377Simp 920295436Sandrew mmu0_dsp1: mmu@40d01000 { 921295436Sandrew compatible = "ti,dra7-dsp-iommu"; 922295436Sandrew reg = <0x40d01000 0x100>; 923295436Sandrew interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 924295436Sandrew ti,hwmods = "mmu0_dsp1"; 925295436Sandrew #iommu-cells = <0>; 926295436Sandrew ti,syscon-mmuconfig = <&dsp1_system 0x0>; 927295436Sandrew status = "disabled"; 928295436Sandrew }; 929295436Sandrew 930295436Sandrew mmu1_dsp1: mmu@40d02000 { 931295436Sandrew compatible = "ti,dra7-dsp-iommu"; 932295436Sandrew reg = <0x40d02000 0x100>; 933295436Sandrew interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 934295436Sandrew ti,hwmods = "mmu1_dsp1"; 935295436Sandrew #iommu-cells = <0>; 936295436Sandrew ti,syscon-mmuconfig = <&dsp1_system 0x1>; 937295436Sandrew status = "disabled"; 938295436Sandrew }; 939295436Sandrew 940295436Sandrew mmu_ipu1: mmu@58882000 { 941295436Sandrew compatible = "ti,dra7-iommu"; 942295436Sandrew reg = <0x58882000 0x100>; 943295436Sandrew interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; 944295436Sandrew ti,hwmods = "mmu_ipu1"; 945295436Sandrew #iommu-cells = <0>; 946295436Sandrew ti,iommu-bus-err-back; 947295436Sandrew status = "disabled"; 948295436Sandrew }; 949295436Sandrew 950295436Sandrew mmu_ipu2: mmu@55082000 { 951295436Sandrew compatible = "ti,dra7-iommu"; 952295436Sandrew reg = <0x55082000 0x100>; 953295436Sandrew interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 954295436Sandrew ti,hwmods = "mmu_ipu2"; 955295436Sandrew #iommu-cells = <0>; 956295436Sandrew ti,iommu-bus-err-back; 957295436Sandrew status = "disabled"; 958295436Sandrew }; 959295436Sandrew 960279377Simp abb_mpu: regulator-abb-mpu { 961279377Simp compatible = "ti,abb-v3"; 962279377Simp regulator-name = "abb_mpu"; 963279377Simp #address-cells = <0>; 964279377Simp #size-cells = <0>; 965279377Simp clocks = <&sys_clkin1>; 966279377Simp ti,settling-time = <50>; 967279377Simp ti,clock-cycles = <16>; 968279377Simp 969279377Simp reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, 970295436Sandrew <0x4ae06014 0x4>, <0x4a003b20 0xc>, 971279377Simp <0x4ae0c158 0x4>; 972279377Simp reg-names = "setup-address", "control-address", 973279377Simp "int-address", "efuse-address", 974279377Simp "ldo-address"; 975279377Simp ti,tranxdone-status-mask = <0x80>; 976279377Simp /* LDOVBBMPU_FBB_MUX_CTRL */ 977279377Simp ti,ldovbb-override-mask = <0x400>; 978279377Simp /* LDOVBBMPU_FBB_VSET_OUT */ 979279377Simp ti,ldovbb-vset-mask = <0x1F>; 980279377Simp 981279377Simp /* 982279377Simp * NOTE: only FBB mode used but actual vset will 983279377Simp * determine final biasing 984279377Simp */ 985279377Simp ti,abb_info = < 986279377Simp /*uV ABB efuse rbb_m fbb_m vset_m*/ 987279377Simp 1060000 0 0x0 0 0x02000000 0x01F00000 988279377Simp 1160000 0 0x4 0 0x02000000 0x01F00000 989279377Simp 1210000 0 0x8 0 0x02000000 0x01F00000 990279377Simp >; 991279377Simp }; 992279377Simp 993279377Simp abb_ivahd: regulator-abb-ivahd { 994279377Simp compatible = "ti,abb-v3"; 995279377Simp regulator-name = "abb_ivahd"; 996279377Simp #address-cells = <0>; 997279377Simp #size-cells = <0>; 998279377Simp clocks = <&sys_clkin1>; 999279377Simp ti,settling-time = <50>; 1000279377Simp ti,clock-cycles = <16>; 1001279377Simp 1002279377Simp reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, 1003295436Sandrew <0x4ae06010 0x4>, <0x4a0025cc 0xc>, 1004279377Simp <0x4a002470 0x4>; 1005279377Simp reg-names = "setup-address", "control-address", 1006279377Simp "int-address", "efuse-address", 1007279377Simp "ldo-address"; 1008279377Simp ti,tranxdone-status-mask = <0x40000000>; 1009279377Simp /* LDOVBBIVA_FBB_MUX_CTRL */ 1010279377Simp ti,ldovbb-override-mask = <0x400>; 1011279377Simp /* LDOVBBIVA_FBB_VSET_OUT */ 1012279377Simp ti,ldovbb-vset-mask = <0x1F>; 1013279377Simp 1014279377Simp /* 1015279377Simp * NOTE: only FBB mode used but actual vset will 1016279377Simp * determine final biasing 1017279377Simp */ 1018279377Simp ti,abb_info = < 1019279377Simp /*uV ABB efuse rbb_m fbb_m vset_m*/ 1020279377Simp 1055000 0 0x0 0 0x02000000 0x01F00000 1021279377Simp 1150000 0 0x4 0 0x02000000 0x01F00000 1022279377Simp 1250000 0 0x8 0 0x02000000 0x01F00000 1023279377Simp >; 1024279377Simp }; 1025279377Simp 1026279377Simp abb_dspeve: regulator-abb-dspeve { 1027279377Simp compatible = "ti,abb-v3"; 1028279377Simp regulator-name = "abb_dspeve"; 1029279377Simp #address-cells = <0>; 1030279377Simp #size-cells = <0>; 1031279377Simp clocks = <&sys_clkin1>; 1032279377Simp ti,settling-time = <50>; 1033279377Simp ti,clock-cycles = <16>; 1034279377Simp 1035279377Simp reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, 1036295436Sandrew <0x4ae06010 0x4>, <0x4a0025e0 0xc>, 1037279377Simp <0x4a00246c 0x4>; 1038279377Simp reg-names = "setup-address", "control-address", 1039279377Simp "int-address", "efuse-address", 1040279377Simp "ldo-address"; 1041279377Simp ti,tranxdone-status-mask = <0x20000000>; 1042279377Simp /* LDOVBBDSPEVE_FBB_MUX_CTRL */ 1043279377Simp ti,ldovbb-override-mask = <0x400>; 1044279377Simp /* LDOVBBDSPEVE_FBB_VSET_OUT */ 1045279377Simp ti,ldovbb-vset-mask = <0x1F>; 1046279377Simp 1047279377Simp /* 1048279377Simp * NOTE: only FBB mode used but actual vset will 1049279377Simp * determine final biasing 1050279377Simp */ 1051279377Simp ti,abb_info = < 1052279377Simp /*uV ABB efuse rbb_m fbb_m vset_m*/ 1053279377Simp 1055000 0 0x0 0 0x02000000 0x01F00000 1054279377Simp 1150000 0 0x4 0 0x02000000 0x01F00000 1055279377Simp 1250000 0 0x8 0 0x02000000 0x01F00000 1056279377Simp >; 1057279377Simp }; 1058279377Simp 1059279377Simp abb_gpu: regulator-abb-gpu { 1060279377Simp compatible = "ti,abb-v3"; 1061279377Simp regulator-name = "abb_gpu"; 1062279377Simp #address-cells = <0>; 1063279377Simp #size-cells = <0>; 1064279377Simp clocks = <&sys_clkin1>; 1065279377Simp ti,settling-time = <50>; 1066279377Simp ti,clock-cycles = <16>; 1067279377Simp 1068279377Simp reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, 1069295436Sandrew <0x4ae06010 0x4>, <0x4a003b08 0xc>, 1070279377Simp <0x4ae0c154 0x4>; 1071279377Simp reg-names = "setup-address", "control-address", 1072279377Simp "int-address", "efuse-address", 1073279377Simp "ldo-address"; 1074279377Simp ti,tranxdone-status-mask = <0x10000000>; 1075279377Simp /* LDOVBBGPU_FBB_MUX_CTRL */ 1076279377Simp ti,ldovbb-override-mask = <0x400>; 1077279377Simp /* LDOVBBGPU_FBB_VSET_OUT */ 1078279377Simp ti,ldovbb-vset-mask = <0x1F>; 1079279377Simp 1080279377Simp /* 1081279377Simp * NOTE: only FBB mode used but actual vset will 1082279377Simp * determine final biasing 1083279377Simp */ 1084279377Simp ti,abb_info = < 1085279377Simp /*uV ABB efuse rbb_m fbb_m vset_m*/ 1086279377Simp 1090000 0 0x0 0 0x02000000 0x01F00000 1087279377Simp 1210000 0 0x4 0 0x02000000 0x01F00000 1088279377Simp 1280000 0 0x8 0 0x02000000 0x01F00000 1089279377Simp >; 1090279377Simp }; 1091279377Simp 1092279377Simp mcspi1: spi@48098000 { 1093279377Simp compatible = "ti,omap4-mcspi"; 1094279377Simp reg = <0x48098000 0x200>; 1095279377Simp interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1096279377Simp #address-cells = <1>; 1097279377Simp #size-cells = <0>; 1098279377Simp ti,hwmods = "mcspi1"; 1099279377Simp ti,spi-num-cs = <4>; 1100295436Sandrew dmas = <&sdma_xbar 35>, 1101295436Sandrew <&sdma_xbar 36>, 1102295436Sandrew <&sdma_xbar 37>, 1103295436Sandrew <&sdma_xbar 38>, 1104295436Sandrew <&sdma_xbar 39>, 1105295436Sandrew <&sdma_xbar 40>, 1106295436Sandrew <&sdma_xbar 41>, 1107295436Sandrew <&sdma_xbar 42>; 1108279377Simp dma-names = "tx0", "rx0", "tx1", "rx1", 1109279377Simp "tx2", "rx2", "tx3", "rx3"; 1110279377Simp status = "disabled"; 1111279377Simp }; 1112279377Simp 1113279377Simp mcspi2: spi@4809a000 { 1114279377Simp compatible = "ti,omap4-mcspi"; 1115279377Simp reg = <0x4809a000 0x200>; 1116279377Simp interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1117279377Simp #address-cells = <1>; 1118279377Simp #size-cells = <0>; 1119279377Simp ti,hwmods = "mcspi2"; 1120279377Simp ti,spi-num-cs = <2>; 1121295436Sandrew dmas = <&sdma_xbar 43>, 1122295436Sandrew <&sdma_xbar 44>, 1123295436Sandrew <&sdma_xbar 45>, 1124295436Sandrew <&sdma_xbar 46>; 1125279377Simp dma-names = "tx0", "rx0", "tx1", "rx1"; 1126279377Simp status = "disabled"; 1127279377Simp }; 1128279377Simp 1129279377Simp mcspi3: spi@480b8000 { 1130279377Simp compatible = "ti,omap4-mcspi"; 1131279377Simp reg = <0x480b8000 0x200>; 1132279377Simp interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1133279377Simp #address-cells = <1>; 1134279377Simp #size-cells = <0>; 1135279377Simp ti,hwmods = "mcspi3"; 1136279377Simp ti,spi-num-cs = <2>; 1137295436Sandrew dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; 1138279377Simp dma-names = "tx0", "rx0"; 1139279377Simp status = "disabled"; 1140279377Simp }; 1141279377Simp 1142279377Simp mcspi4: spi@480ba000 { 1143279377Simp compatible = "ti,omap4-mcspi"; 1144279377Simp reg = <0x480ba000 0x200>; 1145279377Simp interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1146279377Simp #address-cells = <1>; 1147279377Simp #size-cells = <0>; 1148279377Simp ti,hwmods = "mcspi4"; 1149279377Simp ti,spi-num-cs = <1>; 1150295436Sandrew dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; 1151279377Simp dma-names = "tx0", "rx0"; 1152279377Simp status = "disabled"; 1153279377Simp }; 1154279377Simp 1155279377Simp qspi: qspi@4b300000 { 1156279377Simp compatible = "ti,dra7xxx-qspi"; 1157295436Sandrew reg = <0x4b300000 0x100>, 1158295436Sandrew <0x5c000000 0x4000000>; 1159295436Sandrew reg-names = "qspi_base", "qspi_mmap"; 1160295436Sandrew syscon-chipselects = <&scm_conf 0x558>; 1161279377Simp #address-cells = <1>; 1162279377Simp #size-cells = <0>; 1163279377Simp ti,hwmods = "qspi"; 1164279377Simp clocks = <&qspi_gfclk_div>; 1165279377Simp clock-names = "fck"; 1166279377Simp num-cs = <4>; 1167279377Simp interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1168279377Simp status = "disabled"; 1169279377Simp }; 1170279377Simp 1171279377Simp omap_control_sata: control-phy@4a002374 { 1172279377Simp compatible = "ti,control-phy-pipe3"; 1173279377Simp reg = <0x4a002374 0x4>; 1174279377Simp reg-names = "power"; 1175279377Simp clocks = <&sys_clkin1>; 1176279377Simp clock-names = "sysclk"; 1177279377Simp }; 1178279377Simp 1179279377Simp /* OCP2SCP3 */ 1180279377Simp ocp2scp@4a090000 { 1181279377Simp compatible = "ti,omap-ocp2scp"; 1182279377Simp #address-cells = <1>; 1183279377Simp #size-cells = <1>; 1184279377Simp ranges; 1185279377Simp reg = <0x4a090000 0x20>; 1186279377Simp ti,hwmods = "ocp2scp3"; 1187279377Simp sata_phy: phy@4A096000 { 1188279377Simp compatible = "ti,phy-pipe3-sata"; 1189279377Simp reg = <0x4A096000 0x80>, /* phy_rx */ 1190279377Simp <0x4A096400 0x64>, /* phy_tx */ 1191279377Simp <0x4A096800 0x40>; /* pll_ctrl */ 1192279377Simp reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1193279377Simp ctrl-module = <&omap_control_sata>; 1194295436Sandrew clocks = <&sys_clkin1>, <&sata_ref_clk>; 1195295436Sandrew clock-names = "sysclk", "refclk"; 1196295436Sandrew syscon-pllreset = <&scm_conf 0x3fc>; 1197279377Simp #phy-cells = <0>; 1198279377Simp }; 1199279377Simp 1200279377Simp pcie1_phy: pciephy@4a094000 { 1201279377Simp compatible = "ti,phy-pipe3-pcie"; 1202279377Simp reg = <0x4a094000 0x80>, /* phy_rx */ 1203279377Simp <0x4a094400 0x64>; /* phy_tx */ 1204279377Simp reg-names = "phy_rx", "phy_tx"; 1205279377Simp ctrl-module = <&omap_control_pcie1phy>; 1206279377Simp clocks = <&dpll_pcie_ref_ck>, 1207279377Simp <&dpll_pcie_ref_m2ldo_ck>, 1208279377Simp <&optfclk_pciephy1_32khz>, 1209279377Simp <&optfclk_pciephy1_clk>, 1210279377Simp <&optfclk_pciephy1_div_clk>, 1211279377Simp <&optfclk_pciephy_div>; 1212279377Simp clock-names = "dpll_ref", "dpll_ref_m2", 1213279377Simp "wkupclk", "refclk", 1214279377Simp "div-clk", "phy-div"; 1215279377Simp #phy-cells = <0>; 1216279377Simp }; 1217279377Simp 1218279377Simp pcie2_phy: pciephy@4a095000 { 1219279377Simp compatible = "ti,phy-pipe3-pcie"; 1220279377Simp reg = <0x4a095000 0x80>, /* phy_rx */ 1221279377Simp <0x4a095400 0x64>; /* phy_tx */ 1222279377Simp reg-names = "phy_rx", "phy_tx"; 1223279377Simp ctrl-module = <&omap_control_pcie2phy>; 1224279377Simp clocks = <&dpll_pcie_ref_ck>, 1225279377Simp <&dpll_pcie_ref_m2ldo_ck>, 1226279377Simp <&optfclk_pciephy2_32khz>, 1227279377Simp <&optfclk_pciephy2_clk>, 1228279377Simp <&optfclk_pciephy2_div_clk>, 1229279377Simp <&optfclk_pciephy_div>; 1230279377Simp clock-names = "dpll_ref", "dpll_ref_m2", 1231279377Simp "wkupclk", "refclk", 1232279377Simp "div-clk", "phy-div"; 1233279377Simp #phy-cells = <0>; 1234279377Simp status = "disabled"; 1235279377Simp }; 1236279377Simp }; 1237279377Simp 1238279377Simp sata: sata@4a141100 { 1239279377Simp compatible = "snps,dwc-ahci"; 1240279377Simp reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; 1241279377Simp interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1242279377Simp phys = <&sata_phy>; 1243279377Simp phy-names = "sata-phy"; 1244279377Simp clocks = <&sata_ref_clk>; 1245279377Simp ti,hwmods = "sata"; 1246279377Simp }; 1247279377Simp 1248279377Simp omap_control_pcie1phy: control-phy@0x4a003c40 { 1249279377Simp compatible = "ti,control-phy-pcie"; 1250279377Simp reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; 1251279377Simp reg-names = "power", "control_sma", "pcie_pcs"; 1252279377Simp clocks = <&sys_clkin1>; 1253279377Simp clock-names = "sysclk"; 1254279377Simp }; 1255279377Simp 1256279377Simp omap_control_pcie2phy: control-pcie@0x4a003c44 { 1257279377Simp compatible = "ti,control-phy-pcie"; 1258279377Simp reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; 1259279377Simp reg-names = "power", "control_sma", "pcie_pcs"; 1260279377Simp clocks = <&sys_clkin1>; 1261279377Simp clock-names = "sysclk"; 1262279377Simp status = "disabled"; 1263279377Simp }; 1264279377Simp 1265295436Sandrew rtc: rtc@48838000 { 1266279377Simp compatible = "ti,am3352-rtc"; 1267279377Simp reg = <0x48838000 0x100>; 1268279377Simp interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1269279377Simp <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 1270279377Simp ti,hwmods = "rtcss"; 1271279377Simp clocks = <&sys_32k_ck>; 1272279377Simp }; 1273279377Simp 1274279377Simp omap_control_usb2phy1: control-phy@4a002300 { 1275279377Simp compatible = "ti,control-phy-usb2"; 1276279377Simp reg = <0x4a002300 0x4>; 1277279377Simp reg-names = "power"; 1278279377Simp }; 1279279377Simp 1280279377Simp omap_control_usb3phy1: control-phy@4a002370 { 1281279377Simp compatible = "ti,control-phy-pipe3"; 1282279377Simp reg = <0x4a002370 0x4>; 1283279377Simp reg-names = "power"; 1284279377Simp }; 1285279377Simp 1286279377Simp omap_control_usb2phy2: control-phy@0x4a002e74 { 1287279377Simp compatible = "ti,control-phy-usb2-dra7"; 1288279377Simp reg = <0x4a002e74 0x4>; 1289279377Simp reg-names = "power"; 1290279377Simp }; 1291279377Simp 1292279377Simp /* OCP2SCP1 */ 1293279377Simp ocp2scp@4a080000 { 1294279377Simp compatible = "ti,omap-ocp2scp"; 1295279377Simp #address-cells = <1>; 1296279377Simp #size-cells = <1>; 1297279377Simp ranges; 1298279377Simp reg = <0x4a080000 0x20>; 1299279377Simp ti,hwmods = "ocp2scp1"; 1300279377Simp 1301279377Simp usb2_phy1: phy@4a084000 { 1302279377Simp compatible = "ti,omap-usb2"; 1303279377Simp reg = <0x4a084000 0x400>; 1304279377Simp ctrl-module = <&omap_control_usb2phy1>; 1305279377Simp clocks = <&usb_phy1_always_on_clk32k>, 1306279377Simp <&usb_otg_ss1_refclk960m>; 1307279377Simp clock-names = "wkupclk", 1308279377Simp "refclk"; 1309279377Simp #phy-cells = <0>; 1310279377Simp }; 1311279377Simp 1312279377Simp usb2_phy2: phy@4a085000 { 1313279377Simp compatible = "ti,omap-usb2"; 1314279377Simp reg = <0x4a085000 0x400>; 1315279377Simp ctrl-module = <&omap_control_usb2phy2>; 1316279377Simp clocks = <&usb_phy2_always_on_clk32k>, 1317279377Simp <&usb_otg_ss2_refclk960m>; 1318279377Simp clock-names = "wkupclk", 1319279377Simp "refclk"; 1320279377Simp #phy-cells = <0>; 1321279377Simp }; 1322279377Simp 1323279377Simp usb3_phy1: phy@4a084400 { 1324279377Simp compatible = "ti,omap-usb3"; 1325279377Simp reg = <0x4a084400 0x80>, 1326279377Simp <0x4a084800 0x64>, 1327279377Simp <0x4a084c00 0x40>; 1328279377Simp reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1329279377Simp ctrl-module = <&omap_control_usb3phy1>; 1330279377Simp clocks = <&usb_phy3_always_on_clk32k>, 1331279377Simp <&sys_clkin1>, 1332279377Simp <&usb_otg_ss1_refclk960m>; 1333279377Simp clock-names = "wkupclk", 1334279377Simp "sysclk", 1335279377Simp "refclk"; 1336279377Simp #phy-cells = <0>; 1337279377Simp }; 1338279377Simp }; 1339279377Simp 1340279377Simp omap_dwc3_1: omap_dwc3_1@48880000 { 1341279377Simp compatible = "ti,dwc3"; 1342279377Simp ti,hwmods = "usb_otg_ss1"; 1343279377Simp reg = <0x48880000 0x10000>; 1344279377Simp interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1345279377Simp #address-cells = <1>; 1346279377Simp #size-cells = <1>; 1347279377Simp utmi-mode = <2>; 1348279377Simp ranges; 1349279377Simp usb1: usb@48890000 { 1350279377Simp compatible = "snps,dwc3"; 1351279377Simp reg = <0x48890000 0x17000>; 1352295436Sandrew interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1353295436Sandrew <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1354295436Sandrew <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1355295436Sandrew interrupt-names = "peripheral", 1356295436Sandrew "host", 1357295436Sandrew "otg"; 1358279377Simp phys = <&usb2_phy1>, <&usb3_phy1>; 1359279377Simp phy-names = "usb2-phy", "usb3-phy"; 1360279377Simp tx-fifo-resize; 1361279377Simp maximum-speed = "super-speed"; 1362279377Simp dr_mode = "otg"; 1363279377Simp snps,dis_u3_susphy_quirk; 1364279377Simp snps,dis_u2_susphy_quirk; 1365279377Simp }; 1366279377Simp }; 1367279377Simp 1368279377Simp omap_dwc3_2: omap_dwc3_2@488c0000 { 1369279377Simp compatible = "ti,dwc3"; 1370279377Simp ti,hwmods = "usb_otg_ss2"; 1371279377Simp reg = <0x488c0000 0x10000>; 1372279377Simp interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1373279377Simp #address-cells = <1>; 1374279377Simp #size-cells = <1>; 1375279377Simp utmi-mode = <2>; 1376279377Simp ranges; 1377279377Simp usb2: usb@488d0000 { 1378279377Simp compatible = "snps,dwc3"; 1379279377Simp reg = <0x488d0000 0x17000>; 1380295436Sandrew interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1381295436Sandrew <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1382295436Sandrew <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1383295436Sandrew interrupt-names = "peripheral", 1384295436Sandrew "host", 1385295436Sandrew "otg"; 1386279377Simp phys = <&usb2_phy2>; 1387279377Simp phy-names = "usb2-phy"; 1388279377Simp tx-fifo-resize; 1389279377Simp maximum-speed = "high-speed"; 1390279377Simp dr_mode = "otg"; 1391279377Simp snps,dis_u3_susphy_quirk; 1392279377Simp snps,dis_u2_susphy_quirk; 1393279377Simp }; 1394279377Simp }; 1395279377Simp 1396279377Simp /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ 1397279377Simp omap_dwc3_3: omap_dwc3_3@48900000 { 1398279377Simp compatible = "ti,dwc3"; 1399279377Simp ti,hwmods = "usb_otg_ss3"; 1400279377Simp reg = <0x48900000 0x10000>; 1401279377Simp interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1402279377Simp #address-cells = <1>; 1403279377Simp #size-cells = <1>; 1404279377Simp utmi-mode = <2>; 1405279377Simp ranges; 1406279377Simp status = "disabled"; 1407279377Simp usb3: usb@48910000 { 1408279377Simp compatible = "snps,dwc3"; 1409279377Simp reg = <0x48910000 0x17000>; 1410295436Sandrew interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1411295436Sandrew <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1412295436Sandrew <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1413295436Sandrew interrupt-names = "peripheral", 1414295436Sandrew "host", 1415295436Sandrew "otg"; 1416279377Simp tx-fifo-resize; 1417279377Simp maximum-speed = "high-speed"; 1418279377Simp dr_mode = "otg"; 1419279377Simp snps,dis_u3_susphy_quirk; 1420279377Simp snps,dis_u2_susphy_quirk; 1421279377Simp }; 1422279377Simp }; 1423279377Simp 1424279377Simp elm: elm@48078000 { 1425279377Simp compatible = "ti,am3352-elm"; 1426279377Simp reg = <0x48078000 0xfc0>; /* device IO registers */ 1427279377Simp interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1428279377Simp ti,hwmods = "elm"; 1429279377Simp status = "disabled"; 1430279377Simp }; 1431279377Simp 1432279377Simp gpmc: gpmc@50000000 { 1433279377Simp compatible = "ti,am3352-gpmc"; 1434279377Simp ti,hwmods = "gpmc"; 1435279377Simp reg = <0x50000000 0x37c>; /* device IO registers */ 1436279377Simp interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1437279377Simp gpmc,num-cs = <8>; 1438279377Simp gpmc,num-waitpins = <2>; 1439279377Simp #address-cells = <2>; 1440279377Simp #size-cells = <1>; 1441279377Simp status = "disabled"; 1442279377Simp }; 1443279377Simp 1444279377Simp atl: atl@4843c000 { 1445279377Simp compatible = "ti,dra7-atl"; 1446279377Simp reg = <0x4843c000 0x3ff>; 1447279377Simp ti,hwmods = "atl"; 1448279377Simp ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, 1449279377Simp <&atl_clkin2_ck>, <&atl_clkin3_ck>; 1450279377Simp clocks = <&atl_gfclk_mux>; 1451279377Simp clock-names = "fck"; 1452279377Simp status = "disabled"; 1453279377Simp }; 1454279377Simp 1455295436Sandrew mcasp3: mcasp@48468000 { 1456295436Sandrew compatible = "ti,dra7-mcasp-audio"; 1457295436Sandrew ti,hwmods = "mcasp3"; 1458295436Sandrew reg = <0x48468000 0x2000>; 1459295436Sandrew reg-names = "mpu"; 1460295436Sandrew interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1461295436Sandrew <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1462295436Sandrew interrupt-names = "tx", "rx"; 1463295436Sandrew dmas = <&sdma_xbar 133>, <&sdma_xbar 132>; 1464295436Sandrew dma-names = "tx", "rx"; 1465295436Sandrew clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>; 1466295436Sandrew clock-names = "fck", "ahclkx"; 1467295436Sandrew status = "disabled"; 1468295436Sandrew }; 1469295436Sandrew 1470295436Sandrew crossbar_mpu: crossbar@4a002a48 { 1471279377Simp compatible = "ti,irq-crossbar"; 1472279377Simp reg = <0x4a002a48 0x130>; 1473295436Sandrew interrupt-controller; 1474295436Sandrew interrupt-parent = <&wakeupgen>; 1475295436Sandrew #interrupt-cells = <3>; 1476279377Simp ti,max-irqs = <160>; 1477279377Simp ti,max-crossbar-sources = <MAX_SOURCES>; 1478279377Simp ti,reg-size = <2>; 1479279377Simp ti,irqs-reserved = <0 1 2 3 5 6 131 132>; 1480279377Simp ti,irqs-skip = <10 133 139 140>; 1481279377Simp ti,irqs-safe-map = <0>; 1482279377Simp }; 1483279377Simp 1484295436Sandrew mac: ethernet@48484000 { 1485295436Sandrew compatible = "ti,dra7-cpsw","ti,cpsw"; 1486279377Simp ti,hwmods = "gmac"; 1487279377Simp clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; 1488279377Simp clock-names = "fck", "cpts"; 1489279377Simp cpdma_channels = <8>; 1490279377Simp ale_entries = <1024>; 1491279377Simp bd_ram_size = <0x2000>; 1492279377Simp no_bd_ram = <0>; 1493279377Simp rx_descs = <64>; 1494279377Simp mac_control = <0x20>; 1495279377Simp slaves = <2>; 1496279377Simp active_slave = <0>; 1497279377Simp cpts_clock_mult = <0x80000000>; 1498279377Simp cpts_clock_shift = <29>; 1499279377Simp reg = <0x48484000 0x1000 1500279377Simp 0x48485200 0x2E00>; 1501279377Simp #address-cells = <1>; 1502279377Simp #size-cells = <1>; 1503279377Simp /* 1504279377Simp * rx_thresh_pend 1505279377Simp * rx_pend 1506279377Simp * tx_pend 1507279377Simp * misc_pend 1508279377Simp */ 1509279377Simp interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1510279377Simp <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1511279377Simp <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1512279377Simp <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 1513279377Simp ranges; 1514295436Sandrew syscon = <&scm_conf>; 1515279377Simp status = "disabled"; 1516279377Simp 1517279377Simp davinci_mdio: mdio@48485000 { 1518279377Simp compatible = "ti,davinci_mdio"; 1519279377Simp #address-cells = <1>; 1520279377Simp #size-cells = <0>; 1521279377Simp ti,hwmods = "davinci_mdio"; 1522279377Simp bus_freq = <1000000>; 1523279377Simp reg = <0x48485000 0x100>; 1524279377Simp }; 1525279377Simp 1526279377Simp cpsw_emac0: slave@48480200 { 1527279377Simp /* Filled in by U-Boot */ 1528279377Simp mac-address = [ 00 00 00 00 00 00 ]; 1529279377Simp }; 1530279377Simp 1531279377Simp cpsw_emac1: slave@48480300 { 1532279377Simp /* Filled in by U-Boot */ 1533279377Simp mac-address = [ 00 00 00 00 00 00 ]; 1534279377Simp }; 1535279377Simp 1536279377Simp phy_sel: cpsw-phy-sel@4a002554 { 1537279377Simp compatible = "ti,dra7xx-cpsw-phy-sel"; 1538279377Simp reg= <0x4a002554 0x4>; 1539279377Simp reg-names = "gmii-sel"; 1540279377Simp }; 1541279377Simp }; 1542279377Simp 1543279377Simp dcan1: can@481cc000 { 1544279377Simp compatible = "ti,dra7-d_can"; 1545279377Simp ti,hwmods = "dcan1"; 1546279377Simp reg = <0x4ae3c000 0x2000>; 1547295436Sandrew syscon-raminit = <&scm_conf 0x558 0>; 1548279377Simp interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1549279377Simp clocks = <&dcan1_sys_clk_mux>; 1550279377Simp status = "disabled"; 1551279377Simp }; 1552279377Simp 1553279377Simp dcan2: can@481d0000 { 1554279377Simp compatible = "ti,dra7-d_can"; 1555279377Simp ti,hwmods = "dcan2"; 1556279377Simp reg = <0x48480000 0x2000>; 1557295436Sandrew syscon-raminit = <&scm_conf 0x558 1>; 1558279377Simp interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1559279377Simp clocks = <&sys_clkin1>; 1560279377Simp status = "disabled"; 1561279377Simp }; 1562295436Sandrew 1563295436Sandrew dss: dss@58000000 { 1564295436Sandrew compatible = "ti,dra7-dss"; 1565295436Sandrew /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ 1566295436Sandrew /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ 1567295436Sandrew status = "disabled"; 1568295436Sandrew ti,hwmods = "dss_core"; 1569295436Sandrew /* CTRL_CORE_DSS_PLL_CONTROL */ 1570295436Sandrew syscon-pll-ctrl = <&scm_conf 0x538>; 1571295436Sandrew #address-cells = <1>; 1572295436Sandrew #size-cells = <1>; 1573295436Sandrew ranges; 1574295436Sandrew 1575295436Sandrew dispc@58001000 { 1576295436Sandrew compatible = "ti,dra7-dispc"; 1577295436Sandrew reg = <0x58001000 0x1000>; 1578295436Sandrew interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1579295436Sandrew ti,hwmods = "dss_dispc"; 1580295436Sandrew clocks = <&dss_dss_clk>; 1581295436Sandrew clock-names = "fck"; 1582295436Sandrew /* CTRL_CORE_SMA_SW_1 */ 1583295436Sandrew syscon-pol = <&scm_conf 0x534>; 1584295436Sandrew }; 1585295436Sandrew 1586295436Sandrew hdmi: encoder@58060000 { 1587295436Sandrew compatible = "ti,dra7-hdmi"; 1588295436Sandrew reg = <0x58040000 0x200>, 1589295436Sandrew <0x58040200 0x80>, 1590295436Sandrew <0x58040300 0x80>, 1591295436Sandrew <0x58060000 0x19000>; 1592295436Sandrew reg-names = "wp", "pll", "phy", "core"; 1593295436Sandrew interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1594295436Sandrew status = "disabled"; 1595295436Sandrew ti,hwmods = "dss_hdmi"; 1596295436Sandrew clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; 1597295436Sandrew clock-names = "fck", "sys_clk"; 1598295436Sandrew }; 1599295436Sandrew }; 1600279377Simp }; 1601295436Sandrew 1602295436Sandrew thermal_zones: thermal-zones { 1603295436Sandrew #include "omap4-cpu-thermal.dtsi" 1604295436Sandrew #include "omap5-gpu-thermal.dtsi" 1605295436Sandrew #include "omap5-core-thermal.dtsi" 1606295436Sandrew }; 1607295436Sandrew 1608279377Simp}; 1609279377Simp 1610295436Sandrew&cpu_thermal { 1611295436Sandrew polling-delay = <500>; /* milliseconds */ 1612295436Sandrew}; 1613295436Sandrew 1614279377Simp/include/ "dra7xx-clocks.dtsi" 1615