dove.dtsi revision 279377
1/include/ "skeleton.dtsi" 2 3#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 4 5/ { 6 compatible = "marvell,dove"; 7 model = "Marvell Armada 88AP510 SoC"; 8 interrupt-parent = <&intc>; 9 10 aliases { 11 gpio0 = &gpio0; 12 gpio1 = &gpio1; 13 gpio2 = &gpio2; 14 }; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "marvell,pj4a", "marvell,sheeva-v7"; 22 device_type = "cpu"; 23 next-level-cache = <&l2>; 24 reg = <0>; 25 }; 26 }; 27 28 l2: l2-cache { 29 compatible = "marvell,tauros2-cache"; 30 marvell,tauros2-cache-features = <0>; 31 }; 32 33 mbus { 34 compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus"; 35 #address-cells = <2>; 36 #size-cells = <1>; 37 controller = <&mbusc>; 38 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */ 39 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */ 40 41 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */ 42 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */ 43 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */ 44 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ 45 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ 46 47 pcie: pcie-controller { 48 compatible = "marvell,dove-pcie"; 49 status = "disabled"; 50 device_type = "pci"; 51 #address-cells = <3>; 52 #size-cells = <2>; 53 54 msi-parent = <&intc>; 55 bus-range = <0x00 0xff>; 56 57 ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000 58 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000 59 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */ 60 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */ 61 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ 62 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ 63 64 pcie-port@0 { 65 device_type = "pci"; 66 status = "disabled"; 67 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 68 reg = <0x0800 0 0 0 0>; 69 clocks = <&gate_clk 4>; 70 marvell,pcie-port = <0>; 71 72 #address-cells = <3>; 73 #size-cells = <2>; 74 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 75 0x81000000 0 0 0x81000000 0x1 0 1 0>; 76 77 #interrupt-cells = <1>; 78 interrupt-map-mask = <0 0 0 0>; 79 interrupt-map = <0 0 0 0 &intc 16>; 80 }; 81 82 pcie-port@1 { 83 device_type = "pci"; 84 status = "disabled"; 85 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; 86 reg = <0x1000 0 0 0 0>; 87 clocks = <&gate_clk 5>; 88 marvell,pcie-port = <1>; 89 90 #address-cells = <3>; 91 #size-cells = <2>; 92 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 93 0x81000000 0 0 0x81000000 0x2 0 1 0>; 94 95 #interrupt-cells = <1>; 96 interrupt-map-mask = <0 0 0 0>; 97 interrupt-map = <0 0 0 0 &intc 18>; 98 }; 99 }; 100 101 internal-regs { 102 compatible = "simple-bus"; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */ 106 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */ 107 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */ 108 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */ 109 110 spi0: spi-ctrl@10600 { 111 compatible = "marvell,orion-spi"; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 cell-index = <0>; 115 interrupts = <6>; 116 reg = <0x10600 0x28>; 117 clocks = <&core_clk 0>; 118 pinctrl-0 = <&pmx_spi0>; 119 pinctrl-names = "default"; 120 status = "disabled"; 121 }; 122 123 i2c0: i2c-ctrl@11000 { 124 compatible = "marvell,mv64xxx-i2c"; 125 reg = <0x11000 0x20>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 interrupts = <11>; 129 clock-frequency = <400000>; 130 timeout-ms = <1000>; 131 clocks = <&core_clk 0>; 132 status = "disabled"; 133 }; 134 135 uart0: serial@12000 { 136 compatible = "ns16550a"; 137 reg = <0x12000 0x100>; 138 reg-shift = <2>; 139 interrupts = <7>; 140 clocks = <&core_clk 0>; 141 status = "disabled"; 142 }; 143 144 uart1: serial@12100 { 145 compatible = "ns16550a"; 146 reg = <0x12100 0x100>; 147 reg-shift = <2>; 148 interrupts = <8>; 149 clocks = <&core_clk 0>; 150 pinctrl-0 = <&pmx_uart1>; 151 pinctrl-names = "default"; 152 status = "disabled"; 153 }; 154 155 uart2: serial@12200 { 156 compatible = "ns16550a"; 157 reg = <0x12000 0x100>; 158 reg-shift = <2>; 159 interrupts = <9>; 160 clocks = <&core_clk 0>; 161 status = "disabled"; 162 }; 163 164 uart3: serial@12300 { 165 compatible = "ns16550a"; 166 reg = <0x12100 0x100>; 167 reg-shift = <2>; 168 interrupts = <10>; 169 clocks = <&core_clk 0>; 170 status = "disabled"; 171 }; 172 173 spi1: spi-ctrl@14600 { 174 compatible = "marvell,orion-spi"; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 cell-index = <1>; 178 interrupts = <5>; 179 reg = <0x14600 0x28>; 180 clocks = <&core_clk 0>; 181 status = "disabled"; 182 }; 183 184 mbusc: mbus-ctrl@20000 { 185 compatible = "marvell,mbus-controller"; 186 reg = <0x20000 0x80>, <0x800100 0x8>; 187 }; 188 189 sysc: system-ctrl@20000 { 190 compatible = "marvell,orion-system-controller"; 191 reg = <0x20000 0x110>; 192 }; 193 194 bridge_intc: bridge-interrupt-ctrl@20110 { 195 compatible = "marvell,orion-bridge-intc"; 196 interrupt-controller; 197 #interrupt-cells = <1>; 198 reg = <0x20110 0x8>; 199 interrupts = <0>; 200 marvell,#interrupts = <5>; 201 }; 202 203 intc: main-interrupt-ctrl@20200 { 204 compatible = "marvell,orion-intc"; 205 interrupt-controller; 206 #interrupt-cells = <1>; 207 reg = <0x20200 0x10>, <0x20210 0x10>; 208 }; 209 210 timer: timer@20300 { 211 compatible = "marvell,orion-timer"; 212 reg = <0x20300 0x20>; 213 interrupt-parent = <&bridge_intc>; 214 interrupts = <1>, <2>; 215 clocks = <&core_clk 0>; 216 }; 217 218 watchdog@20300 { 219 compatible = "marvell,orion-wdt"; 220 reg = <0x20300 0x28>, <0x20108 0x4>; 221 interrupt-parent = <&bridge_intc>; 222 interrupts = <3>; 223 clocks = <&core_clk 0>; 224 }; 225 226 crypto: crypto-engine@30000 { 227 compatible = "marvell,orion-crypto"; 228 reg = <0x30000 0x10000>, 229 <0xffffe000 0x800>; 230 reg-names = "regs", "sram"; 231 interrupts = <31>; 232 clocks = <&gate_clk 15>; 233 status = "okay"; 234 }; 235 236 ehci0: usb-host@50000 { 237 compatible = "marvell,orion-ehci"; 238 reg = <0x50000 0x1000>; 239 interrupts = <24>; 240 clocks = <&gate_clk 0>; 241 status = "okay"; 242 }; 243 244 ehci1: usb-host@51000 { 245 compatible = "marvell,orion-ehci"; 246 reg = <0x51000 0x1000>; 247 interrupts = <25>; 248 clocks = <&gate_clk 1>; 249 status = "okay"; 250 }; 251 252 xor0: dma-engine@60800 { 253 compatible = "marvell,orion-xor"; 254 reg = <0x60800 0x100 255 0x60a00 0x100>; 256 clocks = <&gate_clk 23>; 257 status = "okay"; 258 259 channel0 { 260 interrupts = <39>; 261 dmacap,memcpy; 262 dmacap,xor; 263 }; 264 265 channel1 { 266 interrupts = <40>; 267 dmacap,memcpy; 268 dmacap,xor; 269 }; 270 }; 271 272 xor1: dma-engine@60900 { 273 compatible = "marvell,orion-xor"; 274 reg = <0x60900 0x100 275 0x60b00 0x100>; 276 clocks = <&gate_clk 24>; 277 status = "okay"; 278 279 channel0 { 280 interrupts = <42>; 281 dmacap,memcpy; 282 dmacap,xor; 283 }; 284 285 channel1 { 286 interrupts = <43>; 287 dmacap,memcpy; 288 dmacap,xor; 289 }; 290 }; 291 292 sdio1: sdio-host@90000 { 293 compatible = "marvell,dove-sdhci"; 294 reg = <0x90000 0x100>; 295 interrupts = <36>, <38>; 296 clocks = <&gate_clk 9>; 297 pinctrl-0 = <&pmx_sdio1>; 298 pinctrl-names = "default"; 299 status = "disabled"; 300 }; 301 302 eth: ethernet-ctrl@72000 { 303 compatible = "marvell,orion-eth"; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 reg = <0x72000 0x4000>; 307 clocks = <&gate_clk 2>; 308 marvell,tx-checksum-limit = <1600>; 309 status = "disabled"; 310 311 ethernet-port@0 { 312 compatible = "marvell,orion-eth-port"; 313 reg = <0>; 314 interrupts = <29>; 315 /* overwrite MAC address in bootloader */ 316 local-mac-address = [00 00 00 00 00 00]; 317 phy-handle = <ðphy>; 318 }; 319 }; 320 321 mdio: mdio-bus@72004 { 322 compatible = "marvell,orion-mdio"; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 reg = <0x72004 0x84>; 326 interrupts = <30>; 327 clocks = <&gate_clk 2>; 328 status = "disabled"; 329 330 ethphy: ethernet-phy { 331 /* set phy address in board file */ 332 }; 333 }; 334 335 sdio0: sdio-host@92000 { 336 compatible = "marvell,dove-sdhci"; 337 reg = <0x92000 0x100>; 338 interrupts = <35>, <37>; 339 clocks = <&gate_clk 8>; 340 pinctrl-0 = <&pmx_sdio0>; 341 pinctrl-names = "default"; 342 status = "disabled"; 343 }; 344 345 sata0: sata-host@a0000 { 346 compatible = "marvell,orion-sata"; 347 reg = <0xa0000 0x2400>; 348 interrupts = <62>; 349 clocks = <&gate_clk 3>; 350 phys = <&sata_phy0>; 351 phy-names = "port0"; 352 nr-ports = <1>; 353 status = "disabled"; 354 }; 355 356 sata_phy0: sata-phy@a2000 { 357 compatible = "marvell,mvebu-sata-phy"; 358 reg = <0xa2000 0x0334>; 359 clocks = <&gate_clk 3>; 360 clock-names = "sata"; 361 #phy-cells = <0>; 362 status = "ok"; 363 }; 364 365 audio0: audio-controller@b0000 { 366 compatible = "marvell,dove-audio"; 367 reg = <0xb0000 0x2210>; 368 interrupts = <19>, <20>; 369 clocks = <&gate_clk 12>; 370 clock-names = "internal"; 371 status = "disabled"; 372 }; 373 374 audio1: audio-controller@b4000 { 375 compatible = "marvell,dove-audio"; 376 reg = <0xb4000 0x2210>; 377 interrupts = <21>, <22>; 378 clocks = <&gate_clk 13>; 379 clock-names = "internal"; 380 status = "disabled"; 381 }; 382 383 thermal: thermal-diode@d001c { 384 compatible = "marvell,dove-thermal"; 385 reg = <0xd001c 0x0c>, <0xd005c 0x08>; 386 }; 387 388 gate_clk: clock-gating-ctrl@d0038 { 389 compatible = "marvell,dove-gating-clock"; 390 reg = <0xd0038 0x4>; 391 clocks = <&core_clk 0>; 392 #clock-cells = <1>; 393 }; 394 395 pinctrl: pin-ctrl@d0200 { 396 compatible = "marvell,dove-pinctrl"; 397 reg = <0xd0200 0x14>, 398 <0xd0440 0x04>; 399 clocks = <&gate_clk 22>; 400 401 pmx_gpio_0: pmx-gpio-0 { 402 marvell,pins = "mpp0"; 403 marvell,function = "gpio"; 404 }; 405 406 pmx_gpio_1: pmx-gpio-1 { 407 marvell,pins = "mpp1"; 408 marvell,function = "gpio"; 409 }; 410 411 pmx_gpio_2: pmx-gpio-2 { 412 marvell,pins = "mpp2"; 413 marvell,function = "gpio"; 414 }; 415 416 pmx_gpio_3: pmx-gpio-3 { 417 marvell,pins = "mpp3"; 418 marvell,function = "gpio"; 419 }; 420 421 pmx_gpio_4: pmx-gpio-4 { 422 marvell,pins = "mpp4"; 423 marvell,function = "gpio"; 424 }; 425 426 pmx_gpio_5: pmx-gpio-5 { 427 marvell,pins = "mpp5"; 428 marvell,function = "gpio"; 429 }; 430 431 pmx_gpio_6: pmx-gpio-6 { 432 marvell,pins = "mpp6"; 433 marvell,function = "gpio"; 434 }; 435 436 pmx_gpio_7: pmx-gpio-7 { 437 marvell,pins = "mpp7"; 438 marvell,function = "gpio"; 439 }; 440 441 pmx_gpio_8: pmx-gpio-8 { 442 marvell,pins = "mpp8"; 443 marvell,function = "gpio"; 444 }; 445 446 pmx_gpio_9: pmx-gpio-9 { 447 marvell,pins = "mpp9"; 448 marvell,function = "gpio"; 449 }; 450 451 pmx_gpio_10: pmx-gpio-10 { 452 marvell,pins = "mpp10"; 453 marvell,function = "gpio"; 454 }; 455 456 pmx_gpio_11: pmx-gpio-11 { 457 marvell,pins = "mpp11"; 458 marvell,function = "gpio"; 459 }; 460 461 pmx_gpio_12: pmx-gpio-12 { 462 marvell,pins = "mpp12"; 463 marvell,function = "gpio"; 464 }; 465 466 pmx_gpio_13: pmx-gpio-13 { 467 marvell,pins = "mpp13"; 468 marvell,function = "gpio"; 469 }; 470 471 pmx_audio1_extclk: pmx-audio1-extclk { 472 marvell,pins = "mpp13"; 473 marvell,function = "audio1"; 474 }; 475 476 pmx_gpio_14: pmx-gpio-14 { 477 marvell,pins = "mpp14"; 478 marvell,function = "gpio"; 479 }; 480 481 pmx_gpio_15: pmx-gpio-15 { 482 marvell,pins = "mpp15"; 483 marvell,function = "gpio"; 484 }; 485 486 pmx_gpio_16: pmx-gpio-16 { 487 marvell,pins = "mpp16"; 488 marvell,function = "gpio"; 489 }; 490 491 pmx_gpio_17: pmx-gpio-17 { 492 marvell,pins = "mpp17"; 493 marvell,function = "gpio"; 494 }; 495 496 pmx_gpio_18: pmx-gpio-18 { 497 marvell,pins = "mpp18"; 498 marvell,function = "gpio"; 499 }; 500 501 pmx_gpio_19: pmx-gpio-19 { 502 marvell,pins = "mpp19"; 503 marvell,function = "gpio"; 504 }; 505 506 pmx_gpio_20: pmx-gpio-20 { 507 marvell,pins = "mpp20"; 508 marvell,function = "gpio"; 509 }; 510 511 pmx_gpio_21: pmx-gpio-21 { 512 marvell,pins = "mpp21"; 513 marvell,function = "gpio"; 514 }; 515 516 pmx_camera: pmx-camera { 517 marvell,pins = "mpp_camera"; 518 marvell,function = "camera"; 519 }; 520 521 pmx_camera_gpio: pmx-camera-gpio { 522 marvell,pins = "mpp_camera"; 523 marvell,function = "gpio"; 524 }; 525 526 pmx_sdio0: pmx-sdio0 { 527 marvell,pins = "mpp_sdio0"; 528 marvell,function = "sdio0"; 529 }; 530 531 pmx_sdio0_gpio: pmx-sdio0-gpio { 532 marvell,pins = "mpp_sdio0"; 533 marvell,function = "gpio"; 534 }; 535 536 pmx_sdio1: pmx-sdio1 { 537 marvell,pins = "mpp_sdio1"; 538 marvell,function = "sdio1"; 539 }; 540 541 pmx_sdio1_gpio: pmx-sdio1-gpio { 542 marvell,pins = "mpp_sdio1"; 543 marvell,function = "gpio"; 544 }; 545 546 pmx_audio1_gpio: pmx-audio1-gpio { 547 marvell,pins = "mpp_audio1"; 548 marvell,function = "gpio"; 549 }; 550 551 pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo { 552 marvell,pins = "mpp_audio1"; 553 marvell,function = "i2s1/spdifo"; 554 }; 555 556 pmx_spi0: pmx-spi0 { 557 marvell,pins = "mpp_spi0"; 558 marvell,function = "spi0"; 559 }; 560 561 pmx_spi0_gpio: pmx-spi0-gpio { 562 marvell,pins = "mpp_spi0"; 563 marvell,function = "gpio"; 564 }; 565 566 pmx_uart1: pmx-uart1 { 567 marvell,pins = "mpp_uart1"; 568 marvell,function = "uart1"; 569 }; 570 571 pmx_uart1_gpio: pmx-uart1-gpio { 572 marvell,pins = "mpp_uart1"; 573 marvell,function = "gpio"; 574 }; 575 576 pmx_nand: pmx-nand { 577 marvell,pins = "mpp_nand"; 578 marvell,function = "nand"; 579 }; 580 581 pmx_nand_gpo: pmx-nand-gpo { 582 marvell,pins = "mpp_nand"; 583 marvell,function = "gpo"; 584 }; 585 }; 586 587 core_clk: core-clocks@d0214 { 588 compatible = "marvell,dove-core-clock"; 589 reg = <0xd0214 0x4>; 590 #clock-cells = <1>; 591 }; 592 593 gpio0: gpio-ctrl@d0400 { 594 compatible = "marvell,orion-gpio"; 595 #gpio-cells = <2>; 596 gpio-controller; 597 reg = <0xd0400 0x20>; 598 ngpios = <32>; 599 interrupt-controller; 600 #interrupt-cells = <2>; 601 interrupts = <12>, <13>, <14>, <60>; 602 }; 603 604 gpio1: gpio-ctrl@d0420 { 605 compatible = "marvell,orion-gpio"; 606 #gpio-cells = <2>; 607 gpio-controller; 608 reg = <0xd0420 0x20>; 609 ngpios = <32>; 610 interrupt-controller; 611 #interrupt-cells = <2>; 612 interrupts = <61>; 613 }; 614 615 rtc: real-time-clock@d8500 { 616 compatible = "marvell,orion-rtc"; 617 reg = <0xd8500 0x20>; 618 }; 619 620 gconf: global-config@e802c { 621 compatible = "marvell,dove-global-config", 622 "syscon"; 623 reg = <0xe802c 0x14>; 624 }; 625 626 gpio2: gpio-ctrl@e8400 { 627 compatible = "marvell,orion-gpio"; 628 #gpio-cells = <2>; 629 gpio-controller; 630 reg = <0xe8400 0x0c>; 631 ngpios = <8>; 632 }; 633 634 lcd1: lcd-controller@810000 { 635 compatible = "marvell,dove-lcd"; 636 reg = <0x810000 0x1000>; 637 interrupts = <46>; 638 status = "disabled"; 639 }; 640 641 lcd0: lcd-controller@820000 { 642 compatible = "marvell,dove-lcd"; 643 reg = <0x820000 0x1000>; 644 interrupts = <47>; 645 status = "disabled"; 646 }; 647 }; 648 }; 649}; 650