dm816x.dtsi revision 279385 
1/*
2 * This file is licensed under the terms of the GNU General Public License
3 * version 2.  This program is licensed "as is" without any warranty of any
4 * kind, whether express or implied.
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/pinctrl/omap.h>
9
10#include "skeleton.dtsi"
11
12/ {
13	compatible = "ti,dm816";
14	interrupt-parent = <&intc>;
15
16	aliases {
17		i2c0 = &i2c1;
18		i2c1 = &i2c2;
19		serial0 = &uart1;
20		serial1 = &uart2;
21		serial2 = &uart3;
22		ethernet0 = &eth0;
23		ethernet1 = &eth1;
24	};
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29		cpu@0 {
30			compatible = "arm,cortex-a8";
31			device_type = "cpu";
32			reg = <0>;
33		};
34	};
35
36	pmu {
37		compatible = "arm,cortex-a8-pmu";
38		interrupts = <3>;
39	};
40
41	/*
42	 * The soc node represents the soc top level view. It is used for IPs
43	 * that are not memory mapped in the MPU view or for the MPU itself.
44	 */
45	soc {
46		compatible = "ti,omap-infra";
47		mpu {
48			compatible = "ti,omap3-mpu";
49			ti,hwmods = "mpu";
50		};
51	};
52
53	/*
54	 * XXX: Use a flat representation of the dm816x interconnect.
55	 * The real dm816x interconnect network is quite complex. Since
56	 * it will not bring real advantage to represent that in DT
57	 * for the moment, just use a fake OCP bus entry to represent
58	 * the whole bus hierarchy.
59	 */
60	ocp {
61		compatible = "ti,omap3-l3-smx", "simple-bus";
62		reg = <0x44000000 0x10000>;
63		interrupts = <9 10>;
64		#address-cells = <1>;
65		#size-cells = <1>;
66		ranges;
67		ti,hwmods = "l3_main";
68
69		prcm: prcm@48180000 {
70			compatible = "ti,dm816-prcm";
71			reg = <0x48180000 0x4000>;
72
73			prcm_clocks: clocks {
74				#address-cells = <1>;
75				#size-cells = <0>;
76			};
77
78			prcm_clockdomains: clockdomains {
79			};
80		};
81
82		scrm: scrm@48140000 {
83			compatible = "ti,dm816-scrm", "simple-bus";
84			reg = <0x48140000 0x21000>;
85			#address-cells = <1>;
86			#size-cells = <1>;
87			ranges = <0 0x48140000 0x21000>;
88
89			dm816x_pinmux: pinmux@800 {
90				compatible = "pinctrl-single";
91				reg = <0x800 0x50a>;
92				#address-cells = <1>;
93				#size-cells = <0>;
94				pinctrl-single,register-width = <16>;
95				pinctrl-single,function-mask = <0xf>;
96			};
97
98			/* Device Configuration Registers */
99			scm_conf: syscon@600 {
100				compatible = "syscon";
101				reg = <0x600 0x110>;
102				#address-cells = <1>;
103				#size-cells = <1>;
104			};
105
106			scrm_clocks: clocks {
107				#address-cells = <1>;
108				#size-cells = <0>;
109			};
110
111			scrm_clockdomains: clockdomains {
112			};
113		};
114
115		edma: edma@49000000 {
116			compatible = "ti,edma3";
117			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
118			reg =   <0x49000000 0x10000>,
119			        <0x44e10f90 0x40>;
120			interrupts = <12 13 14>;
121			#dma-cells = <1>;
122		};
123
124		elm: elm@48080000 {
125			compatible = "ti,816-elm";
126			ti,hwmods = "elm";
127			reg = <0x48080000 0x2000>;
128			interrupts = <4>;
129		};
130
131		gpio1: gpio@48032000 {
132			compatible = "ti,omap3-gpio";
133			ti,hwmods = "gpio1";
134			reg = <0x48032000 0x1000>;
135			interrupts = <97>;
136		};
137
138		gpio2: gpio@4804c000 {
139			compatible = "ti,omap3-gpio";
140			ti,hwmods = "gpio2";
141			reg = <0x4804c000 0x1000>;
142			interrupts = <99>;
143		};
144
145		gpmc: gpmc@50000000 {
146			compatible = "ti,am3352-gpmc";
147			ti,hwmods = "gpmc";
148			reg = <0x50000000 0x2000>;
149			#address-cells = <2>;
150			#size-cells = <1>;
151			interrupts = <100>;
152			gpmc,num-cs = <6>;
153			gpmc,num-waitpins = <2>;
154		};
155
156		i2c1: i2c@48028000 {
157			compatible = "ti,omap4-i2c";
158			ti,hwmods = "i2c1";
159			reg = <0x48028000 0x1000>;
160			#address-cells = <1>;
161			#size-cells = <0>;
162			interrupts = <70>;
163			dmas = <&edma 58 &edma 59>;
164			dma-names = "tx", "rx";
165		};
166
167		i2c2: i2c@4802a000 {
168			compatible = "ti,omap4-i2c";
169			ti,hwmods = "i2c2";
170			reg = <0x4802a000 0x1000>;
171			#address-cells = <1>;
172			#size-cells = <0>;
173			interrupts = <71>;
174			dmas = <&edma 60 &edma 61>;
175			dma-names = "tx", "rx";
176		};
177
178		intc: interrupt-controller@48200000 {
179			compatible = "ti,dm816-intc";
180			interrupt-controller;
181			#interrupt-cells = <1>;
182			reg = <0x48200000 0x1000>;
183		};
184
185		mailbox: mailbox@480c8000 {
186			compatible = "ti,omap4-mailbox";
187			reg = <0x480c8000 0x2000>;
188			interrupts = <77>;
189			ti,hwmods = "mailbox";
190			ti,mbox-num-users = <4>;
191			ti,mbox-num-fifos = <12>;
192			mbox_dsp: mbox_dsp {
193				ti,mbox-tx = <3 0 0>;
194				ti,mbox-rx = <0 0 0>;
195			};
196		};
197
198		mdio: mdio@4a100800 {
199			compatible = "ti,davinci_mdio";
200			#address-cells = <1>;
201			#size-cells = <0>;
202			reg = <0x4a100800 0x100>;
203			ti,hwmods = "davinci_mdio";
204			bus_freq = <1000000>;
205			phy0: ethernet-phy@0 {
206				reg = <1>;
207			};
208			phy1: ethernet-phy@1 {
209				reg = <2>;
210			};
211		};
212
213		eth0: ethernet@4a100000 {
214			compatible = "ti,dm816-emac";
215			ti,hwmods = "emac0";
216			reg = <0x4a100000 0x800
217			       0x4a100900 0x3700>;
218			clocks = <&sysclk24_ck>;
219			syscon = <&scm_conf>;
220			ti,davinci-ctrl-reg-offset = <0>;
221			ti,davinci-ctrl-mod-reg-offset = <0x900>;
222			ti,davinci-ctrl-ram-offset = <0x2000>;
223			ti,davinci-ctrl-ram-size = <0x2000>;
224			interrupts = <40 41 42 43>;
225			phy-handle = <&phy0>;
226		};
227
228		eth1: ethernet@4a120000 {
229			compatible = "ti,dm816-emac";
230			ti,hwmods = "emac1";
231			reg = <0x4a120000 0x4000>;
232			clocks = <&sysclk24_ck>;
233			syscon = <&scm_conf>;
234			ti,davinci-ctrl-reg-offset = <0>;
235			ti,davinci-ctrl-mod-reg-offset = <0x900>;
236			ti,davinci-ctrl-ram-offset = <0x2000>;
237			ti,davinci-ctrl-ram-size = <0x2000>;
238			interrupts = <44 45 46 47>;
239			phy-handle = <&phy1>;
240		};
241
242		mcspi1: spi@48030000 {
243			compatible = "ti,omap4-mcspi";
244			reg = <0x48030000 0x1000>;
245			#address-cells = <1>;
246			#size-cells = <0>;
247			interrupts = <65>;
248			ti,spi-num-cs = <4>;
249			ti,hwmods = "mcspi1";
250			dmas = <&edma 16 &edma 17
251				&edma 18 &edma 19>;
252			dma-names = "tx0", "rx0", "tx1", "rx1";
253		};
254
255		mmc1: mmc@48060000 {
256			compatible = "ti,omap4-hsmmc";
257			reg = <0x48060000 0x11000>;
258			ti,hwmods = "mmc1";
259			interrupts = <64>;
260			dmas = <&edma 24 &edma 25>;
261			dma-names = "tx", "rx";
262		};
263
264		timer1: timer@4802e000 {
265			compatible = "ti,dm816-timer";
266			reg = <0x4802e000 0x2000>;
267			interrupts = <67>;
268			ti,hwmods = "timer1";
269			ti,timer-alwon;
270		};
271
272		timer2: timer@48040000 {
273			compatible = "ti,dm816-timer";
274			reg = <0x48040000 0x2000>;
275			interrupts = <68>;
276			ti,hwmods = "timer2";
277		};
278
279		timer3: timer@48042000 {
280			compatible = "ti,dm816-timer";
281			reg = <0x48042000 0x2000>;
282			interrupts = <69>;
283			ti,hwmods = "timer3";
284		};
285
286		timer4: timer@48044000 {
287			compatible = "ti,dm816-timer";
288			reg = <0x48044000 0x2000>;
289			interrupts = <92>;
290			ti,hwmods = "timer4";
291		};
292
293		timer5: timer@48046000 {
294			compatible = "ti,dm816-timer";
295			reg = <0x48046000 0x2000>;
296			interrupts = <93>;
297			ti,hwmods = "timer5";
298		};
299
300		timer6: timer@48048000 {
301			compatible = "ti,dm816-timer";
302			reg = <0x48048000 0x2000>;
303			interrupts = <94>;
304			ti,hwmods = "timer6";
305		};
306
307		timer7: timer@4804a000 {
308			compatible = "ti,dm816-timer";
309			reg = <0x4804a000 0x2000>;
310			interrupts = <95>;
311			ti,hwmods = "timer7";
312		};
313
314		uart1: uart@48020000 {
315			compatible = "ti,omap3-uart";
316			ti,hwmods = "uart1";
317			reg = <0x48020000 0x2000>;
318			clock-frequency = <48000000>;
319			interrupts = <72>;
320			dmas = <&edma 26 &edma 27>;
321			dma-names = "tx", "rx";
322		};
323
324		uart2: uart@48022000 {
325			compatible = "ti,omap3-uart";
326			ti,hwmods = "uart2";
327			reg = <0x48022000 0x2000>;
328			clock-frequency = <48000000>;
329			interrupts = <73>;
330			dmas = <&edma 28 &edma 29>;
331			dma-names = "tx", "rx";
332		};
333
334		uart3: uart@48024000 {
335			compatible = "ti,omap3-uart";
336			ti,hwmods = "uart3";
337			reg = <0x48024000 0x2000>;
338			clock-frequency = <48000000>;
339			interrupts = <74>;
340			dmas = <&edma 30 &edma 31>;
341			dma-names = "tx", "rx";
342		};
343
344		/* NOTE: USB needs a transceiver driver for phys to work */
345		usb: usb_otg_hs@47401000 {
346			compatible = "ti,am33xx-usb";
347			reg = <0x47401000 0x400000>;
348			ranges;
349			#address-cells = <1>;
350			#size-cells = <1>;
351			ti,hwmods = "usb_otg_hs";
352
353			usb0: usb@47401000 {
354				compatible = "ti,musb-am33xx";
355				reg = <0x47401400 0x400
356				       0x47401000 0x200>;
357				reg-names = "mc", "control";
358				interrupts = <18>;
359				interrupt-names = "mc";
360				dr_mode = "otg";
361				mentor,multipoint = <1>;
362				mentor,num-eps = <16>;
363				mentor,ram-bits = <12>;
364				mentor,power = <500>;
365			};
366
367			usb1: usb@47401800 {
368				compatible = "ti,musb-am33xx";
369				status = "disabled";
370				reg = <0x47401c00 0x400
371				       0x47401800 0x200>;
372				reg-names = "mc", "control";
373				interrupts = <19>;
374				interrupt-names = "mc";
375				dr_mode = "otg";
376				mentor,multipoint = <1>;
377				mentor,num-eps = <16>;
378				mentor,ram-bits = <12>;
379				mentor,power = <500>;
380			};
381		};
382
383		wd_timer2: wd_timer@480c2000 {
384			compatible = "ti,omap3-wdt";
385			ti,hwmods = "wd_timer";
386			reg = <0x480c2000 0x1000>;
387			interrupts = <0>;
388		};
389	};
390};
391
392#include "dm816x-clocks.dtsi"
393