1279377Simp/* 2279377Simp * This program is free software; you can redistribute it and/or modify 3279377Simp * it under the terms of the GNU General Public License version 2 as 4279377Simp * published by the Free Software Foundation. 5279377Simp */ 6279377Simp 7279377Simp&scrm { 8279377Simp main_fapll: main_fapll { 9279377Simp #clock-cells = <1>; 10279377Simp compatible = "ti,dm816-fapll-clock"; 11279377Simp reg = <0x400 0x40>; 12279377Simp clocks = <&sys_clkin_ck &sys_clkin_ck>; 13279377Simp clock-indices = <1>, <2>, <3>, <4>, <5>, 14279377Simp <6>, <7>; 15279377Simp clock-output-names = "main_pll_clk1", 16279377Simp "main_pll_clk2", 17279377Simp "main_pll_clk3", 18279377Simp "main_pll_clk4", 19279377Simp "main_pll_clk5", 20279377Simp "main_pll_clk6", 21279377Simp "main_pll_clk7"; 22279377Simp }; 23279377Simp 24279377Simp ddr_fapll: ddr_fapll { 25279377Simp #clock-cells = <1>; 26279377Simp compatible = "ti,dm816-fapll-clock"; 27279377Simp reg = <0x440 0x30>; 28279377Simp clocks = <&sys_clkin_ck &sys_clkin_ck>; 29279377Simp clock-indices = <1>, <2>, <3>, <4>; 30279377Simp clock-output-names = "ddr_pll_clk1", 31279377Simp "ddr_pll_clk2", 32279377Simp "ddr_pll_clk3", 33279377Simp "ddr_pll_clk4"; 34279377Simp }; 35279377Simp 36279377Simp video_fapll: video_fapll { 37279377Simp #clock-cells = <1>; 38279377Simp compatible = "ti,dm816-fapll-clock"; 39279377Simp reg = <0x470 0x30>; 40279377Simp clocks = <&sys_clkin_ck &sys_clkin_ck>; 41279377Simp clock-indices = <1>, <2>, <3>; 42279377Simp clock-output-names = "video_pll_clk1", 43279377Simp "video_pll_clk2", 44279377Simp "video_pll_clk3"; 45279377Simp }; 46279377Simp 47279377Simp audio_fapll: audio_fapll { 48279377Simp #clock-cells = <1>; 49279377Simp compatible = "ti,dm816-fapll-clock"; 50279377Simp reg = <0x4a0 0x30>; 51279377Simp clocks = <&main_fapll 7>, < &sys_clkin_ck>; 52279377Simp clock-indices = <1>, <2>, <3>, <4>, <5>; 53279377Simp clock-output-names = "audio_pll_clk1", 54279377Simp "audio_pll_clk2", 55279377Simp "audio_pll_clk3", 56279377Simp "audio_pll_clk4", 57279377Simp "audio_pll_clk5"; 58279377Simp }; 59279377Simp}; 60279377Simp 61279377Simp&scrm_clocks { 62279377Simp secure_32k_ck: secure_32k_ck { 63279377Simp #clock-cells = <0>; 64279377Simp compatible = "fixed-clock"; 65279377Simp clock-frequency = <32768>; 66279377Simp }; 67279377Simp 68279377Simp sys_32k_ck: sys_32k_ck { 69279377Simp #clock-cells = <0>; 70279377Simp compatible = "fixed-clock"; 71279377Simp clock-frequency = <32768>; 72279377Simp }; 73279377Simp 74279377Simp tclkin_ck: tclkin_ck { 75279377Simp #clock-cells = <0>; 76279377Simp compatible = "fixed-clock"; 77279377Simp clock-frequency = <32768>; 78279377Simp }; 79279377Simp 80279377Simp sys_clkin_ck: sys_clkin_ck { 81279377Simp #clock-cells = <0>; 82279377Simp compatible = "fixed-clock"; 83279377Simp clock-frequency = <27000000>; 84279377Simp }; 85279377Simp}; 86279377Simp 87279377Simp/* 0x48180000 */ 88279377Simp&prcm_clocks { 89279377Simp clkout_pre_ck: clkout_pre_ck { 90279377Simp #clock-cells = <0>; 91279377Simp compatible = "ti,mux-clock"; 92279377Simp clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1 93279377Simp &audio_fapll 1>; 94279377Simp reg = <0x100>; 95279377Simp }; 96279377Simp 97279377Simp clkout_div_ck: clkout_div_ck { 98279377Simp #clock-cells = <0>; 99279377Simp compatible = "ti,divider-clock"; 100279377Simp clocks = <&clkout_pre_ck>; 101279377Simp ti,bit-shift = <3>; 102279377Simp ti,max-div = <8>; 103279377Simp reg = <0x100>; 104279377Simp }; 105279377Simp 106279377Simp clkout_ck: clkout_ck { 107279377Simp #clock-cells = <0>; 108279377Simp compatible = "ti,gate-clock"; 109279377Simp clocks = <&clkout_div_ck>; 110279377Simp ti,bit-shift = <7>; 111279377Simp reg = <0x100>; 112279377Simp }; 113279377Simp 114279377Simp /* CM_DPLL clocks p1795 */ 115279377Simp sysclk1_ck: sysclk1_ck { 116279377Simp #clock-cells = <0>; 117279377Simp compatible = "ti,divider-clock"; 118279377Simp clocks = <&main_fapll 1>; 119279377Simp ti,max-div = <7>; 120279377Simp reg = <0x0300>; 121279377Simp }; 122279377Simp 123279377Simp sysclk2_ck: sysclk2_ck { 124279377Simp #clock-cells = <0>; 125279377Simp compatible = "ti,divider-clock"; 126279377Simp clocks = <&main_fapll 2>; 127279377Simp ti,max-div = <7>; 128279377Simp reg = <0x0304>; 129279377Simp }; 130279377Simp 131279377Simp sysclk3_ck: sysclk3_ck { 132279377Simp #clock-cells = <0>; 133279377Simp compatible = "ti,divider-clock"; 134279377Simp clocks = <&main_fapll 3>; 135279377Simp ti,max-div = <7>; 136279377Simp reg = <0x0308>; 137279377Simp }; 138279377Simp 139279377Simp sysclk4_ck: sysclk4_ck { 140279377Simp #clock-cells = <0>; 141279377Simp compatible = "ti,divider-clock"; 142279377Simp clocks = <&main_fapll 4>; 143279377Simp ti,max-div = <1>; 144279377Simp reg = <0x030c>; 145279377Simp }; 146279377Simp 147279377Simp sysclk5_ck: sysclk5_ck { 148279377Simp #clock-cells = <0>; 149279377Simp compatible = "ti,divider-clock"; 150279377Simp clocks = <&sysclk4_ck>; 151279377Simp ti,max-div = <1>; 152279377Simp reg = <0x0310>; 153279377Simp }; 154279377Simp 155279377Simp sysclk6_ck: sysclk6_ck { 156279377Simp #clock-cells = <0>; 157279377Simp compatible = "ti,divider-clock"; 158279377Simp clocks = <&main_fapll 4>; 159279377Simp ti,dividers = <2>, <4>; 160279377Simp reg = <0x0314>; 161279377Simp }; 162279377Simp 163279377Simp sysclk10_ck: sysclk10_ck { 164279377Simp #clock-cells = <0>; 165279377Simp compatible = "ti,divider-clock"; 166279377Simp clocks = <&ddr_fapll 2>; 167279377Simp ti,max-div = <7>; 168279377Simp reg = <0x0324>; 169279377Simp }; 170279377Simp 171279377Simp sysclk24_ck: sysclk24_ck { 172279377Simp #clock-cells = <0>; 173279377Simp compatible = "ti,divider-clock"; 174279377Simp clocks = <&main_fapll 5>; 175279377Simp ti,max-div = <7>; 176279377Simp reg = <0x03b4>; 177279377Simp }; 178279377Simp 179279377Simp mpu_ck: mpu_ck { 180279377Simp #clock-cells = <0>; 181279377Simp compatible = "ti,gate-clock"; 182279377Simp clocks = <&sysclk2_ck>; 183279377Simp ti,bit-shift = <1>; 184279377Simp reg = <0x15dc>; 185279377Simp }; 186279377Simp 187279377Simp audio_pll_a_ck: audio_pll_a_ck { 188279377Simp #clock-cells = <0>; 189279377Simp compatible = "ti,divider-clock"; 190279377Simp clocks = <&audio_fapll 1>; 191279377Simp ti,max-div = <7>; 192279377Simp reg = <0x035c>; 193279377Simp }; 194279377Simp 195279377Simp sysclk18_ck: sysclk18_ck { 196279377Simp #clock-cells = <0>; 197279377Simp compatible = "ti,mux-clock"; 198279377Simp clocks = <&sys_32k_ck>, <&audio_pll_a_ck>; 199279377Simp reg = <0x0378>; 200279377Simp }; 201279377Simp 202279377Simp timer1_fck: timer1_fck { 203279377Simp #clock-cells = <0>; 204279377Simp compatible = "ti,mux-clock"; 205279377Simp clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; 206279377Simp reg = <0x0390>; 207279377Simp }; 208279377Simp 209279377Simp timer2_fck: timer2_fck { 210279377Simp #clock-cells = <0>; 211279377Simp compatible = "ti,mux-clock"; 212279377Simp clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; 213279377Simp reg = <0x0394>; 214279377Simp }; 215279377Simp 216279377Simp timer3_fck: timer3_fck { 217279377Simp #clock-cells = <0>; 218279377Simp compatible = "ti,mux-clock"; 219279377Simp clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; 220279377Simp reg = <0x0398>; 221279377Simp }; 222279377Simp 223279377Simp timer4_fck: timer4_fck { 224279377Simp #clock-cells = <0>; 225279377Simp compatible = "ti,mux-clock"; 226279377Simp clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; 227279377Simp reg = <0x039c>; 228279377Simp }; 229279377Simp 230279377Simp timer5_fck: timer5_fck { 231279377Simp #clock-cells = <0>; 232279377Simp compatible = "ti,mux-clock"; 233279377Simp clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; 234279377Simp reg = <0x03a0>; 235279377Simp }; 236279377Simp 237279377Simp timer6_fck: timer6_fck { 238279377Simp #clock-cells = <0>; 239279377Simp compatible = "ti,mux-clock"; 240279377Simp clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; 241279377Simp reg = <0x03a4>; 242279377Simp }; 243279377Simp 244279377Simp timer7_fck: timer7_fck { 245279377Simp #clock-cells = <0>; 246279377Simp compatible = "ti,mux-clock"; 247279377Simp clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; 248279377Simp reg = <0x03a8>; 249279377Simp }; 250279377Simp}; 251