bcm63138.dtsi revision 279377
1/* 2 * Broadcom BCM63138 DSL SoCs Device Tree 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7 8#include "skeleton.dtsi" 9 10/ { 11 compatible = "brcm,bcm63138"; 12 model = "Broadcom BCM63138 DSL SoC"; 13 interrupt-parent = <&gic>; 14 15 aliases { 16 uart0 = &serial0; 17 uart1 = &serial1; 18 }; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a9"; 27 next-level-cache = <&L2>; 28 reg = <0>; 29 }; 30 31 cpu@1 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a9"; 34 next-level-cache = <&L2>; 35 reg = <1>; 36 }; 37 }; 38 39 clocks { 40 #address-cells = <1>; 41 #size-cells = <0>; 42 43 arm_timer_clk: arm_timer_clk { 44 #clock-cells = <0>; 45 compatible = "fixed-clock"; 46 clock-frequency = <500000000>; 47 }; 48 49 periph_clk: periph_clk { 50 #clock-cells = <0>; 51 compatible = "fixed-clock"; 52 clock-frequency = <50000000>; 53 clock-output-names = "periph"; 54 }; 55 }; 56 57 /* ARM bus */ 58 axi@80000000 { 59 compatible = "simple-bus"; 60 ranges = <0 0x80000000 0x784000>; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 64 L2: cache-controller@1d000 { 65 compatible = "arm,pl310-cache"; 66 reg = <0x1d000 0x1000>; 67 cache-unified; 68 cache-level = <2>; 69 cache-size = <524288>; 70 cache-sets = <1024>; 71 cache-line-size = <32>; 72 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; 73 }; 74 75 scu: scu@1e000 { 76 compatible = "arm,cortex-a9-scu"; 77 reg = <0x1e000 0x100>; 78 }; 79 80 gic: interrupt-controller@1e100 { 81 compatible = "arm,cortex-a9-gic"; 82 reg = <0x1f000 0x1000 83 0x1e100 0x100>; 84 #interrupt-cells = <3>; 85 #address-cells = <0>; 86 interrupt-controller; 87 }; 88 89 global_timer: timer@1e200 { 90 compatible = "arm,cortex-a9-global-timer"; 91 reg = <0x1e200 0x20>; 92 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 93 clocks = <&arm_timer_clk>; 94 }; 95 96 local_timer: local-timer@1e600 { 97 compatible = "arm,cortex-a9-twd-timer"; 98 reg = <0x1e600 0x20>; 99 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; 100 clocks = <&arm_timer_clk>; 101 }; 102 103 twd_watchdog: watchdog@1e620 { 104 compatible = "arm,cortex-a9-twd-wdt"; 105 reg = <0x1e620 0x20>; 106 interrupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>; 107 }; 108 }; 109 110 /* Legacy UBUS base */ 111 ubus@fffe8000 { 112 compatible = "simple-bus"; 113 #address-cells = <1>; 114 #size-cells = <1>; 115 ranges = <0 0xfffe8000 0x8100>; 116 117 serial0: serial@600 { 118 compatible = "brcm,bcm6345-uart"; 119 reg = <0x600 0x1b>; 120 interrupts = <GIC_SPI 32 0>; 121 clocks = <&periph_clk>; 122 clock-names = "periph"; 123 status = "disabled"; 124 }; 125 126 serial1: serial@620 { 127 compatible = "brcm,bcm6345-uart"; 128 reg = <0x620 0x1b>; 129 interrupts = <GIC_SPI 33 0>; 130 clocks = <&periph_clk>; 131 clock-names = "periph"; 132 status = "disabled"; 133 }; 134 }; 135}; 136