bcm5301x.dtsi revision 279377
1279377Simp/* 2279377Simp * Broadcom BCM470X / BCM5301X ARM platform code. 3279377Simp * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, 4279377Simp * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs 5279377Simp * 6279377Simp * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> 7279377Simp * 8279377Simp * Licensed under the GNU/GPL. See COPYING for details. 9279377Simp */ 10279377Simp 11279377Simp#include <dt-bindings/gpio/gpio.h> 12279377Simp#include <dt-bindings/input/input.h> 13279377Simp#include <dt-bindings/interrupt-controller/irq.h> 14279377Simp#include <dt-bindings/interrupt-controller/arm-gic.h> 15279377Simp#include "skeleton.dtsi" 16279377Simp 17279377Simp/ { 18279377Simp interrupt-parent = <&gic>; 19279377Simp 20279377Simp chipcommonA { 21279377Simp compatible = "simple-bus"; 22279377Simp ranges = <0x00000000 0x18000000 0x00001000>; 23279377Simp #address-cells = <1>; 24279377Simp #size-cells = <1>; 25279377Simp 26279377Simp uart0: serial@0300 { 27279377Simp compatible = "ns16550"; 28279377Simp reg = <0x0300 0x100>; 29279377Simp interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 30279377Simp clock-frequency = <100000000>; 31279377Simp status = "disabled"; 32279377Simp }; 33279377Simp 34279377Simp uart1: serial@0400 { 35279377Simp compatible = "ns16550"; 36279377Simp reg = <0x0400 0x100>; 37279377Simp interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 38279377Simp clock-frequency = <100000000>; 39279377Simp status = "disabled"; 40279377Simp }; 41279377Simp }; 42279377Simp 43279377Simp mpcore { 44279377Simp compatible = "simple-bus"; 45279377Simp ranges = <0x00000000 0x19020000 0x00003000>; 46279377Simp #address-cells = <1>; 47279377Simp #size-cells = <1>; 48279377Simp 49279377Simp scu@0000 { 50279377Simp compatible = "arm,cortex-a9-scu"; 51279377Simp reg = <0x0000 0x100>; 52279377Simp }; 53279377Simp 54279377Simp timer@0200 { 55279377Simp compatible = "arm,cortex-a9-global-timer"; 56279377Simp reg = <0x0200 0x100>; 57279377Simp interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 58279377Simp clocks = <&clk_periph>; 59279377Simp }; 60279377Simp 61279377Simp local-timer@0600 { 62279377Simp compatible = "arm,cortex-a9-twd-timer"; 63279377Simp reg = <0x0600 0x100>; 64279377Simp interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; 65279377Simp clocks = <&clk_periph>; 66279377Simp }; 67279377Simp 68279377Simp gic: interrupt-controller@1000 { 69279377Simp compatible = "arm,cortex-a9-gic"; 70279377Simp #interrupt-cells = <3>; 71279377Simp #address-cells = <0>; 72279377Simp interrupt-controller; 73279377Simp reg = <0x1000 0x1000>, 74279377Simp <0x0100 0x100>; 75279377Simp }; 76279377Simp 77279377Simp L2: cache-controller@2000 { 78279377Simp compatible = "arm,pl310-cache"; 79279377Simp reg = <0x2000 0x1000>; 80279377Simp cache-unified; 81279377Simp cache-level = <2>; 82279377Simp }; 83279377Simp }; 84279377Simp 85279377Simp clocks { 86279377Simp #address-cells = <1>; 87279377Simp #size-cells = <0>; 88279377Simp 89279377Simp /* As long as we do not have a real clock driver us this 90279377Simp * fixed clock */ 91279377Simp clk_periph: periph { 92279377Simp compatible = "fixed-clock"; 93279377Simp #clock-cells = <0>; 94279377Simp clock-frequency = <400000000>; 95279377Simp }; 96279377Simp }; 97279377Simp 98279377Simp axi@18000000 { 99279377Simp compatible = "brcm,bus-axi"; 100279377Simp reg = <0x18000000 0x1000>; 101279377Simp ranges = <0x00000000 0x18000000 0x00100000>; 102279377Simp #address-cells = <1>; 103279377Simp #size-cells = <1>; 104279377Simp 105279377Simp #interrupt-cells = <1>; 106279377Simp interrupt-map-mask = <0x000fffff 0xffff>; 107279377Simp interrupt-map = 108279377Simp /* ChipCommon */ 109279377Simp <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 110279377Simp 111279377Simp /* USB 2.0 Controller */ 112279377Simp <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 113279377Simp 114279377Simp /* USB 3.0 Controller */ 115279377Simp <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 116279377Simp 117279377Simp /* Ethernet Controller 0 */ 118279377Simp <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 119279377Simp 120279377Simp /* Ethernet Controller 1 */ 121279377Simp <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 122279377Simp 123279377Simp /* Ethernet Controller 2 */ 124279377Simp <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 125279377Simp 126279377Simp /* Ethernet Controller 3 */ 127279377Simp <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 128279377Simp 129279377Simp /* NAND Controller */ 130279377Simp <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 131279377Simp <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 132279377Simp <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 133279377Simp <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 134279377Simp <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 135279377Simp <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 136279377Simp <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 137279377Simp <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 138279377Simp 139279377Simp chipcommon: chipcommon@0 { 140279377Simp reg = <0x00000000 0x1000>; 141279377Simp 142279377Simp gpio-controller; 143279377Simp #gpio-cells = <2>; 144279377Simp }; 145279377Simp }; 146279377Simp}; 147