1295011Sandrew#include <dt-bindings/pinctrl/bcm2835.h> 2295011Sandrew#include <dt-bindings/clock/bcm2835.h> 3295011Sandrew#include "skeleton.dtsi" 4295011Sandrew 5295011Sandrew/* This include file covers the common peripherals and configuration between 6295011Sandrew * bcm2835 and bcm2836 implementations, leaving the CPU configuration to 7295011Sandrew * bcm2835.dtsi and bcm2836.dtsi. 8295011Sandrew */ 9295011Sandrew 10295011Sandrew/ { 11295011Sandrew compatible = "brcm,bcm2835"; 12295011Sandrew model = "BCM2835"; 13295011Sandrew interrupt-parent = <&intc>; 14295011Sandrew 15295011Sandrew chosen { 16295011Sandrew bootargs = "earlyprintk console=ttyAMA0"; 17295011Sandrew }; 18295011Sandrew 19295011Sandrew soc { 20295011Sandrew compatible = "simple-bus"; 21295011Sandrew #address-cells = <1>; 22295011Sandrew #size-cells = <1>; 23295011Sandrew 24295011Sandrew timer@7e003000 { 25295011Sandrew compatible = "brcm,bcm2835-system-timer"; 26295011Sandrew reg = <0x7e003000 0x1000>; 27295011Sandrew interrupts = <1 0>, <1 1>, <1 2>, <1 3>; 28295011Sandrew /* This could be a reference to BCM2835_CLOCK_TIMER, 29295011Sandrew * but we don't have the driver using the common clock 30295011Sandrew * support yet. 31295011Sandrew */ 32295011Sandrew clock-frequency = <1000000>; 33295011Sandrew }; 34295011Sandrew 35295011Sandrew dma: dma@7e007000 { 36295011Sandrew compatible = "brcm,bcm2835-dma"; 37295011Sandrew reg = <0x7e007000 0xf00>; 38295011Sandrew interrupts = <1 16>, 39295011Sandrew <1 17>, 40295011Sandrew <1 18>, 41295011Sandrew <1 19>, 42295011Sandrew <1 20>, 43295011Sandrew <1 21>, 44295011Sandrew <1 22>, 45295011Sandrew <1 23>, 46295011Sandrew <1 24>, 47295011Sandrew <1 25>, 48295011Sandrew <1 26>, 49295011Sandrew <1 27>, 50295011Sandrew <1 28>; 51295011Sandrew 52295011Sandrew #dma-cells = <1>; 53295011Sandrew brcm,dma-channel-mask = <0x7f35>; 54295011Sandrew }; 55295011Sandrew 56295011Sandrew intc: interrupt-controller@7e00b200 { 57295011Sandrew compatible = "brcm,bcm2835-armctrl-ic"; 58295011Sandrew reg = <0x7e00b200 0x200>; 59295011Sandrew interrupt-controller; 60295011Sandrew #interrupt-cells = <2>; 61295011Sandrew }; 62295011Sandrew 63295011Sandrew watchdog@7e100000 { 64295011Sandrew compatible = "brcm,bcm2835-pm-wdt"; 65295011Sandrew reg = <0x7e100000 0x28>; 66295011Sandrew }; 67295011Sandrew 68295011Sandrew clocks: cprman@7e101000 { 69295011Sandrew compatible = "brcm,bcm2835-cprman"; 70295011Sandrew #clock-cells = <1>; 71295011Sandrew reg = <0x7e101000 0x2000>; 72295011Sandrew 73295011Sandrew /* CPRMAN derives everything from the platform's 74295011Sandrew * oscillator. 75295011Sandrew */ 76295011Sandrew clocks = <&clk_osc>; 77295011Sandrew }; 78295011Sandrew 79295011Sandrew rng@7e104000 { 80295011Sandrew compatible = "brcm,bcm2835-rng"; 81295011Sandrew reg = <0x7e104000 0x10>; 82295011Sandrew }; 83295011Sandrew 84295011Sandrew mailbox: mailbox@7e00b800 { 85295011Sandrew compatible = "brcm,bcm2835-mbox"; 86295011Sandrew reg = <0x7e00b880 0x40>; 87295011Sandrew interrupts = <0 1>; 88295011Sandrew #mbox-cells = <0>; 89295011Sandrew }; 90295011Sandrew 91295011Sandrew gpio: gpio@7e200000 { 92295011Sandrew compatible = "brcm,bcm2835-gpio"; 93295011Sandrew reg = <0x7e200000 0xb4>; 94295011Sandrew /* 95295011Sandrew * The GPIO IP block is designed for 3 banks of GPIOs. 96295011Sandrew * Each bank has a GPIO interrupt for itself. 97295011Sandrew * There is an overall "any bank" interrupt. 98295011Sandrew * In order, these are GIC interrupts 17, 18, 19, 20. 99295011Sandrew * Since the BCM2835 only has 2 banks, the 2nd bank 100295011Sandrew * interrupt output appears to be mirrored onto the 101295011Sandrew * 3rd bank's interrupt signal. 102295011Sandrew * So, a bank0 interrupt shows up on 17, 20, and 103295011Sandrew * a bank1 interrupt shows up on 18, 19, 20! 104295011Sandrew */ 105295011Sandrew interrupts = <2 17>, <2 18>, <2 19>, <2 20>; 106295011Sandrew 107295011Sandrew gpio-controller; 108295011Sandrew #gpio-cells = <2>; 109295011Sandrew 110295011Sandrew interrupt-controller; 111295011Sandrew #interrupt-cells = <2>; 112295011Sandrew }; 113295011Sandrew 114295011Sandrew uart0: uart@7e201000 { 115295011Sandrew compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; 116295011Sandrew reg = <0x7e201000 0x1000>; 117295011Sandrew interrupts = <2 25>; 118295011Sandrew clocks = <&clocks BCM2835_CLOCK_UART>, 119295011Sandrew <&clocks BCM2835_CLOCK_VPU>; 120295011Sandrew clock-names = "uartclk", "apb_pclk"; 121295011Sandrew arm,primecell-periphid = <0x00241011>; 122295011Sandrew }; 123295011Sandrew 124295011Sandrew i2s: i2s@7e203000 { 125295011Sandrew compatible = "brcm,bcm2835-i2s"; 126295011Sandrew reg = <0x7e203000 0x20>, 127295011Sandrew <0x7e101098 0x02>; 128295011Sandrew 129295011Sandrew dmas = <&dma 2>, 130295011Sandrew <&dma 3>; 131295011Sandrew dma-names = "tx", "rx"; 132295011Sandrew status = "disabled"; 133295011Sandrew }; 134295011Sandrew 135295011Sandrew spi: spi@7e204000 { 136295011Sandrew compatible = "brcm,bcm2835-spi"; 137295011Sandrew reg = <0x7e204000 0x1000>; 138295011Sandrew interrupts = <2 22>; 139295011Sandrew clocks = <&clocks BCM2835_CLOCK_VPU>; 140295011Sandrew #address-cells = <1>; 141295011Sandrew #size-cells = <0>; 142295011Sandrew status = "disabled"; 143295011Sandrew }; 144295011Sandrew 145295011Sandrew i2c0: i2c@7e205000 { 146295011Sandrew compatible = "brcm,bcm2835-i2c"; 147295011Sandrew reg = <0x7e205000 0x1000>; 148295011Sandrew interrupts = <2 21>; 149295011Sandrew clocks = <&clocks BCM2835_CLOCK_VPU>; 150295011Sandrew #address-cells = <1>; 151295011Sandrew #size-cells = <0>; 152295011Sandrew status = "disabled"; 153295011Sandrew }; 154295011Sandrew 155295011Sandrew aux: aux@0x7e215000 { 156295011Sandrew compatible = "brcm,bcm2835-aux"; 157295011Sandrew #clock-cells = <1>; 158295011Sandrew reg = <0x7e215000 0x8>; 159295011Sandrew clocks = <&clocks BCM2835_CLOCK_VPU>; 160295011Sandrew }; 161295011Sandrew 162295011Sandrew sdhci: sdhci@7e300000 { 163295011Sandrew compatible = "brcm,bcm2835-sdhci"; 164295011Sandrew reg = <0x7e300000 0x100>; 165295011Sandrew interrupts = <2 30>; 166295011Sandrew clocks = <&clocks BCM2835_CLOCK_EMMC>; 167295011Sandrew status = "disabled"; 168295011Sandrew }; 169295011Sandrew 170295011Sandrew i2c1: i2c@7e804000 { 171295011Sandrew compatible = "brcm,bcm2835-i2c"; 172295011Sandrew reg = <0x7e804000 0x1000>; 173295011Sandrew interrupts = <2 21>; 174295011Sandrew clocks = <&clocks BCM2835_CLOCK_VPU>; 175295011Sandrew #address-cells = <1>; 176295011Sandrew #size-cells = <0>; 177295011Sandrew status = "disabled"; 178295011Sandrew }; 179295011Sandrew 180295011Sandrew i2c2: i2c@7e805000 { 181295011Sandrew compatible = "brcm,bcm2835-i2c"; 182295011Sandrew reg = <0x7e805000 0x1000>; 183295011Sandrew interrupts = <2 21>; 184295011Sandrew clocks = <&clocks BCM2835_CLOCK_VPU>; 185295011Sandrew #address-cells = <1>; 186295011Sandrew #size-cells = <0>; 187295011Sandrew status = "disabled"; 188295011Sandrew }; 189295011Sandrew 190295011Sandrew usb@7e980000 { 191295011Sandrew compatible = "brcm,bcm2835-usb"; 192295011Sandrew reg = <0x7e980000 0x10000>; 193295011Sandrew interrupts = <1 9>; 194295011Sandrew }; 195295011Sandrew }; 196295011Sandrew 197295011Sandrew clocks { 198295011Sandrew compatible = "simple-bus"; 199295011Sandrew #address-cells = <1>; 200295011Sandrew #size-cells = <0>; 201295011Sandrew 202295011Sandrew /* The oscillator is the root of the clock tree. */ 203295011Sandrew clk_osc: clock@3 { 204295011Sandrew compatible = "fixed-clock"; 205295011Sandrew reg = <3>; 206295011Sandrew #clock-cells = <0>; 207295011Sandrew clock-output-names = "osc"; 208295011Sandrew clock-frequency = <19200000>; 209295011Sandrew }; 210295011Sandrew 211295011Sandrew }; 212295011Sandrew}; 213