armada-xp.dtsi revision 279385
1/* 2 * Device Tree Include file for Marvell Armada XP family SoC 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Lior Amsalem <alior@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * Ben Dooks <ben.dooks@codethink.co.uk> 10 * 11 * This file is dual-licensed: you can use it either under the terms 12 * of the GPL or the X11 license, at your option. Note that this dual 13 * licensing only applies to this file, and not this project as a 14 * whole. 15 * 16 * a) This file is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of the 19 * License, or (at your option) any later version. 20 * 21 * This file is distributed in the hope that it will be useful 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * Or, alternatively 27 * 28 * b) Permission is hereby granted, free of charge, to any person 29 * obtaining a copy of this software and associated documentation 30 * files (the "Software"), to deal in the Software without 31 * restriction, including without limitation the rights to use 32 * copy, modify, merge, publish, distribute, sublicense, and/or 33 * sell copies of the Software, and to permit persons to whom the 34 * Software is furnished to do so, subject to the following 35 * conditions: 36 * 37 * The above copyright notice and this permission notice shall be 38 * included in all copies or substantial portions of the Software. 39 * 40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47 * OTHER DEALINGS IN THE SOFTWARE. 48 * 49 * Contains definitions specific to the Armada XP SoC that are not 50 * common to all Armada SoCs. 51 */ 52 53#include "armada-370-xp.dtsi" 54 55/ { 56 model = "Marvell Armada XP family SoC"; 57 compatible = "marvell,armadaxp", "marvell,armada-370-xp"; 58 59 aliases { 60 eth2 = ð2; 61 }; 62 63 soc { 64 compatible = "marvell,armadaxp-mbus", "simple-bus"; 65 66 bootrom { 67 compatible = "marvell,bootrom"; 68 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; 69 }; 70 71 internal-regs { 72 sdramc@1400 { 73 compatible = "marvell,armada-xp-sdram-controller"; 74 reg = <0x1400 0x500>; 75 }; 76 77 L2: l2-cache { 78 compatible = "marvell,aurora-system-cache"; 79 reg = <0x08000 0x1000>; 80 cache-id-part = <0x100>; 81 cache-unified; 82 wt-override; 83 }; 84 85 spi0: spi@10600 { 86 pinctrl-0 = <&spi0_pins>; 87 pinctrl-names = "default"; 88 }; 89 90 i2c0: i2c@11000 { 91 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; 92 reg = <0x11000 0x100>; 93 }; 94 95 i2c1: i2c@11100 { 96 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; 97 reg = <0x11100 0x100>; 98 }; 99 100 uart2: serial@12200 { 101 compatible = "snps,dw-apb-uart"; 102 pinctrl-0 = <&uart2_pins>; 103 pinctrl-names = "default"; 104 reg = <0x12200 0x100>; 105 reg-shift = <2>; 106 interrupts = <43>; 107 reg-io-width = <1>; 108 clocks = <&coreclk 0>; 109 status = "disabled"; 110 }; 111 112 uart3: serial@12300 { 113 compatible = "snps,dw-apb-uart"; 114 pinctrl-0 = <&uart3_pins>; 115 pinctrl-names = "default"; 116 reg = <0x12300 0x100>; 117 reg-shift = <2>; 118 interrupts = <44>; 119 reg-io-width = <1>; 120 clocks = <&coreclk 0>; 121 status = "disabled"; 122 }; 123 124 system-controller@18200 { 125 compatible = "marvell,armada-370-xp-system-controller"; 126 reg = <0x18200 0x500>; 127 }; 128 129 gateclk: clock-gating-control@18220 { 130 compatible = "marvell,armada-xp-gating-clock"; 131 reg = <0x18220 0x4>; 132 clocks = <&coreclk 0>; 133 #clock-cells = <1>; 134 }; 135 136 coreclk: mvebu-sar@18230 { 137 compatible = "marvell,armada-xp-core-clock"; 138 reg = <0x18230 0x08>; 139 #clock-cells = <1>; 140 }; 141 142 thermal@182b0 { 143 compatible = "marvell,armadaxp-thermal"; 144 reg = <0x182b0 0x4 145 0x184d0 0x4>; 146 status = "okay"; 147 }; 148 149 cpuclk: clock-complex@18700 { 150 #clock-cells = <1>; 151 compatible = "marvell,armada-xp-cpu-clock"; 152 reg = <0x18700 0xA0>, <0x1c054 0x10>; 153 clocks = <&coreclk 1>; 154 }; 155 156 interrupt-controller@20000 { 157 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 158 }; 159 160 timer@20300 { 161 compatible = "marvell,armada-xp-timer"; 162 clocks = <&coreclk 2>, <&refclk>; 163 clock-names = "nbclk", "fixed"; 164 }; 165 166 watchdog@20300 { 167 compatible = "marvell,armada-xp-wdt"; 168 clocks = <&coreclk 2>, <&refclk>; 169 clock-names = "nbclk", "fixed"; 170 }; 171 172 cpurst@20800 { 173 compatible = "marvell,armada-370-cpu-reset"; 174 reg = <0x20800 0x20>; 175 }; 176 177 eth2: ethernet@30000 { 178 compatible = "marvell,armada-370-neta"; 179 reg = <0x30000 0x4000>; 180 interrupts = <12>; 181 clocks = <&gateclk 2>; 182 status = "disabled"; 183 }; 184 185 usb@50000 { 186 clocks = <&gateclk 18>; 187 }; 188 189 usb@51000 { 190 clocks = <&gateclk 19>; 191 }; 192 193 usb@52000 { 194 compatible = "marvell,orion-ehci"; 195 reg = <0x52000 0x500>; 196 interrupts = <47>; 197 clocks = <&gateclk 20>; 198 status = "disabled"; 199 }; 200 201 xor@60900 { 202 compatible = "marvell,orion-xor"; 203 reg = <0x60900 0x100 204 0x60b00 0x100>; 205 clocks = <&gateclk 22>; 206 status = "okay"; 207 208 xor10 { 209 interrupts = <51>; 210 dmacap,memcpy; 211 dmacap,xor; 212 }; 213 xor11 { 214 interrupts = <52>; 215 dmacap,memcpy; 216 dmacap,xor; 217 dmacap,memset; 218 }; 219 }; 220 221 xor@f0900 { 222 compatible = "marvell,orion-xor"; 223 reg = <0xF0900 0x100 224 0xF0B00 0x100>; 225 clocks = <&gateclk 28>; 226 status = "okay"; 227 228 xor00 { 229 interrupts = <94>; 230 dmacap,memcpy; 231 dmacap,xor; 232 }; 233 xor01 { 234 interrupts = <95>; 235 dmacap,memcpy; 236 dmacap,xor; 237 dmacap,memset; 238 }; 239 }; 240 }; 241 }; 242 243 clocks { 244 /* 25 MHz reference crystal */ 245 refclk: oscillator { 246 compatible = "fixed-clock"; 247 #clock-cells = <0>; 248 clock-frequency = <25000000>; 249 }; 250 }; 251}; 252 253&pinctrl { 254 ge0_gmii_pins: ge0-gmii-pins { 255 marvell,pins = 256 "mpp0", "mpp1", "mpp2", "mpp3", 257 "mpp4", "mpp5", "mpp6", "mpp7", 258 "mpp8", "mpp9", "mpp10", "mpp11", 259 "mpp12", "mpp13", "mpp14", "mpp15", 260 "mpp16", "mpp17", "mpp18", "mpp19", 261 "mpp20", "mpp21", "mpp22", "mpp23"; 262 marvell,function = "ge0"; 263 }; 264 265 ge0_rgmii_pins: ge0-rgmii-pins { 266 marvell,pins = 267 "mpp0", "mpp1", "mpp2", "mpp3", 268 "mpp4", "mpp5", "mpp6", "mpp7", 269 "mpp8", "mpp9", "mpp10", "mpp11"; 270 marvell,function = "ge0"; 271 }; 272 273 ge1_rgmii_pins: ge1-rgmii-pins { 274 marvell,pins = 275 "mpp12", "mpp13", "mpp14", "mpp15", 276 "mpp16", "mpp17", "mpp18", "mpp19", 277 "mpp20", "mpp21", "mpp22", "mpp23"; 278 marvell,function = "ge1"; 279 }; 280 281 sdio_pins: sdio-pins { 282 marvell,pins = "mpp30", "mpp31", "mpp32", 283 "mpp33", "mpp34", "mpp35"; 284 marvell,function = "sd0"; 285 }; 286 287 spi0_pins: spi0-pins { 288 marvell,pins = "mpp36", "mpp37", 289 "mpp38", "mpp39"; 290 marvell,function = "spi"; 291 }; 292 293 uart2_pins: uart2-pins { 294 marvell,pins = "mpp42", "mpp43"; 295 marvell,function = "uart2"; 296 }; 297 298 uart3_pins: uart3-pins { 299 marvell,pins = "mpp44", "mpp45"; 300 marvell,function = "uart3"; 301 }; 302}; 303