1279377Simp/* 2279377Simp * Device Tree Include file for Marvell Armada XP family SoC 3279377Simp * 4279377Simp * Copyright (C) 2012 Marvell 5279377Simp * 6279377Simp * Lior Amsalem <alior@marvell.com> 7279377Simp * Gregory CLEMENT <gregory.clement@free-electrons.com> 8279377Simp * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9279377Simp * Ben Dooks <ben.dooks@codethink.co.uk> 10279377Simp * 11279377Simp * This file is dual-licensed: you can use it either under the terms 12279377Simp * of the GPL or the X11 license, at your option. Note that this dual 13279377Simp * licensing only applies to this file, and not this project as a 14279377Simp * whole. 15279377Simp * 16279377Simp * a) This file is free software; you can redistribute it and/or 17279377Simp * modify it under the terms of the GNU General Public License as 18279377Simp * published by the Free Software Foundation; either version 2 of the 19279377Simp * License, or (at your option) any later version. 20279377Simp * 21279377Simp * This file is distributed in the hope that it will be useful 22279377Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 23279377Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24279377Simp * GNU General Public License for more details. 25279377Simp * 26279377Simp * Or, alternatively 27279377Simp * 28279377Simp * b) Permission is hereby granted, free of charge, to any person 29279377Simp * obtaining a copy of this software and associated documentation 30279377Simp * files (the "Software"), to deal in the Software without 31279377Simp * restriction, including without limitation the rights to use 32279377Simp * copy, modify, merge, publish, distribute, sublicense, and/or 33279377Simp * sell copies of the Software, and to permit persons to whom the 34279377Simp * Software is furnished to do so, subject to the following 35279377Simp * conditions: 36279377Simp * 37279377Simp * The above copyright notice and this permission notice shall be 38279377Simp * included in all copies or substantial portions of the Software. 39279377Simp * 40279377Simp * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 41279377Simp * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42279377Simp * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43279377Simp * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44279377Simp * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 45279377Simp * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46279377Simp * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47279377Simp * OTHER DEALINGS IN THE SOFTWARE. 48279377Simp * 49279377Simp * Contains definitions specific to the Armada XP SoC that are not 50279377Simp * common to all Armada SoCs. 51279377Simp */ 52279377Simp 53279377Simp#include "armada-370-xp.dtsi" 54279377Simp 55279377Simp/ { 56279377Simp model = "Marvell Armada XP family SoC"; 57279377Simp compatible = "marvell,armadaxp", "marvell,armada-370-xp"; 58279377Simp 59279377Simp aliases { 60295436Sandrew serial2 = &uart2; 61295436Sandrew serial3 = &uart3; 62279377Simp }; 63279377Simp 64279377Simp soc { 65279377Simp compatible = "marvell,armadaxp-mbus", "simple-bus"; 66279377Simp 67279377Simp bootrom { 68279377Simp compatible = "marvell,bootrom"; 69279377Simp reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; 70279377Simp }; 71279377Simp 72279377Simp internal-regs { 73279377Simp sdramc@1400 { 74279377Simp compatible = "marvell,armada-xp-sdram-controller"; 75279377Simp reg = <0x1400 0x500>; 76279377Simp }; 77279377Simp 78279377Simp L2: l2-cache { 79279377Simp compatible = "marvell,aurora-system-cache"; 80279377Simp reg = <0x08000 0x1000>; 81279377Simp cache-id-part = <0x100>; 82295436Sandrew cache-level = <2>; 83279377Simp cache-unified; 84279377Simp wt-override; 85279377Simp }; 86279377Simp 87279377Simp spi0: spi@10600 { 88295436Sandrew compatible = "marvell,armada-xp-spi", 89295436Sandrew "marvell,orion-spi"; 90279377Simp pinctrl-0 = <&spi0_pins>; 91279377Simp pinctrl-names = "default"; 92279377Simp }; 93279377Simp 94295436Sandrew spi1: spi@10680 { 95295436Sandrew compatible = "marvell,armada-xp-spi", 96295436Sandrew "marvell,orion-spi"; 97295436Sandrew }; 98295436Sandrew 99295436Sandrew 100279377Simp i2c0: i2c@11000 { 101279377Simp compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; 102279377Simp reg = <0x11000 0x100>; 103279377Simp }; 104279377Simp 105279377Simp i2c1: i2c@11100 { 106279377Simp compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; 107279377Simp reg = <0x11100 0x100>; 108279377Simp }; 109279377Simp 110279377Simp uart2: serial@12200 { 111279377Simp compatible = "snps,dw-apb-uart"; 112279377Simp pinctrl-0 = <&uart2_pins>; 113279377Simp pinctrl-names = "default"; 114279377Simp reg = <0x12200 0x100>; 115279377Simp reg-shift = <2>; 116279377Simp interrupts = <43>; 117279377Simp reg-io-width = <1>; 118279377Simp clocks = <&coreclk 0>; 119279377Simp status = "disabled"; 120279377Simp }; 121279377Simp 122279377Simp uart3: serial@12300 { 123279377Simp compatible = "snps,dw-apb-uart"; 124279377Simp pinctrl-0 = <&uart3_pins>; 125279377Simp pinctrl-names = "default"; 126279377Simp reg = <0x12300 0x100>; 127279377Simp reg-shift = <2>; 128279377Simp interrupts = <44>; 129279377Simp reg-io-width = <1>; 130279377Simp clocks = <&coreclk 0>; 131279377Simp status = "disabled"; 132279377Simp }; 133279377Simp 134279377Simp system-controller@18200 { 135279377Simp compatible = "marvell,armada-370-xp-system-controller"; 136279377Simp reg = <0x18200 0x500>; 137279377Simp }; 138279377Simp 139279377Simp gateclk: clock-gating-control@18220 { 140279377Simp compatible = "marvell,armada-xp-gating-clock"; 141279377Simp reg = <0x18220 0x4>; 142279377Simp clocks = <&coreclk 0>; 143279377Simp #clock-cells = <1>; 144279377Simp }; 145279377Simp 146279377Simp coreclk: mvebu-sar@18230 { 147279377Simp compatible = "marvell,armada-xp-core-clock"; 148279377Simp reg = <0x18230 0x08>; 149279377Simp #clock-cells = <1>; 150279377Simp }; 151279377Simp 152279377Simp thermal@182b0 { 153279377Simp compatible = "marvell,armadaxp-thermal"; 154279377Simp reg = <0x182b0 0x4 155279377Simp 0x184d0 0x4>; 156279377Simp status = "okay"; 157279377Simp }; 158279377Simp 159279377Simp cpuclk: clock-complex@18700 { 160279377Simp #clock-cells = <1>; 161279377Simp compatible = "marvell,armada-xp-cpu-clock"; 162295436Sandrew reg = <0x18700 0x24>, <0x1c054 0x10>; 163279377Simp clocks = <&coreclk 1>; 164279377Simp }; 165279377Simp 166295436Sandrew interrupt-controller@20a00 { 167279377Simp reg = <0x20a00 0x2d0>, <0x21070 0x58>; 168279377Simp }; 169279377Simp 170279377Simp timer@20300 { 171279377Simp compatible = "marvell,armada-xp-timer"; 172279377Simp clocks = <&coreclk 2>, <&refclk>; 173279377Simp clock-names = "nbclk", "fixed"; 174279377Simp }; 175279377Simp 176279377Simp watchdog@20300 { 177279377Simp compatible = "marvell,armada-xp-wdt"; 178279377Simp clocks = <&coreclk 2>, <&refclk>; 179279377Simp clock-names = "nbclk", "fixed"; 180279377Simp }; 181279377Simp 182279377Simp cpurst@20800 { 183279377Simp compatible = "marvell,armada-370-cpu-reset"; 184279377Simp reg = <0x20800 0x20>; 185279377Simp }; 186279377Simp 187295436Sandrew cpu-config@21000 { 188295436Sandrew compatible = "marvell,armada-xp-cpu-config"; 189295436Sandrew reg = <0x21000 0x8>; 190295436Sandrew }; 191295436Sandrew 192279377Simp eth2: ethernet@30000 { 193295436Sandrew compatible = "marvell,armada-xp-neta"; 194279377Simp reg = <0x30000 0x4000>; 195279377Simp interrupts = <12>; 196279377Simp clocks = <&gateclk 2>; 197279377Simp status = "disabled"; 198279377Simp }; 199279377Simp 200279377Simp usb@50000 { 201279377Simp clocks = <&gateclk 18>; 202279377Simp }; 203279377Simp 204279377Simp usb@51000 { 205279377Simp clocks = <&gateclk 19>; 206279377Simp }; 207279377Simp 208279377Simp usb@52000 { 209279377Simp compatible = "marvell,orion-ehci"; 210279377Simp reg = <0x52000 0x500>; 211279377Simp interrupts = <47>; 212279377Simp clocks = <&gateclk 20>; 213279377Simp status = "disabled"; 214279377Simp }; 215279377Simp 216279377Simp xor@60900 { 217279377Simp compatible = "marvell,orion-xor"; 218279377Simp reg = <0x60900 0x100 219279377Simp 0x60b00 0x100>; 220279377Simp clocks = <&gateclk 22>; 221279377Simp status = "okay"; 222279377Simp 223279377Simp xor10 { 224279377Simp interrupts = <51>; 225279377Simp dmacap,memcpy; 226279377Simp dmacap,xor; 227279377Simp }; 228279377Simp xor11 { 229279377Simp interrupts = <52>; 230279377Simp dmacap,memcpy; 231279377Simp dmacap,xor; 232279377Simp dmacap,memset; 233279377Simp }; 234279377Simp }; 235279377Simp 236295436Sandrew ethernet@70000 { 237295436Sandrew compatible = "marvell,armada-xp-neta"; 238295436Sandrew }; 239295436Sandrew 240295436Sandrew ethernet@74000 { 241295436Sandrew compatible = "marvell,armada-xp-neta"; 242295436Sandrew }; 243295436Sandrew 244295436Sandrew crypto@90000 { 245295436Sandrew compatible = "marvell,armada-xp-crypto"; 246295436Sandrew reg = <0x90000 0x10000>; 247295436Sandrew reg-names = "regs"; 248295436Sandrew interrupts = <48>, <49>; 249295436Sandrew clocks = <&gateclk 23>, <&gateclk 23>; 250295436Sandrew clock-names = "cesa0", "cesa1"; 251295436Sandrew marvell,crypto-srams = <&crypto_sram0>, 252295436Sandrew <&crypto_sram1>; 253295436Sandrew marvell,crypto-sram-size = <0x800>; 254295436Sandrew }; 255295436Sandrew 256279377Simp xor@f0900 { 257279377Simp compatible = "marvell,orion-xor"; 258279377Simp reg = <0xF0900 0x100 259279377Simp 0xF0B00 0x100>; 260279377Simp clocks = <&gateclk 28>; 261279377Simp status = "okay"; 262279377Simp 263279377Simp xor00 { 264279377Simp interrupts = <94>; 265279377Simp dmacap,memcpy; 266279377Simp dmacap,xor; 267279377Simp }; 268279377Simp xor01 { 269279377Simp interrupts = <95>; 270279377Simp dmacap,memcpy; 271279377Simp dmacap,xor; 272279377Simp dmacap,memset; 273279377Simp }; 274279377Simp }; 275279377Simp }; 276295436Sandrew 277295436Sandrew crypto_sram0: sa-sram0 { 278295436Sandrew compatible = "mmio-sram"; 279295436Sandrew reg = <MBUS_ID(0x09, 0x09) 0 0x800>; 280295436Sandrew clocks = <&gateclk 23>; 281295436Sandrew #address-cells = <1>; 282295436Sandrew #size-cells = <1>; 283295436Sandrew ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; 284295436Sandrew }; 285295436Sandrew 286295436Sandrew crypto_sram1: sa-sram1 { 287295436Sandrew compatible = "mmio-sram"; 288295436Sandrew reg = <MBUS_ID(0x09, 0x05) 0 0x800>; 289295436Sandrew clocks = <&gateclk 23>; 290295436Sandrew #address-cells = <1>; 291295436Sandrew #size-cells = <1>; 292295436Sandrew ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; 293295436Sandrew }; 294279377Simp }; 295279377Simp 296279377Simp clocks { 297279377Simp /* 25 MHz reference crystal */ 298279377Simp refclk: oscillator { 299279377Simp compatible = "fixed-clock"; 300279377Simp #clock-cells = <0>; 301279377Simp clock-frequency = <25000000>; 302279377Simp }; 303279377Simp }; 304279377Simp}; 305279377Simp 306279377Simp&pinctrl { 307279377Simp ge0_gmii_pins: ge0-gmii-pins { 308279377Simp marvell,pins = 309279377Simp "mpp0", "mpp1", "mpp2", "mpp3", 310279377Simp "mpp4", "mpp5", "mpp6", "mpp7", 311279377Simp "mpp8", "mpp9", "mpp10", "mpp11", 312279377Simp "mpp12", "mpp13", "mpp14", "mpp15", 313279377Simp "mpp16", "mpp17", "mpp18", "mpp19", 314279377Simp "mpp20", "mpp21", "mpp22", "mpp23"; 315279377Simp marvell,function = "ge0"; 316279377Simp }; 317279377Simp 318279377Simp ge0_rgmii_pins: ge0-rgmii-pins { 319279377Simp marvell,pins = 320279377Simp "mpp0", "mpp1", "mpp2", "mpp3", 321279377Simp "mpp4", "mpp5", "mpp6", "mpp7", 322279377Simp "mpp8", "mpp9", "mpp10", "mpp11"; 323279377Simp marvell,function = "ge0"; 324279377Simp }; 325279377Simp 326279377Simp ge1_rgmii_pins: ge1-rgmii-pins { 327279377Simp marvell,pins = 328279377Simp "mpp12", "mpp13", "mpp14", "mpp15", 329279377Simp "mpp16", "mpp17", "mpp18", "mpp19", 330279377Simp "mpp20", "mpp21", "mpp22", "mpp23"; 331279377Simp marvell,function = "ge1"; 332279377Simp }; 333279377Simp 334279377Simp sdio_pins: sdio-pins { 335279377Simp marvell,pins = "mpp30", "mpp31", "mpp32", 336279377Simp "mpp33", "mpp34", "mpp35"; 337279377Simp marvell,function = "sd0"; 338279377Simp }; 339279377Simp 340279377Simp spi0_pins: spi0-pins { 341279377Simp marvell,pins = "mpp36", "mpp37", 342279377Simp "mpp38", "mpp39"; 343295436Sandrew marvell,function = "spi0"; 344279377Simp }; 345279377Simp 346279377Simp uart2_pins: uart2-pins { 347279377Simp marvell,pins = "mpp42", "mpp43"; 348279377Simp marvell,function = "uart2"; 349279377Simp }; 350279377Simp 351279377Simp uart3_pins: uart3-pins { 352279377Simp marvell,pins = "mpp44", "mpp45"; 353279377Simp marvell,function = "uart3"; 354279377Simp }; 355279377Simp}; 356