armada-xp-mv78460.dtsi revision 279377
1279377Simp/* 2279377Simp * Device Tree Include file for Marvell Armada XP family SoC 3279377Simp * 4279377Simp * Copyright (C) 2012 Marvell 5279377Simp * 6279377Simp * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7279377Simp * 8279377Simp * This file is dual-licensed: you can use it either under the terms 9279377Simp * of the GPL or the X11 license, at your option. Note that this dual 10279377Simp * licensing only applies to this file, and not this project as a 11279377Simp * whole. 12279377Simp * 13279377Simp * a) This file is free software; you can redistribute it and/or 14279377Simp * modify it under the terms of the GNU General Public License as 15279377Simp * published by the Free Software Foundation; either version 2 of the 16279377Simp * License, or (at your option) any later version. 17279377Simp * 18279377Simp * This file is distributed in the hope that it will be useful 19279377Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 20279377Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21279377Simp * GNU General Public License for more details. 22279377Simp * 23279377Simp * Or, alternatively 24279377Simp * 25279377Simp * b) Permission is hereby granted, free of charge, to any person 26279377Simp * obtaining a copy of this software and associated documentation 27279377Simp * files (the "Software"), to deal in the Software without 28279377Simp * restriction, including without limitation the rights to use 29279377Simp * copy, modify, merge, publish, distribute, sublicense, and/or 30279377Simp * sell copies of the Software, and to permit persons to whom the 31279377Simp * Software is furnished to do so, subject to the following 32279377Simp * conditions: 33279377Simp * 34279377Simp * The above copyright notice and this permission notice shall be 35279377Simp * included in all copies or substantial portions of the Software. 36279377Simp * 37279377Simp * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38279377Simp * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39279377Simp * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40279377Simp * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41279377Simp * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42279377Simp * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43279377Simp * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44279377Simp * OTHER DEALINGS IN THE SOFTWARE. 45279377Simp * 46279377Simp * Contains definitions specific to the Armada XP MV78460 SoC that are not 47279377Simp * common to all Armada XP SoCs. 48279377Simp */ 49279377Simp 50279377Simp#include "armada-xp.dtsi" 51279377Simp 52279377Simp/ { 53279377Simp model = "Marvell Armada XP MV78460 SoC"; 54279377Simp compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; 55279377Simp 56279377Simp aliases { 57279377Simp gpio0 = &gpio0; 58279377Simp gpio1 = &gpio1; 59279377Simp gpio2 = &gpio2; 60279377Simp eth3 = ð3; 61279377Simp }; 62279377Simp 63279377Simp 64279377Simp cpus { 65279377Simp #address-cells = <1>; 66279377Simp #size-cells = <0>; 67279377Simp enable-method = "marvell,armada-xp-smp"; 68279377Simp 69279377Simp cpu@0 { 70279377Simp device_type = "cpu"; 71279377Simp compatible = "marvell,sheeva-v7"; 72279377Simp reg = <0>; 73279377Simp clocks = <&cpuclk 0>; 74279377Simp clock-latency = <1000000>; 75279377Simp }; 76279377Simp 77279377Simp cpu@1 { 78279377Simp device_type = "cpu"; 79279377Simp compatible = "marvell,sheeva-v7"; 80279377Simp reg = <1>; 81279377Simp clocks = <&cpuclk 1>; 82279377Simp clock-latency = <1000000>; 83279377Simp }; 84279377Simp 85279377Simp cpu@2 { 86279377Simp device_type = "cpu"; 87279377Simp compatible = "marvell,sheeva-v7"; 88279377Simp reg = <2>; 89279377Simp clocks = <&cpuclk 2>; 90279377Simp clock-latency = <1000000>; 91279377Simp }; 92279377Simp 93279377Simp cpu@3 { 94279377Simp device_type = "cpu"; 95279377Simp compatible = "marvell,sheeva-v7"; 96279377Simp reg = <3>; 97279377Simp clocks = <&cpuclk 3>; 98279377Simp clock-latency = <1000000>; 99279377Simp }; 100279377Simp }; 101279377Simp 102279377Simp soc { 103279377Simp /* 104279377Simp * MV78460 has 4 PCIe units Gen2.0: Two units can be 105279377Simp * configured as x4 or quad x1 lanes. Two units are 106279377Simp * x4/x1. 107279377Simp */ 108279377Simp pcie-controller { 109279377Simp compatible = "marvell,armada-xp-pcie"; 110279377Simp status = "disabled"; 111279377Simp device_type = "pci"; 112279377Simp 113279377Simp #address-cells = <3>; 114279377Simp #size-cells = <2>; 115279377Simp 116279377Simp msi-parent = <&mpic>; 117279377Simp bus-range = <0x00 0xff>; 118279377Simp 119279377Simp ranges = 120279377Simp <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 121279377Simp 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 122279377Simp 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 123279377Simp 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 124279377Simp 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 125279377Simp 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 126279377Simp 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ 127279377Simp 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ 128279377Simp 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ 129279377Simp 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ 130279377Simp 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 131279377Simp 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 132279377Simp 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 133279377Simp 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 134279377Simp 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 135279377Simp 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 136279377Simp 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 137279377Simp 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 138279377Simp 139279377Simp 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 140279377Simp 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 141279377Simp 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ 142279377Simp 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ 143279377Simp 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ 144279377Simp 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ 145279377Simp 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ 146279377Simp 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ 147279377Simp 148279377Simp 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 149279377Simp 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ 150279377Simp 151279377Simp 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ 152279377Simp 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; 153279377Simp 154279377Simp pcie@1,0 { 155279377Simp device_type = "pci"; 156279377Simp assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 157279377Simp reg = <0x0800 0 0 0 0>; 158279377Simp #address-cells = <3>; 159279377Simp #size-cells = <2>; 160279377Simp #interrupt-cells = <1>; 161279377Simp ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 162279377Simp 0x81000000 0 0 0x81000000 0x1 0 1 0>; 163279377Simp interrupt-map-mask = <0 0 0 0>; 164279377Simp interrupt-map = <0 0 0 0 &mpic 58>; 165279377Simp marvell,pcie-port = <0>; 166279377Simp marvell,pcie-lane = <0>; 167279377Simp clocks = <&gateclk 5>; 168279377Simp status = "disabled"; 169279377Simp }; 170279377Simp 171279377Simp pcie@2,0 { 172279377Simp device_type = "pci"; 173279377Simp assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; 174279377Simp reg = <0x1000 0 0 0 0>; 175279377Simp #address-cells = <3>; 176279377Simp #size-cells = <2>; 177279377Simp #interrupt-cells = <1>; 178279377Simp ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 179279377Simp 0x81000000 0 0 0x81000000 0x2 0 1 0>; 180279377Simp interrupt-map-mask = <0 0 0 0>; 181279377Simp interrupt-map = <0 0 0 0 &mpic 59>; 182279377Simp marvell,pcie-port = <0>; 183279377Simp marvell,pcie-lane = <1>; 184279377Simp clocks = <&gateclk 6>; 185279377Simp status = "disabled"; 186279377Simp }; 187279377Simp 188279377Simp pcie@3,0 { 189279377Simp device_type = "pci"; 190279377Simp assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; 191279377Simp reg = <0x1800 0 0 0 0>; 192279377Simp #address-cells = <3>; 193279377Simp #size-cells = <2>; 194279377Simp #interrupt-cells = <1>; 195279377Simp ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 196279377Simp 0x81000000 0 0 0x81000000 0x3 0 1 0>; 197279377Simp interrupt-map-mask = <0 0 0 0>; 198279377Simp interrupt-map = <0 0 0 0 &mpic 60>; 199279377Simp marvell,pcie-port = <0>; 200279377Simp marvell,pcie-lane = <2>; 201279377Simp clocks = <&gateclk 7>; 202279377Simp status = "disabled"; 203279377Simp }; 204279377Simp 205279377Simp pcie@4,0 { 206279377Simp device_type = "pci"; 207279377Simp assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; 208279377Simp reg = <0x2000 0 0 0 0>; 209279377Simp #address-cells = <3>; 210279377Simp #size-cells = <2>; 211279377Simp #interrupt-cells = <1>; 212279377Simp ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 213279377Simp 0x81000000 0 0 0x81000000 0x4 0 1 0>; 214279377Simp interrupt-map-mask = <0 0 0 0>; 215279377Simp interrupt-map = <0 0 0 0 &mpic 61>; 216279377Simp marvell,pcie-port = <0>; 217279377Simp marvell,pcie-lane = <3>; 218279377Simp clocks = <&gateclk 8>; 219279377Simp status = "disabled"; 220279377Simp }; 221279377Simp 222279377Simp pcie@5,0 { 223279377Simp device_type = "pci"; 224279377Simp assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; 225279377Simp reg = <0x2800 0 0 0 0>; 226279377Simp #address-cells = <3>; 227279377Simp #size-cells = <2>; 228279377Simp #interrupt-cells = <1>; 229279377Simp ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 230279377Simp 0x81000000 0 0 0x81000000 0x5 0 1 0>; 231279377Simp interrupt-map-mask = <0 0 0 0>; 232279377Simp interrupt-map = <0 0 0 0 &mpic 62>; 233279377Simp marvell,pcie-port = <1>; 234279377Simp marvell,pcie-lane = <0>; 235279377Simp clocks = <&gateclk 9>; 236279377Simp status = "disabled"; 237279377Simp }; 238279377Simp 239279377Simp pcie@6,0 { 240279377Simp device_type = "pci"; 241279377Simp assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; 242279377Simp reg = <0x3000 0 0 0 0>; 243279377Simp #address-cells = <3>; 244279377Simp #size-cells = <2>; 245279377Simp #interrupt-cells = <1>; 246279377Simp ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 247279377Simp 0x81000000 0 0 0x81000000 0x6 0 1 0>; 248279377Simp interrupt-map-mask = <0 0 0 0>; 249279377Simp interrupt-map = <0 0 0 0 &mpic 63>; 250279377Simp marvell,pcie-port = <1>; 251279377Simp marvell,pcie-lane = <1>; 252279377Simp clocks = <&gateclk 10>; 253279377Simp status = "disabled"; 254279377Simp }; 255279377Simp 256279377Simp pcie@7,0 { 257279377Simp device_type = "pci"; 258279377Simp assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; 259279377Simp reg = <0x3800 0 0 0 0>; 260279377Simp #address-cells = <3>; 261279377Simp #size-cells = <2>; 262279377Simp #interrupt-cells = <1>; 263279377Simp ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 264279377Simp 0x81000000 0 0 0x81000000 0x7 0 1 0>; 265279377Simp interrupt-map-mask = <0 0 0 0>; 266279377Simp interrupt-map = <0 0 0 0 &mpic 64>; 267279377Simp marvell,pcie-port = <1>; 268279377Simp marvell,pcie-lane = <2>; 269279377Simp clocks = <&gateclk 11>; 270279377Simp status = "disabled"; 271279377Simp }; 272279377Simp 273279377Simp pcie@8,0 { 274279377Simp device_type = "pci"; 275279377Simp assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; 276279377Simp reg = <0x4000 0 0 0 0>; 277279377Simp #address-cells = <3>; 278279377Simp #size-cells = <2>; 279279377Simp #interrupt-cells = <1>; 280279377Simp ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 281279377Simp 0x81000000 0 0 0x81000000 0x8 0 1 0>; 282279377Simp interrupt-map-mask = <0 0 0 0>; 283279377Simp interrupt-map = <0 0 0 0 &mpic 65>; 284279377Simp marvell,pcie-port = <1>; 285279377Simp marvell,pcie-lane = <3>; 286279377Simp clocks = <&gateclk 12>; 287279377Simp status = "disabled"; 288279377Simp }; 289279377Simp 290279377Simp pcie@9,0 { 291279377Simp device_type = "pci"; 292279377Simp assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; 293279377Simp reg = <0x4800 0 0 0 0>; 294279377Simp #address-cells = <3>; 295279377Simp #size-cells = <2>; 296279377Simp #interrupt-cells = <1>; 297279377Simp ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 298279377Simp 0x81000000 0 0 0x81000000 0x9 0 1 0>; 299279377Simp interrupt-map-mask = <0 0 0 0>; 300279377Simp interrupt-map = <0 0 0 0 &mpic 99>; 301279377Simp marvell,pcie-port = <2>; 302279377Simp marvell,pcie-lane = <0>; 303279377Simp clocks = <&gateclk 26>; 304279377Simp status = "disabled"; 305279377Simp }; 306279377Simp 307279377Simp pcie@10,0 { 308279377Simp device_type = "pci"; 309279377Simp assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; 310279377Simp reg = <0x5000 0 0 0 0>; 311279377Simp #address-cells = <3>; 312279377Simp #size-cells = <2>; 313279377Simp #interrupt-cells = <1>; 314279377Simp ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 315279377Simp 0x81000000 0 0 0x81000000 0xa 0 1 0>; 316279377Simp interrupt-map-mask = <0 0 0 0>; 317279377Simp interrupt-map = <0 0 0 0 &mpic 103>; 318279377Simp marvell,pcie-port = <3>; 319279377Simp marvell,pcie-lane = <0>; 320279377Simp clocks = <&gateclk 27>; 321279377Simp status = "disabled"; 322279377Simp }; 323279377Simp }; 324279377Simp 325279377Simp internal-regs { 326279377Simp gpio0: gpio@18100 { 327279377Simp compatible = "marvell,orion-gpio"; 328279377Simp reg = <0x18100 0x40>; 329279377Simp ngpios = <32>; 330279377Simp gpio-controller; 331279377Simp #gpio-cells = <2>; 332279377Simp interrupt-controller; 333279377Simp #interrupt-cells = <2>; 334279377Simp interrupts = <82>, <83>, <84>, <85>; 335279377Simp }; 336279377Simp 337279377Simp gpio1: gpio@18140 { 338279377Simp compatible = "marvell,orion-gpio"; 339279377Simp reg = <0x18140 0x40>; 340279377Simp ngpios = <32>; 341279377Simp gpio-controller; 342279377Simp #gpio-cells = <2>; 343279377Simp interrupt-controller; 344279377Simp #interrupt-cells = <2>; 345279377Simp interrupts = <87>, <88>, <89>, <90>; 346279377Simp }; 347279377Simp 348279377Simp gpio2: gpio@18180 { 349279377Simp compatible = "marvell,orion-gpio"; 350279377Simp reg = <0x18180 0x40>; 351279377Simp ngpios = <3>; 352279377Simp gpio-controller; 353279377Simp #gpio-cells = <2>; 354279377Simp interrupt-controller; 355279377Simp #interrupt-cells = <2>; 356279377Simp interrupts = <91>; 357279377Simp }; 358279377Simp 359279377Simp eth3: ethernet@34000 { 360279377Simp compatible = "marvell,armada-370-neta"; 361279377Simp reg = <0x34000 0x4000>; 362279377Simp interrupts = <14>; 363279377Simp clocks = <&gateclk 1>; 364279377Simp status = "disabled"; 365279377Simp }; 366279377Simp }; 367279377Simp }; 368279377Simp}; 369279377Simp 370279377Simp&pinctrl { 371279377Simp compatible = "marvell,mv78460-pinctrl"; 372279377Simp}; 373