1279377Simp/* 2279377Simp * Device Tree Include file for Marvell Armada XP family SoC 3279377Simp * 4279377Simp * Copyright (C) 2012 Marvell 5279377Simp * 6279377Simp * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7279377Simp * 8279377Simp * This file is dual-licensed: you can use it either under the terms 9279377Simp * of the GPL or the X11 license, at your option. Note that this dual 10279377Simp * licensing only applies to this file, and not this project as a 11279377Simp * whole. 12279377Simp * 13279377Simp * a) This file is free software; you can redistribute it and/or 14279377Simp * modify it under the terms of the GNU General Public License as 15279377Simp * published by the Free Software Foundation; either version 2 of the 16279377Simp * License, or (at your option) any later version. 17279377Simp * 18279377Simp * This file is distributed in the hope that it will be useful 19279377Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 20279377Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21279377Simp * GNU General Public License for more details. 22279377Simp * 23279377Simp * Or, alternatively 24279377Simp * 25279377Simp * b) Permission is hereby granted, free of charge, to any person 26279377Simp * obtaining a copy of this software and associated documentation 27279377Simp * files (the "Software"), to deal in the Software without 28279377Simp * restriction, including without limitation the rights to use 29279377Simp * copy, modify, merge, publish, distribute, sublicense, and/or 30279377Simp * sell copies of the Software, and to permit persons to whom the 31279377Simp * Software is furnished to do so, subject to the following 32279377Simp * conditions: 33279377Simp * 34279377Simp * The above copyright notice and this permission notice shall be 35279377Simp * included in all copies or substantial portions of the Software. 36279377Simp * 37279377Simp * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38279377Simp * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39279377Simp * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40279377Simp * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41279377Simp * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42279377Simp * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43279377Simp * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44279377Simp * OTHER DEALINGS IN THE SOFTWARE. 45279377Simp * 46279377Simp * Contains definitions specific to the Armada XP MV78460 SoC that are not 47279377Simp * common to all Armada XP SoCs. 48279377Simp */ 49279377Simp 50279377Simp#include "armada-xp.dtsi" 51279377Simp 52279377Simp/ { 53279377Simp model = "Marvell Armada XP MV78460 SoC"; 54279377Simp compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; 55279377Simp 56279377Simp aliases { 57279377Simp gpio0 = &gpio0; 58279377Simp gpio1 = &gpio1; 59279377Simp gpio2 = &gpio2; 60279377Simp }; 61279377Simp 62279377Simp 63279377Simp cpus { 64279377Simp #address-cells = <1>; 65279377Simp #size-cells = <0>; 66279377Simp enable-method = "marvell,armada-xp-smp"; 67279377Simp 68279377Simp cpu@0 { 69279377Simp device_type = "cpu"; 70279377Simp compatible = "marvell,sheeva-v7"; 71279377Simp reg = <0>; 72279377Simp clocks = <&cpuclk 0>; 73279377Simp clock-latency = <1000000>; 74279377Simp }; 75279377Simp 76279377Simp cpu@1 { 77279377Simp device_type = "cpu"; 78279377Simp compatible = "marvell,sheeva-v7"; 79279377Simp reg = <1>; 80279377Simp clocks = <&cpuclk 1>; 81279377Simp clock-latency = <1000000>; 82279377Simp }; 83279377Simp 84279377Simp cpu@2 { 85279377Simp device_type = "cpu"; 86279377Simp compatible = "marvell,sheeva-v7"; 87279377Simp reg = <2>; 88279377Simp clocks = <&cpuclk 2>; 89279377Simp clock-latency = <1000000>; 90279377Simp }; 91279377Simp 92279377Simp cpu@3 { 93279377Simp device_type = "cpu"; 94279377Simp compatible = "marvell,sheeva-v7"; 95279377Simp reg = <3>; 96279377Simp clocks = <&cpuclk 3>; 97279377Simp clock-latency = <1000000>; 98279377Simp }; 99279377Simp }; 100279377Simp 101279377Simp soc { 102279377Simp /* 103279377Simp * MV78460 has 4 PCIe units Gen2.0: Two units can be 104279377Simp * configured as x4 or quad x1 lanes. Two units are 105279377Simp * x4/x1. 106279377Simp */ 107279377Simp pcie-controller { 108279377Simp compatible = "marvell,armada-xp-pcie"; 109279377Simp status = "disabled"; 110279377Simp device_type = "pci"; 111279377Simp 112279377Simp #address-cells = <3>; 113279377Simp #size-cells = <2>; 114279377Simp 115279377Simp msi-parent = <&mpic>; 116279377Simp bus-range = <0x00 0xff>; 117279377Simp 118279377Simp ranges = 119279377Simp <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 120279377Simp 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 121279377Simp 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 122279377Simp 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 123279377Simp 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 124279377Simp 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 125279377Simp 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ 126279377Simp 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ 127279377Simp 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ 128279377Simp 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ 129279377Simp 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 130279377Simp 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 131279377Simp 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 132279377Simp 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 133279377Simp 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 134279377Simp 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 135279377Simp 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 136279377Simp 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 137279377Simp 138279377Simp 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 139279377Simp 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 140279377Simp 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ 141279377Simp 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ 142279377Simp 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ 143279377Simp 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ 144279377Simp 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ 145279377Simp 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ 146279377Simp 147279377Simp 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 148279377Simp 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ 149279377Simp 150279377Simp 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ 151279377Simp 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; 152279377Simp 153279377Simp pcie@1,0 { 154279377Simp device_type = "pci"; 155279377Simp assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 156279377Simp reg = <0x0800 0 0 0 0>; 157279377Simp #address-cells = <3>; 158279377Simp #size-cells = <2>; 159279377Simp #interrupt-cells = <1>; 160279377Simp ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 161279377Simp 0x81000000 0 0 0x81000000 0x1 0 1 0>; 162279377Simp interrupt-map-mask = <0 0 0 0>; 163279377Simp interrupt-map = <0 0 0 0 &mpic 58>; 164279377Simp marvell,pcie-port = <0>; 165279377Simp marvell,pcie-lane = <0>; 166279377Simp clocks = <&gateclk 5>; 167279377Simp status = "disabled"; 168279377Simp }; 169279377Simp 170279377Simp pcie@2,0 { 171279377Simp device_type = "pci"; 172279377Simp assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; 173279377Simp reg = <0x1000 0 0 0 0>; 174279377Simp #address-cells = <3>; 175279377Simp #size-cells = <2>; 176279377Simp #interrupt-cells = <1>; 177279377Simp ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 178279377Simp 0x81000000 0 0 0x81000000 0x2 0 1 0>; 179279377Simp interrupt-map-mask = <0 0 0 0>; 180279377Simp interrupt-map = <0 0 0 0 &mpic 59>; 181279377Simp marvell,pcie-port = <0>; 182279377Simp marvell,pcie-lane = <1>; 183279377Simp clocks = <&gateclk 6>; 184279377Simp status = "disabled"; 185279377Simp }; 186279377Simp 187279377Simp pcie@3,0 { 188279377Simp device_type = "pci"; 189279377Simp assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; 190279377Simp reg = <0x1800 0 0 0 0>; 191279377Simp #address-cells = <3>; 192279377Simp #size-cells = <2>; 193279377Simp #interrupt-cells = <1>; 194279377Simp ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 195279377Simp 0x81000000 0 0 0x81000000 0x3 0 1 0>; 196279377Simp interrupt-map-mask = <0 0 0 0>; 197279377Simp interrupt-map = <0 0 0 0 &mpic 60>; 198279377Simp marvell,pcie-port = <0>; 199279377Simp marvell,pcie-lane = <2>; 200279377Simp clocks = <&gateclk 7>; 201279377Simp status = "disabled"; 202279377Simp }; 203279377Simp 204279377Simp pcie@4,0 { 205279377Simp device_type = "pci"; 206279377Simp assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; 207279377Simp reg = <0x2000 0 0 0 0>; 208279377Simp #address-cells = <3>; 209279377Simp #size-cells = <2>; 210279377Simp #interrupt-cells = <1>; 211279377Simp ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 212279377Simp 0x81000000 0 0 0x81000000 0x4 0 1 0>; 213279377Simp interrupt-map-mask = <0 0 0 0>; 214279377Simp interrupt-map = <0 0 0 0 &mpic 61>; 215279377Simp marvell,pcie-port = <0>; 216279377Simp marvell,pcie-lane = <3>; 217279377Simp clocks = <&gateclk 8>; 218279377Simp status = "disabled"; 219279377Simp }; 220279377Simp 221279377Simp pcie@5,0 { 222279377Simp device_type = "pci"; 223279377Simp assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; 224279377Simp reg = <0x2800 0 0 0 0>; 225279377Simp #address-cells = <3>; 226279377Simp #size-cells = <2>; 227279377Simp #interrupt-cells = <1>; 228279377Simp ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 229279377Simp 0x81000000 0 0 0x81000000 0x5 0 1 0>; 230279377Simp interrupt-map-mask = <0 0 0 0>; 231279377Simp interrupt-map = <0 0 0 0 &mpic 62>; 232279377Simp marvell,pcie-port = <1>; 233279377Simp marvell,pcie-lane = <0>; 234279377Simp clocks = <&gateclk 9>; 235279377Simp status = "disabled"; 236279377Simp }; 237279377Simp 238279377Simp pcie@6,0 { 239279377Simp device_type = "pci"; 240279377Simp assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; 241279377Simp reg = <0x3000 0 0 0 0>; 242279377Simp #address-cells = <3>; 243279377Simp #size-cells = <2>; 244279377Simp #interrupt-cells = <1>; 245279377Simp ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 246279377Simp 0x81000000 0 0 0x81000000 0x6 0 1 0>; 247279377Simp interrupt-map-mask = <0 0 0 0>; 248279377Simp interrupt-map = <0 0 0 0 &mpic 63>; 249279377Simp marvell,pcie-port = <1>; 250279377Simp marvell,pcie-lane = <1>; 251279377Simp clocks = <&gateclk 10>; 252279377Simp status = "disabled"; 253279377Simp }; 254279377Simp 255279377Simp pcie@7,0 { 256279377Simp device_type = "pci"; 257279377Simp assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; 258279377Simp reg = <0x3800 0 0 0 0>; 259279377Simp #address-cells = <3>; 260279377Simp #size-cells = <2>; 261279377Simp #interrupt-cells = <1>; 262279377Simp ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 263279377Simp 0x81000000 0 0 0x81000000 0x7 0 1 0>; 264279377Simp interrupt-map-mask = <0 0 0 0>; 265279377Simp interrupt-map = <0 0 0 0 &mpic 64>; 266279377Simp marvell,pcie-port = <1>; 267279377Simp marvell,pcie-lane = <2>; 268279377Simp clocks = <&gateclk 11>; 269279377Simp status = "disabled"; 270279377Simp }; 271279377Simp 272279377Simp pcie@8,0 { 273279377Simp device_type = "pci"; 274279377Simp assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; 275279377Simp reg = <0x4000 0 0 0 0>; 276279377Simp #address-cells = <3>; 277279377Simp #size-cells = <2>; 278279377Simp #interrupt-cells = <1>; 279279377Simp ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 280279377Simp 0x81000000 0 0 0x81000000 0x8 0 1 0>; 281279377Simp interrupt-map-mask = <0 0 0 0>; 282279377Simp interrupt-map = <0 0 0 0 &mpic 65>; 283279377Simp marvell,pcie-port = <1>; 284279377Simp marvell,pcie-lane = <3>; 285279377Simp clocks = <&gateclk 12>; 286279377Simp status = "disabled"; 287279377Simp }; 288279377Simp 289279377Simp pcie@9,0 { 290279377Simp device_type = "pci"; 291279377Simp assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; 292279377Simp reg = <0x4800 0 0 0 0>; 293279377Simp #address-cells = <3>; 294279377Simp #size-cells = <2>; 295279377Simp #interrupt-cells = <1>; 296279377Simp ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 297279377Simp 0x81000000 0 0 0x81000000 0x9 0 1 0>; 298279377Simp interrupt-map-mask = <0 0 0 0>; 299279377Simp interrupt-map = <0 0 0 0 &mpic 99>; 300279377Simp marvell,pcie-port = <2>; 301279377Simp marvell,pcie-lane = <0>; 302279377Simp clocks = <&gateclk 26>; 303279377Simp status = "disabled"; 304279377Simp }; 305279377Simp 306279377Simp pcie@10,0 { 307279377Simp device_type = "pci"; 308279377Simp assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; 309279377Simp reg = <0x5000 0 0 0 0>; 310279377Simp #address-cells = <3>; 311279377Simp #size-cells = <2>; 312279377Simp #interrupt-cells = <1>; 313279377Simp ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 314279377Simp 0x81000000 0 0 0x81000000 0xa 0 1 0>; 315279377Simp interrupt-map-mask = <0 0 0 0>; 316279377Simp interrupt-map = <0 0 0 0 &mpic 103>; 317279377Simp marvell,pcie-port = <3>; 318279377Simp marvell,pcie-lane = <0>; 319279377Simp clocks = <&gateclk 27>; 320279377Simp status = "disabled"; 321279377Simp }; 322279377Simp }; 323279377Simp 324279377Simp internal-regs { 325279377Simp gpio0: gpio@18100 { 326279377Simp compatible = "marvell,orion-gpio"; 327279377Simp reg = <0x18100 0x40>; 328279377Simp ngpios = <32>; 329279377Simp gpio-controller; 330279377Simp #gpio-cells = <2>; 331279377Simp interrupt-controller; 332279377Simp #interrupt-cells = <2>; 333279377Simp interrupts = <82>, <83>, <84>, <85>; 334279377Simp }; 335279377Simp 336279377Simp gpio1: gpio@18140 { 337279377Simp compatible = "marvell,orion-gpio"; 338279377Simp reg = <0x18140 0x40>; 339279377Simp ngpios = <32>; 340279377Simp gpio-controller; 341279377Simp #gpio-cells = <2>; 342279377Simp interrupt-controller; 343279377Simp #interrupt-cells = <2>; 344279377Simp interrupts = <87>, <88>, <89>, <90>; 345279377Simp }; 346279377Simp 347279377Simp gpio2: gpio@18180 { 348279377Simp compatible = "marvell,orion-gpio"; 349279377Simp reg = <0x18180 0x40>; 350279377Simp ngpios = <3>; 351279377Simp gpio-controller; 352279377Simp #gpio-cells = <2>; 353279377Simp interrupt-controller; 354279377Simp #interrupt-cells = <2>; 355279377Simp interrupts = <91>; 356279377Simp }; 357279377Simp 358279377Simp eth3: ethernet@34000 { 359295436Sandrew compatible = "marvell,armada-xp-neta"; 360279377Simp reg = <0x34000 0x4000>; 361279377Simp interrupts = <14>; 362279377Simp clocks = <&gateclk 1>; 363279377Simp status = "disabled"; 364279377Simp }; 365279377Simp }; 366279377Simp }; 367279377Simp}; 368279377Simp 369279377Simp&pinctrl { 370279377Simp compatible = "marvell,mv78460-pinctrl"; 371279377Simp}; 372