armada-xp-mv78260.dtsi revision 279377
1279377Simp/* 2279377Simp * Device Tree Include file for Marvell Armada XP family SoC 3279377Simp * 4279377Simp * Copyright (C) 2012 Marvell 5279377Simp * 6279377Simp * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7279377Simp * 8279377Simp * This file is dual-licensed: you can use it either under the terms 9279377Simp * of the GPL or the X11 license, at your option. Note that this dual 10279377Simp * licensing only applies to this file, and not this project as a 11279377Simp * whole. 12279377Simp * 13279377Simp * a) This file is free software; you can redistribute it and/or 14279377Simp * modify it under the terms of the GNU General Public License as 15279377Simp * published by the Free Software Foundation; either version 2 of the 16279377Simp * License, or (at your option) any later version. 17279377Simp * 18279377Simp * This file is distributed in the hope that it will be useful 19279377Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 20279377Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21279377Simp * GNU General Public License for more details. 22279377Simp * 23279377Simp * Or, alternatively 24279377Simp * 25279377Simp * b) Permission is hereby granted, free of charge, to any person 26279377Simp * obtaining a copy of this software and associated documentation 27279377Simp * files (the "Software"), to deal in the Software without 28279377Simp * restriction, including without limitation the rights to use 29279377Simp * copy, modify, merge, publish, distribute, sublicense, and/or 30279377Simp * sell copies of the Software, and to permit persons to whom the 31279377Simp * Software is furnished to do so, subject to the following 32279377Simp * conditions: 33279377Simp * 34279377Simp * The above copyright notice and this permission notice shall be 35279377Simp * included in all copies or substantial portions of the Software. 36279377Simp * 37279377Simp * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38279377Simp * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39279377Simp * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40279377Simp * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41279377Simp * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42279377Simp * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43279377Simp * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44279377Simp * OTHER DEALINGS IN THE SOFTWARE. 45279377Simp * 46279377Simp * Contains definitions specific to the Armada XP MV78260 SoC that are not 47279377Simp * common to all Armada XP SoCs. 48279377Simp */ 49279377Simp 50279377Simp#include "armada-xp.dtsi" 51279377Simp 52279377Simp/ { 53279377Simp model = "Marvell Armada XP MV78260 SoC"; 54279377Simp compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; 55279377Simp 56279377Simp aliases { 57279377Simp gpio0 = &gpio0; 58279377Simp gpio1 = &gpio1; 59279377Simp gpio2 = &gpio2; 60279377Simp eth3 = ð3; 61279377Simp }; 62279377Simp 63279377Simp cpus { 64279377Simp #address-cells = <1>; 65279377Simp #size-cells = <0>; 66279377Simp enable-method = "marvell,armada-xp-smp"; 67279377Simp 68279377Simp cpu@0 { 69279377Simp device_type = "cpu"; 70279377Simp compatible = "marvell,sheeva-v7"; 71279377Simp reg = <0>; 72279377Simp clocks = <&cpuclk 0>; 73279377Simp clock-latency = <1000000>; 74279377Simp }; 75279377Simp 76279377Simp cpu@1 { 77279377Simp device_type = "cpu"; 78279377Simp compatible = "marvell,sheeva-v7"; 79279377Simp reg = <1>; 80279377Simp clocks = <&cpuclk 1>; 81279377Simp clock-latency = <1000000>; 82279377Simp }; 83279377Simp }; 84279377Simp 85279377Simp soc { 86279377Simp /* 87279377Simp * MV78260 has 3 PCIe units Gen2.0: Two units can be 88279377Simp * configured as x4 or quad x1 lanes. One unit is 89279377Simp * x4 only. 90279377Simp */ 91279377Simp pcie-controller { 92279377Simp compatible = "marvell,armada-xp-pcie"; 93279377Simp status = "disabled"; 94279377Simp device_type = "pci"; 95279377Simp 96279377Simp #address-cells = <3>; 97279377Simp #size-cells = <2>; 98279377Simp 99279377Simp msi-parent = <&mpic>; 100279377Simp bus-range = <0x00 0xff>; 101279377Simp 102279377Simp ranges = 103279377Simp <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 104279377Simp 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 105279377Simp 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 106279377Simp 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 107279377Simp 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 108279377Simp 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 109279377Simp 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ 110279377Simp 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ 111279377Simp 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ 112279377Simp 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 113279377Simp 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 114279377Simp 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 115279377Simp 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 116279377Simp 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 117279377Simp 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 118279377Simp 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 119279377Simp 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 120279377Simp 121279377Simp 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 122279377Simp 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 123279377Simp 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ 124279377Simp 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ 125279377Simp 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ 126279377Simp 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ 127279377Simp 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ 128279377Simp 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ 129279377Simp 130279377Simp 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 131279377Simp 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; 132279377Simp 133279377Simp pcie@1,0 { 134279377Simp device_type = "pci"; 135279377Simp assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 136279377Simp reg = <0x0800 0 0 0 0>; 137279377Simp #address-cells = <3>; 138279377Simp #size-cells = <2>; 139279377Simp #interrupt-cells = <1>; 140279377Simp ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 141279377Simp 0x81000000 0 0 0x81000000 0x1 0 1 0>; 142279377Simp interrupt-map-mask = <0 0 0 0>; 143279377Simp interrupt-map = <0 0 0 0 &mpic 58>; 144279377Simp marvell,pcie-port = <0>; 145279377Simp marvell,pcie-lane = <0>; 146279377Simp clocks = <&gateclk 5>; 147279377Simp status = "disabled"; 148279377Simp }; 149279377Simp 150279377Simp pcie@2,0 { 151279377Simp device_type = "pci"; 152279377Simp assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 153279377Simp reg = <0x1000 0 0 0 0>; 154279377Simp #address-cells = <3>; 155279377Simp #size-cells = <2>; 156279377Simp #interrupt-cells = <1>; 157279377Simp ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 158279377Simp 0x81000000 0 0 0x81000000 0x2 0 1 0>; 159279377Simp interrupt-map-mask = <0 0 0 0>; 160279377Simp interrupt-map = <0 0 0 0 &mpic 59>; 161279377Simp marvell,pcie-port = <0>; 162279377Simp marvell,pcie-lane = <1>; 163279377Simp clocks = <&gateclk 6>; 164279377Simp status = "disabled"; 165279377Simp }; 166279377Simp 167279377Simp pcie@3,0 { 168279377Simp device_type = "pci"; 169279377Simp assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; 170279377Simp reg = <0x1800 0 0 0 0>; 171279377Simp #address-cells = <3>; 172279377Simp #size-cells = <2>; 173279377Simp #interrupt-cells = <1>; 174279377Simp ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 175279377Simp 0x81000000 0 0 0x81000000 0x3 0 1 0>; 176279377Simp interrupt-map-mask = <0 0 0 0>; 177279377Simp interrupt-map = <0 0 0 0 &mpic 60>; 178279377Simp marvell,pcie-port = <0>; 179279377Simp marvell,pcie-lane = <2>; 180279377Simp clocks = <&gateclk 7>; 181279377Simp status = "disabled"; 182279377Simp }; 183279377Simp 184279377Simp pcie@4,0 { 185279377Simp device_type = "pci"; 186279377Simp assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; 187279377Simp reg = <0x2000 0 0 0 0>; 188279377Simp #address-cells = <3>; 189279377Simp #size-cells = <2>; 190279377Simp #interrupt-cells = <1>; 191279377Simp ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 192279377Simp 0x81000000 0 0 0x81000000 0x4 0 1 0>; 193279377Simp interrupt-map-mask = <0 0 0 0>; 194279377Simp interrupt-map = <0 0 0 0 &mpic 61>; 195279377Simp marvell,pcie-port = <0>; 196279377Simp marvell,pcie-lane = <3>; 197279377Simp clocks = <&gateclk 8>; 198279377Simp status = "disabled"; 199279377Simp }; 200279377Simp 201279377Simp pcie@5,0 { 202279377Simp device_type = "pci"; 203279377Simp assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 204279377Simp reg = <0x2800 0 0 0 0>; 205279377Simp #address-cells = <3>; 206279377Simp #size-cells = <2>; 207279377Simp #interrupt-cells = <1>; 208279377Simp ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 209279377Simp 0x81000000 0 0 0x81000000 0x5 0 1 0>; 210279377Simp interrupt-map-mask = <0 0 0 0>; 211279377Simp interrupt-map = <0 0 0 0 &mpic 62>; 212279377Simp marvell,pcie-port = <1>; 213279377Simp marvell,pcie-lane = <0>; 214279377Simp clocks = <&gateclk 9>; 215279377Simp status = "disabled"; 216279377Simp }; 217279377Simp 218279377Simp pcie@6,0 { 219279377Simp device_type = "pci"; 220279377Simp assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; 221279377Simp reg = <0x3000 0 0 0 0>; 222279377Simp #address-cells = <3>; 223279377Simp #size-cells = <2>; 224279377Simp #interrupt-cells = <1>; 225279377Simp ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 226279377Simp 0x81000000 0 0 0x81000000 0x6 0 1 0>; 227279377Simp interrupt-map-mask = <0 0 0 0>; 228279377Simp interrupt-map = <0 0 0 0 &mpic 63>; 229279377Simp marvell,pcie-port = <1>; 230279377Simp marvell,pcie-lane = <1>; 231279377Simp clocks = <&gateclk 10>; 232279377Simp status = "disabled"; 233279377Simp }; 234279377Simp 235279377Simp pcie@7,0 { 236279377Simp device_type = "pci"; 237279377Simp assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; 238279377Simp reg = <0x3800 0 0 0 0>; 239279377Simp #address-cells = <3>; 240279377Simp #size-cells = <2>; 241279377Simp #interrupt-cells = <1>; 242279377Simp ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 243279377Simp 0x81000000 0 0 0x81000000 0x7 0 1 0>; 244279377Simp interrupt-map-mask = <0 0 0 0>; 245279377Simp interrupt-map = <0 0 0 0 &mpic 64>; 246279377Simp marvell,pcie-port = <1>; 247279377Simp marvell,pcie-lane = <2>; 248279377Simp clocks = <&gateclk 11>; 249279377Simp status = "disabled"; 250279377Simp }; 251279377Simp 252279377Simp pcie@8,0 { 253279377Simp device_type = "pci"; 254279377Simp assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; 255279377Simp reg = <0x4000 0 0 0 0>; 256279377Simp #address-cells = <3>; 257279377Simp #size-cells = <2>; 258279377Simp #interrupt-cells = <1>; 259279377Simp ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 260279377Simp 0x81000000 0 0 0x81000000 0x8 0 1 0>; 261279377Simp interrupt-map-mask = <0 0 0 0>; 262279377Simp interrupt-map = <0 0 0 0 &mpic 65>; 263279377Simp marvell,pcie-port = <1>; 264279377Simp marvell,pcie-lane = <3>; 265279377Simp clocks = <&gateclk 12>; 266279377Simp status = "disabled"; 267279377Simp }; 268279377Simp 269279377Simp pcie@9,0 { 270279377Simp device_type = "pci"; 271279377Simp assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; 272279377Simp reg = <0x4800 0 0 0 0>; 273279377Simp #address-cells = <3>; 274279377Simp #size-cells = <2>; 275279377Simp #interrupt-cells = <1>; 276279377Simp ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 277279377Simp 0x81000000 0 0 0x81000000 0x9 0 1 0>; 278279377Simp interrupt-map-mask = <0 0 0 0>; 279279377Simp interrupt-map = <0 0 0 0 &mpic 99>; 280279377Simp marvell,pcie-port = <2>; 281279377Simp marvell,pcie-lane = <0>; 282279377Simp clocks = <&gateclk 26>; 283279377Simp status = "disabled"; 284279377Simp }; 285279377Simp }; 286279377Simp 287279377Simp internal-regs { 288279377Simp gpio0: gpio@18100 { 289279377Simp compatible = "marvell,orion-gpio"; 290279377Simp reg = <0x18100 0x40>; 291279377Simp ngpios = <32>; 292279377Simp gpio-controller; 293279377Simp #gpio-cells = <2>; 294279377Simp interrupt-controller; 295279377Simp #interrupt-cells = <2>; 296279377Simp interrupts = <82>, <83>, <84>, <85>; 297279377Simp }; 298279377Simp 299279377Simp gpio1: gpio@18140 { 300279377Simp compatible = "marvell,orion-gpio"; 301279377Simp reg = <0x18140 0x40>; 302279377Simp ngpios = <32>; 303279377Simp gpio-controller; 304279377Simp #gpio-cells = <2>; 305279377Simp interrupt-controller; 306279377Simp #interrupt-cells = <2>; 307279377Simp interrupts = <87>, <88>, <89>, <90>; 308279377Simp }; 309279377Simp 310279377Simp gpio2: gpio@18180 { 311279377Simp compatible = "marvell,orion-gpio"; 312279377Simp reg = <0x18180 0x40>; 313279377Simp ngpios = <3>; 314279377Simp gpio-controller; 315279377Simp #gpio-cells = <2>; 316279377Simp interrupt-controller; 317279377Simp #interrupt-cells = <2>; 318279377Simp interrupts = <91>; 319279377Simp }; 320279377Simp 321279377Simp eth3: ethernet@34000 { 322279377Simp compatible = "marvell,armada-370-neta"; 323279377Simp reg = <0x34000 0x4000>; 324279377Simp interrupts = <14>; 325279377Simp clocks = <&gateclk 1>; 326279377Simp status = "disabled"; 327279377Simp }; 328279377Simp }; 329279377Simp }; 330279377Simp}; 331279377Simp 332279377Simp&pinctrl { 333279377Simp compatible = "marvell,mv78260-pinctrl"; 334279377Simp}; 335