1279377Simp/* 2279377Simp * Device Tree Include file for Marvell Armada XP family SoC 3279377Simp * 4279377Simp * Copyright (C) 2012 Marvell 5279377Simp * 6279377Simp * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7279377Simp * 8279377Simp * This file is dual-licensed: you can use it either under the terms 9279377Simp * of the GPL or the X11 license, at your option. Note that this dual 10279377Simp * licensing only applies to this file, and not this project as a 11279377Simp * whole. 12279377Simp * 13279377Simp * a) This file is free software; you can redistribute it and/or 14279377Simp * modify it under the terms of the GNU General Public License as 15279377Simp * published by the Free Software Foundation; either version 2 of the 16279377Simp * License, or (at your option) any later version. 17279377Simp * 18279377Simp * This file is distributed in the hope that it will be useful 19279377Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 20279377Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21279377Simp * GNU General Public License for more details. 22279377Simp * 23279377Simp * Or, alternatively 24279377Simp * 25279377Simp * b) Permission is hereby granted, free of charge, to any person 26279377Simp * obtaining a copy of this software and associated documentation 27279377Simp * files (the "Software"), to deal in the Software without 28279377Simp * restriction, including without limitation the rights to use 29279377Simp * copy, modify, merge, publish, distribute, sublicense, and/or 30279377Simp * sell copies of the Software, and to permit persons to whom the 31279377Simp * Software is furnished to do so, subject to the following 32279377Simp * conditions: 33279377Simp * 34279377Simp * The above copyright notice and this permission notice shall be 35279377Simp * included in all copies or substantial portions of the Software. 36279377Simp * 37279377Simp * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38279377Simp * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39279377Simp * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40279377Simp * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41279377Simp * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42279377Simp * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43279377Simp * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44279377Simp * OTHER DEALINGS IN THE SOFTWARE. 45279377Simp * 46279377Simp * Contains definitions specific to the Armada XP MV78230 SoC that are not 47279377Simp * common to all Armada XP SoCs. 48279377Simp */ 49279377Simp 50279377Simp#include "armada-xp.dtsi" 51279377Simp 52279377Simp/ { 53279377Simp model = "Marvell Armada XP MV78230 SoC"; 54279377Simp compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; 55279377Simp 56279377Simp aliases { 57279377Simp gpio0 = &gpio0; 58279377Simp gpio1 = &gpio1; 59279377Simp }; 60279377Simp 61279377Simp cpus { 62279377Simp #address-cells = <1>; 63279377Simp #size-cells = <0>; 64279377Simp enable-method = "marvell,armada-xp-smp"; 65279377Simp 66279377Simp cpu@0 { 67279377Simp device_type = "cpu"; 68279377Simp compatible = "marvell,sheeva-v7"; 69279377Simp reg = <0>; 70279377Simp clocks = <&cpuclk 0>; 71279377Simp clock-latency = <1000000>; 72279377Simp }; 73279377Simp 74279377Simp cpu@1 { 75279377Simp device_type = "cpu"; 76279377Simp compatible = "marvell,sheeva-v7"; 77279377Simp reg = <1>; 78279377Simp clocks = <&cpuclk 1>; 79279377Simp clock-latency = <1000000>; 80279377Simp }; 81279377Simp }; 82279377Simp 83279377Simp soc { 84279377Simp /* 85279377Simp * MV78230 has 2 PCIe units Gen2.0: One unit can be 86279377Simp * configured as x4 or quad x1 lanes. One unit is 87279377Simp * x1 only. 88279377Simp */ 89279377Simp pcie-controller { 90279377Simp compatible = "marvell,armada-xp-pcie"; 91279377Simp status = "disabled"; 92279377Simp device_type = "pci"; 93279377Simp 94279377Simp #address-cells = <3>; 95279377Simp #size-cells = <2>; 96279377Simp 97279377Simp msi-parent = <&mpic>; 98279377Simp bus-range = <0x00 0xff>; 99279377Simp 100279377Simp ranges = 101279377Simp <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 102279377Simp 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 103279377Simp 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 104279377Simp 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 105279377Simp 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 106279377Simp 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 107279377Simp 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 108279377Simp 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 109279377Simp 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 110279377Simp 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 111279377Simp 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 112279377Simp 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 113279377Simp 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 114279377Simp 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 115279377Simp 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; 116279377Simp 117279377Simp pcie@1,0 { 118279377Simp device_type = "pci"; 119279377Simp assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 120279377Simp reg = <0x0800 0 0 0 0>; 121279377Simp #address-cells = <3>; 122279377Simp #size-cells = <2>; 123279377Simp #interrupt-cells = <1>; 124279377Simp ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 125279377Simp 0x81000000 0 0 0x81000000 0x1 0 1 0>; 126279377Simp interrupt-map-mask = <0 0 0 0>; 127279377Simp interrupt-map = <0 0 0 0 &mpic 58>; 128279377Simp marvell,pcie-port = <0>; 129279377Simp marvell,pcie-lane = <0>; 130279377Simp clocks = <&gateclk 5>; 131279377Simp status = "disabled"; 132279377Simp }; 133279377Simp 134279377Simp pcie@2,0 { 135279377Simp device_type = "pci"; 136279377Simp assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 137279377Simp reg = <0x1000 0 0 0 0>; 138279377Simp #address-cells = <3>; 139279377Simp #size-cells = <2>; 140279377Simp #interrupt-cells = <1>; 141279377Simp ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 142279377Simp 0x81000000 0 0 0x81000000 0x2 0 1 0>; 143279377Simp interrupt-map-mask = <0 0 0 0>; 144279377Simp interrupt-map = <0 0 0 0 &mpic 59>; 145279377Simp marvell,pcie-port = <0>; 146279377Simp marvell,pcie-lane = <1>; 147279377Simp clocks = <&gateclk 6>; 148279377Simp status = "disabled"; 149279377Simp }; 150279377Simp 151279377Simp pcie@3,0 { 152279377Simp device_type = "pci"; 153279377Simp assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; 154279377Simp reg = <0x1800 0 0 0 0>; 155279377Simp #address-cells = <3>; 156279377Simp #size-cells = <2>; 157279377Simp #interrupt-cells = <1>; 158279377Simp ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 159279377Simp 0x81000000 0 0 0x81000000 0x3 0 1 0>; 160279377Simp interrupt-map-mask = <0 0 0 0>; 161279377Simp interrupt-map = <0 0 0 0 &mpic 60>; 162279377Simp marvell,pcie-port = <0>; 163279377Simp marvell,pcie-lane = <2>; 164279377Simp clocks = <&gateclk 7>; 165279377Simp status = "disabled"; 166279377Simp }; 167279377Simp 168279377Simp pcie@4,0 { 169279377Simp device_type = "pci"; 170279377Simp assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; 171279377Simp reg = <0x2000 0 0 0 0>; 172279377Simp #address-cells = <3>; 173279377Simp #size-cells = <2>; 174279377Simp #interrupt-cells = <1>; 175279377Simp ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 176279377Simp 0x81000000 0 0 0x81000000 0x4 0 1 0>; 177279377Simp interrupt-map-mask = <0 0 0 0>; 178279377Simp interrupt-map = <0 0 0 0 &mpic 61>; 179279377Simp marvell,pcie-port = <0>; 180279377Simp marvell,pcie-lane = <3>; 181279377Simp clocks = <&gateclk 8>; 182279377Simp status = "disabled"; 183279377Simp }; 184279377Simp 185279377Simp pcie@5,0 { 186279377Simp device_type = "pci"; 187279377Simp assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 188279377Simp reg = <0x2800 0 0 0 0>; 189279377Simp #address-cells = <3>; 190279377Simp #size-cells = <2>; 191279377Simp #interrupt-cells = <1>; 192279377Simp ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 193279377Simp 0x81000000 0 0 0x81000000 0x5 0 1 0>; 194279377Simp interrupt-map-mask = <0 0 0 0>; 195279377Simp interrupt-map = <0 0 0 0 &mpic 62>; 196279377Simp marvell,pcie-port = <1>; 197279377Simp marvell,pcie-lane = <0>; 198279377Simp clocks = <&gateclk 9>; 199279377Simp status = "disabled"; 200279377Simp }; 201279377Simp }; 202279377Simp 203279377Simp internal-regs { 204279377Simp gpio0: gpio@18100 { 205279377Simp compatible = "marvell,orion-gpio"; 206279377Simp reg = <0x18100 0x40>; 207279377Simp ngpios = <32>; 208279377Simp gpio-controller; 209279377Simp #gpio-cells = <2>; 210279377Simp interrupt-controller; 211279377Simp #interrupt-cells = <2>; 212279377Simp interrupts = <82>, <83>, <84>, <85>; 213279377Simp }; 214279377Simp 215279377Simp gpio1: gpio@18140 { 216279377Simp compatible = "marvell,orion-gpio"; 217279377Simp reg = <0x18140 0x40>; 218279377Simp ngpios = <17>; 219279377Simp gpio-controller; 220279377Simp #gpio-cells = <2>; 221279377Simp interrupt-controller; 222279377Simp #interrupt-cells = <2>; 223279377Simp interrupts = <87>, <88>, <89>; 224279377Simp }; 225279377Simp }; 226279377Simp }; 227279377Simp}; 228279377Simp 229279377Simp&pinctrl { 230279377Simp compatible = "marvell,mv78230-pinctrl"; 231279377Simp}; 232