armada-xp-gp.dts revision 295436
1279377Simp/* 2279377Simp * Device Tree file for Marvell Armada XP development board 3279377Simp * (DB-MV784MP-GP) 4279377Simp * 5279377Simp * Copyright (C) 2013-2014 Marvell 6279377Simp * 7279377Simp * Lior Amsalem <alior@marvell.com> 8279377Simp * Gregory CLEMENT <gregory.clement@free-electrons.com> 9279377Simp * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10279377Simp * 11279377Simp * This file is dual-licensed: you can use it either under the terms 12279377Simp * of the GPL or the X11 license, at your option. Note that this dual 13279377Simp * licensing only applies to this file, and not this project as a 14279377Simp * whole. 15279377Simp * 16279377Simp * a) This file is free software; you can redistribute it and/or 17279377Simp * modify it under the terms of the GNU General Public License as 18279377Simp * published by the Free Software Foundation; either version 2 of the 19279377Simp * License, or (at your option) any later version. 20279377Simp * 21279377Simp * This file is distributed in the hope that it will be useful 22279377Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 23279377Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24279377Simp * GNU General Public License for more details. 25279377Simp * 26279377Simp * Or, alternatively 27279377Simp * 28279377Simp * b) Permission is hereby granted, free of charge, to any person 29279377Simp * obtaining a copy of this software and associated documentation 30279377Simp * files (the "Software"), to deal in the Software without 31279377Simp * restriction, including without limitation the rights to use 32279377Simp * copy, modify, merge, publish, distribute, sublicense, and/or 33279377Simp * sell copies of the Software, and to permit persons to whom the 34279377Simp * Software is furnished to do so, subject to the following 35279377Simp * conditions: 36279377Simp * 37279377Simp * The above copyright notice and this permission notice shall be 38279377Simp * included in all copies or substantial portions of the Software. 39279377Simp * 40279377Simp * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 41279377Simp * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42279377Simp * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43279377Simp * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44279377Simp * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 45279377Simp * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46279377Simp * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47279377Simp * OTHER DEALINGS IN THE SOFTWARE. 48279377Simp * 49279377Simp * Note: this Device Tree assumes that the bootloader has remapped the 50279377Simp * internal registers to 0xf1000000 (instead of the default 51279377Simp * 0xd0000000). The 0xf1000000 is the default used by the recent, 52279377Simp * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier 53279377Simp * boards were delivered with an older version of the bootloader that 54279377Simp * left internal registers mapped at 0xd0000000. If you are in this 55279377Simp * situation, you should either update your bootloader (preferred 56279377Simp * solution) or the below Device Tree should be adjusted. 57279377Simp */ 58279377Simp 59279377Simp/dts-v1/; 60279377Simp#include <dt-bindings/gpio/gpio.h> 61279377Simp#include "armada-xp-mv78460.dtsi" 62279377Simp 63279377Simp/ { 64279377Simp model = "Marvell Armada XP Development Board DB-MV784MP-GP"; 65279377Simp compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; 66279377Simp 67279377Simp chosen { 68295436Sandrew stdout-path = "serial0:115200n8"; 69279377Simp }; 70279377Simp 71279377Simp memory { 72279377Simp device_type = "memory"; 73279377Simp /* 74279377Simp * 8 GB of plug-in RAM modules by default.The amount 75279377Simp * of memory available can be changed by the 76279377Simp * bootloader according the size of the module 77279377Simp * actually plugged. However, memory between 78279377Simp * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is 79279377Simp * the address range used for I/O (internal registers, 80279377Simp * MBus windows). 81279377Simp */ 82279377Simp reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, 83279377Simp <0x00000001 0x00000000 0x00000001 0x00000000>; 84279377Simp }; 85279377Simp 86279377Simp cpus { 87279377Simp pm_pic { 88279377Simp ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, 89279377Simp <&gpio0 17 GPIO_ACTIVE_LOW>, 90279377Simp <&gpio0 18 GPIO_ACTIVE_LOW>; 91279377Simp }; 92279377Simp }; 93279377Simp 94279377Simp soc { 95279377Simp ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 96279377Simp MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 97295436Sandrew MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000 98295436Sandrew MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000 99295436Sandrew MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>; 100279377Simp 101279377Simp devbus-bootcs { 102279377Simp status = "okay"; 103279377Simp 104279377Simp /* Device Bus parameters are required */ 105279377Simp 106279377Simp /* Read parameters */ 107279377Simp devbus,bus-width = <16>; 108279377Simp devbus,turn-off-ps = <60000>; 109279377Simp devbus,badr-skew-ps = <0>; 110279377Simp devbus,acc-first-ps = <124000>; 111279377Simp devbus,acc-next-ps = <248000>; 112279377Simp devbus,rd-setup-ps = <0>; 113279377Simp devbus,rd-hold-ps = <0>; 114279377Simp 115279377Simp /* Write parameters */ 116279377Simp devbus,sync-enable = <0>; 117279377Simp devbus,wr-high-ps = <60000>; 118279377Simp devbus,wr-low-ps = <60000>; 119279377Simp devbus,ale-wr-ps = <60000>; 120279377Simp 121279377Simp /* NOR 16 MiB */ 122279377Simp nor@0 { 123279377Simp compatible = "cfi-flash"; 124279377Simp reg = <0 0x1000000>; 125279377Simp bank-width = <2>; 126279377Simp }; 127279377Simp }; 128279377Simp 129279377Simp pcie-controller { 130279377Simp status = "okay"; 131279377Simp 132279377Simp /* 133279377Simp * The 3 slots are physically present as 134279377Simp * standard PCIe slots on the board. 135279377Simp */ 136279377Simp pcie@1,0 { 137279377Simp /* Port 0, Lane 0 */ 138279377Simp status = "okay"; 139279377Simp }; 140279377Simp pcie@9,0 { 141279377Simp /* Port 2, Lane 0 */ 142279377Simp status = "okay"; 143279377Simp }; 144279377Simp pcie@10,0 { 145279377Simp /* Port 3, Lane 0 */ 146279377Simp status = "okay"; 147279377Simp }; 148279377Simp }; 149279377Simp 150279377Simp internal-regs { 151279377Simp serial@12000 { 152279377Simp status = "okay"; 153279377Simp }; 154279377Simp serial@12100 { 155279377Simp status = "okay"; 156279377Simp }; 157279377Simp serial@12200 { 158279377Simp status = "okay"; 159279377Simp }; 160279377Simp serial@12300 { 161279377Simp status = "okay"; 162279377Simp }; 163279377Simp pinctrl { 164279377Simp pinctrl-0 = <&pic_pins>; 165279377Simp pinctrl-names = "default"; 166279377Simp pic_pins: pic-pins-0 { 167279377Simp marvell,pins = "mpp16", "mpp17", 168279377Simp "mpp18"; 169279377Simp marvell,function = "gpio"; 170279377Simp }; 171279377Simp }; 172279377Simp sata@a0000 { 173279377Simp nr-ports = <2>; 174279377Simp status = "okay"; 175279377Simp }; 176279377Simp 177279377Simp mdio { 178279377Simp phy0: ethernet-phy@0 { 179279377Simp reg = <16>; 180279377Simp }; 181279377Simp 182279377Simp phy1: ethernet-phy@1 { 183279377Simp reg = <17>; 184279377Simp }; 185279377Simp 186279377Simp phy2: ethernet-phy@2 { 187279377Simp reg = <18>; 188279377Simp }; 189279377Simp 190279377Simp phy3: ethernet-phy@3 { 191279377Simp reg = <19>; 192279377Simp }; 193279377Simp }; 194279377Simp 195279377Simp ethernet@70000 { 196279377Simp status = "okay"; 197279377Simp phy = <&phy0>; 198279377Simp phy-mode = "qsgmii"; 199279377Simp }; 200279377Simp ethernet@74000 { 201279377Simp status = "okay"; 202279377Simp phy = <&phy1>; 203279377Simp phy-mode = "qsgmii"; 204279377Simp }; 205279377Simp ethernet@30000 { 206279377Simp status = "okay"; 207279377Simp phy = <&phy2>; 208279377Simp phy-mode = "qsgmii"; 209279377Simp }; 210279377Simp ethernet@34000 { 211279377Simp status = "okay"; 212279377Simp phy = <&phy3>; 213279377Simp phy-mode = "qsgmii"; 214279377Simp }; 215279377Simp 216279377Simp /* Front-side USB slot */ 217279377Simp usb@50000 { 218279377Simp status = "okay"; 219279377Simp }; 220279377Simp 221279377Simp /* Back-side USB slot */ 222279377Simp usb@51000 { 223279377Simp status = "okay"; 224279377Simp }; 225279377Simp 226279377Simp spi0: spi@10600 { 227279377Simp status = "okay"; 228279377Simp 229279377Simp spi-flash@0 { 230279377Simp #address-cells = <1>; 231279377Simp #size-cells = <1>; 232295436Sandrew compatible = "n25q128a13", "jedec,spi-nor"; 233279377Simp reg = <0>; /* Chip select 0 */ 234279377Simp spi-max-frequency = <108000000>; 235279377Simp }; 236279377Simp }; 237279377Simp 238279377Simp nand@d0000 { 239279377Simp status = "okay"; 240279377Simp num-cs = <1>; 241279377Simp marvell,nand-keep-config; 242279377Simp marvell,nand-enable-arbiter; 243279377Simp nand-on-flash-bbt; 244279377Simp }; 245279377Simp }; 246279377Simp }; 247279377Simp}; 248