armada-39x.dtsi revision 295011
1295011Sandrew/* 2295011Sandrew * Device Tree Include file for Marvell Armada 39x family of SoCs. 3295011Sandrew * 4295011Sandrew * Copyright (C) 2015 Marvell 5295011Sandrew * 6295011Sandrew * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7295011Sandrew * 8295011Sandrew * This file is dual-licensed: you can use it either under the terms 9295011Sandrew * of the GPL or the X11 license, at your option. Note that this dual 10295011Sandrew * licensing only applies to this file, and not this project as a 11295011Sandrew * whole. 12295011Sandrew * 13295011Sandrew * a) This file is free software; you can redistribute it and/or 14295011Sandrew * modify it under the terms of the GNU General Public License as 15295011Sandrew * published by the Free Software Foundation; either version 2 of the 16295011Sandrew * License, or (at your option) any later version. 17295011Sandrew * 18295011Sandrew * This file is distributed in the hope that it will be useful 19295011Sandrew * but WITHOUT ANY WARRANTY; without even the implied warranty of 20295011Sandrew * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21295011Sandrew * GNU General Public License for more details. 22295011Sandrew * 23295011Sandrew * Or, alternatively 24295011Sandrew * 25295011Sandrew * b) Permission is hereby granted, free of charge, to any person 26295011Sandrew * obtaining a copy of this software and associated documentation 27295011Sandrew * files (the "Software"), to deal in the Software without 28295011Sandrew * restriction, including without limitation the rights to use 29295011Sandrew * copy, modify, merge, publish, distribute, sublicense, and/or 30295011Sandrew * sell copies of the Software, and to permit persons to whom the 31295011Sandrew * Software is furnished to do so, subject to the following 32295011Sandrew * conditions: 33295011Sandrew * 34295011Sandrew * The above copyright notice and this permission notice shall be 35295011Sandrew * included in all copies or substantial portions of the Software. 36295011Sandrew * 37295011Sandrew * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38295011Sandrew * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39295011Sandrew * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40295011Sandrew * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41295011Sandrew * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42295011Sandrew * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43295011Sandrew * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44295011Sandrew * OTHER DEALINGS IN THE SOFTWARE. 45295011Sandrew */ 46295011Sandrew 47295011Sandrew#include "skeleton.dtsi" 48295011Sandrew#include <dt-bindings/interrupt-controller/arm-gic.h> 49295011Sandrew#include <dt-bindings/interrupt-controller/irq.h> 50295011Sandrew 51295011Sandrew#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 52295011Sandrew 53295011Sandrew/ { 54295011Sandrew model = "Marvell Armada 39x family SoC"; 55295011Sandrew compatible = "marvell,armada390"; 56295011Sandrew 57295011Sandrew aliases { 58295011Sandrew serial0 = &uart0; 59295011Sandrew serial1 = &uart1; 60295011Sandrew serial2 = &uart2; 61295011Sandrew serial3 = &uart3; 62295011Sandrew }; 63295011Sandrew 64295011Sandrew cpus { 65295011Sandrew #address-cells = <1>; 66295011Sandrew #size-cells = <0>; 67295011Sandrew enable-method = "marvell,armada-390-smp"; 68295011Sandrew 69295011Sandrew cpu@0 { 70295011Sandrew device_type = "cpu"; 71295011Sandrew compatible = "arm,cortex-a9"; 72295011Sandrew reg = <0>; 73295011Sandrew }; 74295011Sandrew cpu@1 { 75295011Sandrew device_type = "cpu"; 76295011Sandrew compatible = "arm,cortex-a9"; 77295011Sandrew reg = <1>; 78295011Sandrew }; 79295011Sandrew }; 80295011Sandrew 81295011Sandrew soc { 82295011Sandrew compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus", 83295011Sandrew "simple-bus"; 84295011Sandrew #address-cells = <2>; 85295011Sandrew #size-cells = <1>; 86295011Sandrew controller = <&mbusc>; 87295011Sandrew interrupt-parent = <&gic>; 88295011Sandrew pcie-mem-aperture = <0xe0000000 0x8000000>; 89295011Sandrew pcie-io-aperture = <0xe8000000 0x100000>; 90295011Sandrew 91295011Sandrew bootrom { 92295011Sandrew compatible = "marvell,bootrom"; 93295011Sandrew reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 94295011Sandrew }; 95295011Sandrew 96295011Sandrew internal-regs { 97295011Sandrew compatible = "simple-bus"; 98295011Sandrew #address-cells = <1>; 99295011Sandrew #size-cells = <1>; 100295011Sandrew ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 101295011Sandrew 102295011Sandrew L2: cache-controller@8000 { 103295011Sandrew compatible = "arm,pl310-cache"; 104295011Sandrew reg = <0x8000 0x1000>; 105295011Sandrew cache-unified; 106295011Sandrew cache-level = <2>; 107295011Sandrew arm,double-linefill-incr = <1>; 108295011Sandrew arm,double-linefill-wrap = <0>; 109295011Sandrew arm,double-linefill = <1>; 110295011Sandrew prefetch-data = <1>; 111295011Sandrew }; 112295011Sandrew 113295011Sandrew scu@c000 { 114295011Sandrew compatible = "arm,cortex-a9-scu"; 115295011Sandrew reg = <0xc000 0x100>; 116295011Sandrew }; 117295011Sandrew 118295011Sandrew timer@c600 { 119295011Sandrew compatible = "arm,cortex-a9-twd-timer"; 120295011Sandrew reg = <0xc600 0x20>; 121295011Sandrew interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 122295011Sandrew clocks = <&coreclk 2>; 123295011Sandrew }; 124295011Sandrew 125295011Sandrew gic: interrupt-controller@d000 { 126295011Sandrew compatible = "arm,cortex-a9-gic"; 127295011Sandrew #interrupt-cells = <3>; 128295011Sandrew #size-cells = <0>; 129295011Sandrew interrupt-controller; 130295011Sandrew reg = <0xd000 0x1000>, 131295011Sandrew <0xc100 0x100>; 132295011Sandrew }; 133295011Sandrew 134295011Sandrew spi0: spi@10600 { 135295011Sandrew compatible = "marvell,armada-390-spi", 136295011Sandrew "marvell,orion-spi"; 137295011Sandrew reg = <0x10600 0x50>; 138295011Sandrew #address-cells = <1>; 139295011Sandrew #size-cells = <0>; 140295011Sandrew cell-index = <0>; 141295011Sandrew interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 142295011Sandrew clocks = <&coreclk 0>; 143295011Sandrew status = "disabled"; 144295011Sandrew }; 145295011Sandrew 146295011Sandrew spi1: spi@10680 { 147295011Sandrew compatible = "marvell,armada-390-spi", 148295011Sandrew "marvell,orion-spi"; 149295011Sandrew reg = <0x10680 0x50>; 150295011Sandrew #address-cells = <1>; 151295011Sandrew #size-cells = <0>; 152295011Sandrew cell-index = <1>; 153295011Sandrew interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 154295011Sandrew clocks = <&coreclk 0>; 155295011Sandrew status = "disabled"; 156295011Sandrew }; 157295011Sandrew 158295011Sandrew i2c0: i2c@11000 { 159295011Sandrew compatible = "marvell,mv64xxx-i2c"; 160295011Sandrew reg = <0x11000 0x20>; 161295011Sandrew #address-cells = <1>; 162295011Sandrew #size-cells = <0>; 163295011Sandrew interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 164295011Sandrew timeout-ms = <1000>; 165295011Sandrew clocks = <&coreclk 0>; 166295011Sandrew status = "disabled"; 167295011Sandrew }; 168295011Sandrew 169295011Sandrew i2c1: i2c@11100 { 170295011Sandrew compatible = "marvell,mv64xxx-i2c"; 171295011Sandrew reg = <0x11100 0x20>; 172295011Sandrew #address-cells = <1>; 173295011Sandrew #size-cells = <0>; 174295011Sandrew interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 175295011Sandrew timeout-ms = <1000>; 176295011Sandrew clocks = <&coreclk 0>; 177295011Sandrew status = "disabled"; 178295011Sandrew }; 179295011Sandrew 180295011Sandrew i2c2: i2c@11200 { 181295011Sandrew compatible = "marvell,mv64xxx-i2c"; 182295011Sandrew reg = <0x11200 0x20>; 183295011Sandrew #address-cells = <1>; 184295011Sandrew #size-cells = <0>; 185295011Sandrew interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 186295011Sandrew timeout-ms = <1000>; 187295011Sandrew clocks = <&coreclk 0>; 188295011Sandrew status = "disabled"; 189295011Sandrew }; 190295011Sandrew 191295011Sandrew i2c3: i2c@11300 { 192295011Sandrew compatible = "marvell,mv64xxx-i2c"; 193295011Sandrew reg = <0x11300 0x20>; 194295011Sandrew #address-cells = <1>; 195295011Sandrew #size-cells = <0>; 196295011Sandrew interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 197295011Sandrew timeout-ms = <1000>; 198295011Sandrew clocks = <&coreclk 0>; 199295011Sandrew status = "disabled"; 200295011Sandrew }; 201295011Sandrew 202295011Sandrew uart0: serial@12000 { 203295011Sandrew compatible = "snps,dw-apb-uart"; 204295011Sandrew reg = <0x12000 0x100>; 205295011Sandrew reg-shift = <2>; 206295011Sandrew interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 207295011Sandrew reg-io-width = <1>; 208295011Sandrew clocks = <&coreclk 0>; 209295011Sandrew status = "disabled"; 210295011Sandrew }; 211295011Sandrew 212295011Sandrew uart1: serial@12100 { 213295011Sandrew compatible = "snps,dw-apb-uart"; 214295011Sandrew reg = <0x12100 0x100>; 215295011Sandrew reg-shift = <2>; 216295011Sandrew interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 217295011Sandrew reg-io-width = <1>; 218295011Sandrew clocks = <&coreclk 0>; 219295011Sandrew status = "disabled"; 220295011Sandrew }; 221295011Sandrew 222295011Sandrew uart2: serial@12200 { 223295011Sandrew compatible = "snps,dw-apb-uart"; 224295011Sandrew reg = <0x12200 0x100>; 225295011Sandrew reg-shift = <2>; 226295011Sandrew interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 227295011Sandrew reg-io-width = <1>; 228295011Sandrew clocks = <&coreclk 0>; 229295011Sandrew status = "disabled"; 230295011Sandrew }; 231295011Sandrew 232295011Sandrew uart3: serial@12300 { 233295011Sandrew compatible = "snps,dw-apb-uart"; 234295011Sandrew reg = <0x12300 0x100>; 235295011Sandrew reg-shift = <2>; 236295011Sandrew interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 237295011Sandrew reg-io-width = <1>; 238295011Sandrew clocks = <&coreclk 0>; 239295011Sandrew status = "disabled"; 240295011Sandrew }; 241295011Sandrew 242295011Sandrew pinctrl@18000 { 243295011Sandrew i2c0_pins: i2c0-pins { 244295011Sandrew marvell,pins = "mpp2", "mpp3"; 245295011Sandrew marvell,function = "i2c0"; 246295011Sandrew }; 247295011Sandrew 248295011Sandrew uart0_pins: uart0-pins { 249295011Sandrew marvell,pins = "mpp0", "mpp1"; 250295011Sandrew marvell,function = "ua0"; 251295011Sandrew }; 252295011Sandrew 253295011Sandrew uart1_pins: uart1-pins { 254295011Sandrew marvell,pins = "mpp19", "mpp20"; 255295011Sandrew marvell,function = "ua1"; 256295011Sandrew }; 257295011Sandrew 258295011Sandrew spi1_pins: spi1-pins { 259295011Sandrew marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; 260295011Sandrew marvell,function = "spi1"; 261295011Sandrew }; 262295011Sandrew 263295011Sandrew nand_pins: nand-pins { 264295011Sandrew marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", 265295011Sandrew "mpp38", "mpp28", "mpp40", "mpp42", 266295011Sandrew "mpp35", "mpp36", "mpp25", "mpp30", 267295011Sandrew "mpp32"; 268295011Sandrew marvell,function = "dev"; 269295011Sandrew }; 270295011Sandrew }; 271295011Sandrew 272295011Sandrew system-controller@18200 { 273295011Sandrew compatible = "marvell,armada-390-system-controller", 274295011Sandrew "marvell,armada-370-xp-system-controller"; 275295011Sandrew reg = <0x18200 0x100>; 276295011Sandrew }; 277295011Sandrew 278295011Sandrew gateclk: clock-gating-control@18220 { 279295011Sandrew compatible = "marvell,armada-390-gating-clock"; 280295011Sandrew reg = <0x18220 0x4>; 281295011Sandrew clocks = <&coreclk 0>; 282295011Sandrew #clock-cells = <1>; 283295011Sandrew }; 284295011Sandrew 285295011Sandrew coreclk: mvebu-sar@18600 { 286295011Sandrew compatible = "marvell,armada-390-core-clock"; 287295011Sandrew reg = <0x18600 0x04>; 288295011Sandrew #clock-cells = <1>; 289295011Sandrew }; 290295011Sandrew 291295011Sandrew mbusc: mbus-controller@20000 { 292295011Sandrew compatible = "marvell,mbus-controller"; 293295011Sandrew reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; 294295011Sandrew }; 295295011Sandrew 296295011Sandrew mpic: interrupt-controller@20a00 { 297295011Sandrew compatible = "marvell,mpic"; 298295011Sandrew reg = <0x20a00 0x2d0>, <0x21070 0x58>; 299295011Sandrew #interrupt-cells = <1>; 300295011Sandrew #size-cells = <1>; 301295011Sandrew interrupt-controller; 302295011Sandrew msi-controller; 303295011Sandrew interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 304295011Sandrew }; 305295011Sandrew 306295011Sandrew timer@20300 { 307295011Sandrew compatible = "marvell,armada-380-timer", 308295011Sandrew "marvell,armada-xp-timer"; 309295011Sandrew reg = <0x20300 0x30>, <0x21040 0x30>; 310295011Sandrew interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 311295011Sandrew <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 312295011Sandrew <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 313295011Sandrew <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 314295011Sandrew <&mpic 5>, 315295011Sandrew <&mpic 6>; 316295011Sandrew clocks = <&coreclk 2>, <&coreclk 5>; 317295011Sandrew clock-names = "nbclk", "fixed"; 318295011Sandrew }; 319295011Sandrew 320295011Sandrew cpurst@20800 { 321295011Sandrew compatible = "marvell,armada-370-cpu-reset"; 322295011Sandrew reg = <0x20800 0x10>; 323295011Sandrew }; 324295011Sandrew 325295011Sandrew pmsu@22000 { 326295011Sandrew compatible = "marvell,armada-390-pmsu", 327295011Sandrew "marvell,armada-380-pmsu"; 328295011Sandrew reg = <0x22000 0x1000>; 329295011Sandrew }; 330295011Sandrew 331295011Sandrew xor@60800 { 332295011Sandrew compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 333295011Sandrew reg = <0x60800 0x100 334295011Sandrew 0x60a00 0x100>; 335295011Sandrew clocks = <&gateclk 22>; 336295011Sandrew status = "okay"; 337295011Sandrew 338295011Sandrew xor00 { 339295011Sandrew interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 340295011Sandrew dmacap,memcpy; 341295011Sandrew dmacap,xor; 342295011Sandrew }; 343295011Sandrew xor01 { 344295011Sandrew interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 345295011Sandrew dmacap,memcpy; 346295011Sandrew dmacap,xor; 347295011Sandrew dmacap,memset; 348295011Sandrew }; 349295011Sandrew }; 350295011Sandrew 351295011Sandrew xor@60900 { 352295011Sandrew compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 353295011Sandrew reg = <0x60900 0x100 354295011Sandrew 0x60b00 0x100>; 355295011Sandrew clocks = <&gateclk 28>; 356295011Sandrew status = "okay"; 357295011Sandrew 358295011Sandrew xor10 { 359295011Sandrew interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 360295011Sandrew dmacap,memcpy; 361295011Sandrew dmacap,xor; 362295011Sandrew }; 363295011Sandrew xor11 { 364295011Sandrew interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 365295011Sandrew dmacap,memcpy; 366295011Sandrew dmacap,xor; 367295011Sandrew dmacap,memset; 368295011Sandrew }; 369295011Sandrew }; 370295011Sandrew 371295011Sandrew flash@d0000 { 372295011Sandrew compatible = "marvell,armada370-nand"; 373295011Sandrew reg = <0xd0000 0x54>; 374295011Sandrew #address-cells = <1>; 375295011Sandrew #size-cells = <1>; 376295011Sandrew interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 377295011Sandrew clocks = <&coredivclk 0>; 378295011Sandrew status = "disabled"; 379295011Sandrew }; 380295011Sandrew 381295011Sandrew sdhci@d8000 { 382295011Sandrew compatible = "marvell,armada-380-sdhci"; 383295011Sandrew reg = <0xd8000 0x1000>, <0xdc000 0x100>; 384295011Sandrew interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 385295011Sandrew clocks = <&gateclk 17>; 386295011Sandrew mrvl,clk-delay-cycles = <0x1F>; 387295011Sandrew status = "disabled"; 388295011Sandrew }; 389295011Sandrew 390295011Sandrew coredivclk: clock@e4250 { 391295011Sandrew compatible = "marvell,armada-390-corediv-clock", 392295011Sandrew "marvell,armada-380-corediv-clock"; 393295011Sandrew reg = <0xe4250 0xc>; 394295011Sandrew #clock-cells = <1>; 395295011Sandrew clocks = <&mainpll>; 396295011Sandrew clock-output-names = "nand"; 397295011Sandrew }; 398295011Sandrew }; 399295011Sandrew 400295011Sandrew pcie-controller { 401295011Sandrew compatible = "marvell,armada-370-pcie"; 402295011Sandrew status = "disabled"; 403295011Sandrew device_type = "pci"; 404295011Sandrew 405295011Sandrew #address-cells = <3>; 406295011Sandrew #size-cells = <2>; 407295011Sandrew 408295011Sandrew msi-parent = <&mpic>; 409295011Sandrew bus-range = <0x00 0xff>; 410295011Sandrew 411295011Sandrew ranges = 412295011Sandrew <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 413295011Sandrew 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 414295011Sandrew 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 415295011Sandrew 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 416295011Sandrew 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 417295011Sandrew 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ 418295011Sandrew 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ 419295011Sandrew 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ 420295011Sandrew 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ 421295011Sandrew 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ 422295011Sandrew 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ 423295011Sandrew 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; 424295011Sandrew 425295011Sandrew /* 426295011Sandrew * This port can be either x4 or x1. When 427295011Sandrew * configured in x4 by the bootloader, then 428295011Sandrew * pcie@4,0 is not available. 429295011Sandrew */ 430295011Sandrew pcie@1,0 { 431295011Sandrew device_type = "pci"; 432295011Sandrew assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 433295011Sandrew reg = <0x0800 0 0 0 0>; 434295011Sandrew #address-cells = <3>; 435295011Sandrew #size-cells = <2>; 436295011Sandrew #interrupt-cells = <1>; 437295011Sandrew ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 438295011Sandrew 0x81000000 0 0 0x81000000 0x1 0 1 0>; 439295011Sandrew interrupt-map-mask = <0 0 0 0>; 440295011Sandrew interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 441295011Sandrew marvell,pcie-port = <0>; 442295011Sandrew marvell,pcie-lane = <0>; 443295011Sandrew clocks = <&gateclk 8>; 444295011Sandrew status = "disabled"; 445295011Sandrew }; 446295011Sandrew 447295011Sandrew /* x1 port */ 448295011Sandrew pcie@2,0 { 449295011Sandrew device_type = "pci"; 450295011Sandrew assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 451295011Sandrew reg = <0x1000 0 0 0 0>; 452295011Sandrew #address-cells = <3>; 453295011Sandrew #size-cells = <2>; 454295011Sandrew #interrupt-cells = <1>; 455295011Sandrew ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 456295011Sandrew 0x81000000 0 0 0x81000000 0x2 0 1 0>; 457295011Sandrew interrupt-map-mask = <0 0 0 0>; 458295011Sandrew interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 459295011Sandrew marvell,pcie-port = <1>; 460295011Sandrew marvell,pcie-lane = <0>; 461295011Sandrew clocks = <&gateclk 5>; 462295011Sandrew status = "disabled"; 463295011Sandrew }; 464295011Sandrew 465295011Sandrew /* x1 port */ 466295011Sandrew pcie@3,0 { 467295011Sandrew device_type = "pci"; 468295011Sandrew assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 469295011Sandrew reg = <0x1800 0 0 0 0>; 470295011Sandrew #address-cells = <3>; 471295011Sandrew #size-cells = <2>; 472295011Sandrew #interrupt-cells = <1>; 473295011Sandrew ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 474295011Sandrew 0x81000000 0 0 0x81000000 0x3 0 1 0>; 475295011Sandrew interrupt-map-mask = <0 0 0 0>; 476295011Sandrew interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 477295011Sandrew marvell,pcie-port = <2>; 478295011Sandrew marvell,pcie-lane = <0>; 479295011Sandrew clocks = <&gateclk 6>; 480295011Sandrew status = "disabled"; 481295011Sandrew }; 482295011Sandrew 483295011Sandrew /* 484295011Sandrew * x1 port only available when pcie@1,0 is 485295011Sandrew * configured as a x1 port 486295011Sandrew */ 487295011Sandrew pcie@4,0 { 488295011Sandrew device_type = "pci"; 489295011Sandrew assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; 490295011Sandrew reg = <0x2000 0 0 0 0>; 491295011Sandrew #address-cells = <3>; 492295011Sandrew #size-cells = <2>; 493295011Sandrew #interrupt-cells = <1>; 494295011Sandrew ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 495295011Sandrew 0x81000000 0 0 0x81000000 0x4 0 1 0>; 496295011Sandrew interrupt-map-mask = <0 0 0 0>; 497295011Sandrew interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 498295011Sandrew marvell,pcie-port = <3>; 499295011Sandrew marvell,pcie-lane = <0>; 500295011Sandrew clocks = <&gateclk 7>; 501295011Sandrew status = "disabled"; 502295011Sandrew }; 503295011Sandrew }; 504295011Sandrew }; 505295011Sandrew 506295011Sandrew clocks { 507295011Sandrew /* 2 GHz fixed main PLL */ 508295011Sandrew mainpll: mainpll { 509295011Sandrew compatible = "fixed-clock"; 510295011Sandrew #clock-cells = <0>; 511295011Sandrew clock-frequency = <1000000000>; 512295011Sandrew }; 513295011Sandrew }; 514295011Sandrew}; 515