1279377Simp/* 2279377Simp * Device Tree Include file for Marvell Armada 370 family SoC 3279377Simp * 4279377Simp * Copyright (C) 2012 Marvell 5279377Simp * 6279377Simp * Lior Amsalem <alior@marvell.com> 7279377Simp * Gregory CLEMENT <gregory.clement@free-electrons.com> 8279377Simp * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9279377Simp * 10279377Simp * This file is dual-licensed: you can use it either under the terms 11279377Simp * of the GPL or the X11 license, at your option. Note that this dual 12279377Simp * licensing only applies to this file, and not this project as a 13279377Simp * whole. 14279377Simp * 15279377Simp * a) This file is free software; you can redistribute it and/or 16279377Simp * modify it under the terms of the GNU General Public License as 17279377Simp * published by the Free Software Foundation; either version 2 of the 18279377Simp * License, or (at your option) any later version. 19279377Simp * 20279377Simp * This file is distributed in the hope that it will be useful 21279377Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 22279377Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23279377Simp * GNU General Public License for more details. 24279377Simp * 25279377Simp * Or, alternatively 26279377Simp * 27279377Simp * b) Permission is hereby granted, free of charge, to any person 28279377Simp * obtaining a copy of this software and associated documentation 29279377Simp * files (the "Software"), to deal in the Software without 30279377Simp * restriction, including without limitation the rights to use 31279377Simp * copy, modify, merge, publish, distribute, sublicense, and/or 32279377Simp * sell copies of the Software, and to permit persons to whom the 33279377Simp * Software is furnished to do so, subject to the following 34279377Simp * conditions: 35279377Simp * 36279377Simp * The above copyright notice and this permission notice shall be 37279377Simp * included in all copies or substantial portions of the Software. 38279377Simp * 39279377Simp * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 40279377Simp * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41279377Simp * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42279377Simp * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43279377Simp * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 44279377Simp * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45279377Simp * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46279377Simp * OTHER DEALINGS IN THE SOFTWARE. 47279377Simp * 48279377Simp * Contains definitions specific to the Armada 370 SoC that are not 49279377Simp * common to all Armada SoCs. 50279377Simp */ 51279377Simp 52279377Simp#include "armada-370-xp.dtsi" 53279377Simp/include/ "skeleton.dtsi" 54279377Simp 55279377Simp/ { 56279377Simp model = "Marvell Armada 370 family SoC"; 57279377Simp compatible = "marvell,armada370", "marvell,armada-370-xp"; 58279377Simp 59279377Simp aliases { 60279377Simp gpio0 = &gpio0; 61279377Simp gpio1 = &gpio1; 62279377Simp gpio2 = &gpio2; 63279377Simp }; 64279377Simp 65279377Simp soc { 66279377Simp compatible = "marvell,armada370-mbus", "simple-bus"; 67279377Simp 68279377Simp bootrom { 69279377Simp compatible = "marvell,bootrom"; 70279377Simp reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; 71279377Simp }; 72279377Simp 73279377Simp pcie-controller { 74279377Simp compatible = "marvell,armada-370-pcie"; 75279377Simp status = "disabled"; 76279377Simp device_type = "pci"; 77279377Simp 78279377Simp #address-cells = <3>; 79279377Simp #size-cells = <2>; 80279377Simp 81279377Simp msi-parent = <&mpic>; 82279377Simp bus-range = <0x00 0xff>; 83279377Simp 84279377Simp ranges = 85279377Simp <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 86279377Simp 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 87279377Simp 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 88279377Simp 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 89279377Simp 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 90279377Simp 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; 91279377Simp 92279377Simp pcie@1,0 { 93279377Simp device_type = "pci"; 94279377Simp assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 95279377Simp reg = <0x0800 0 0 0 0>; 96279377Simp #address-cells = <3>; 97279377Simp #size-cells = <2>; 98279377Simp #interrupt-cells = <1>; 99279377Simp ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 100279377Simp 0x81000000 0 0 0x81000000 0x1 0 1 0>; 101279377Simp interrupt-map-mask = <0 0 0 0>; 102279377Simp interrupt-map = <0 0 0 0 &mpic 58>; 103279377Simp marvell,pcie-port = <0>; 104279377Simp marvell,pcie-lane = <0>; 105279377Simp clocks = <&gateclk 5>; 106279377Simp status = "disabled"; 107279377Simp }; 108279377Simp 109279377Simp pcie@2,0 { 110279377Simp device_type = "pci"; 111279377Simp assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; 112279377Simp reg = <0x1000 0 0 0 0>; 113279377Simp #address-cells = <3>; 114279377Simp #size-cells = <2>; 115279377Simp #interrupt-cells = <1>; 116279377Simp ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 117279377Simp 0x81000000 0 0 0x81000000 0x2 0 1 0>; 118279377Simp interrupt-map-mask = <0 0 0 0>; 119279377Simp interrupt-map = <0 0 0 0 &mpic 62>; 120279377Simp marvell,pcie-port = <1>; 121279377Simp marvell,pcie-lane = <0>; 122279377Simp clocks = <&gateclk 9>; 123279377Simp status = "disabled"; 124279377Simp }; 125279377Simp }; 126279377Simp 127279377Simp internal-regs { 128279377Simp L2: l2-cache { 129279377Simp compatible = "marvell,aurora-outer-cache"; 130279377Simp reg = <0x08000 0x1000>; 131279377Simp cache-id-part = <0x100>; 132295436Sandrew cache-level = <2>; 133279377Simp cache-unified; 134279377Simp wt-override; 135279377Simp }; 136279377Simp 137279377Simp /* 138279377Simp * Default SPI pinctrl setting, can be overwritten on 139279377Simp * board level if a different configuration is used. 140279377Simp */ 141279377Simp spi0: spi@10600 { 142295436Sandrew compatible = "marvell,armada-370-spi", 143295436Sandrew "marvell,orion-spi"; 144279377Simp pinctrl-0 = <&spi0_pins1>; 145279377Simp pinctrl-names = "default"; 146279377Simp }; 147279377Simp 148279377Simp spi1: spi@10680 { 149295436Sandrew compatible = "marvell,armada-370-spi", 150295436Sandrew "marvell,orion-spi"; 151279377Simp pinctrl-0 = <&spi1_pins>; 152279377Simp pinctrl-names = "default"; 153279377Simp }; 154279377Simp 155279377Simp i2c0: i2c@11000 { 156279377Simp reg = <0x11000 0x20>; 157279377Simp }; 158279377Simp 159279377Simp i2c1: i2c@11100 { 160279377Simp reg = <0x11100 0x20>; 161279377Simp }; 162279377Simp 163279377Simp gpio0: gpio@18100 { 164279377Simp compatible = "marvell,orion-gpio"; 165279377Simp reg = <0x18100 0x40>; 166279377Simp ngpios = <32>; 167279377Simp gpio-controller; 168279377Simp #gpio-cells = <2>; 169279377Simp interrupt-controller; 170279377Simp #interrupt-cells = <2>; 171279377Simp interrupts = <82>, <83>, <84>, <85>; 172279377Simp }; 173279377Simp 174279377Simp gpio1: gpio@18140 { 175279377Simp compatible = "marvell,orion-gpio"; 176279377Simp reg = <0x18140 0x40>; 177279377Simp ngpios = <32>; 178279377Simp gpio-controller; 179279377Simp #gpio-cells = <2>; 180279377Simp interrupt-controller; 181279377Simp #interrupt-cells = <2>; 182279377Simp interrupts = <87>, <88>, <89>, <90>; 183279377Simp }; 184279377Simp 185279377Simp gpio2: gpio@18180 { 186279377Simp compatible = "marvell,orion-gpio"; 187279377Simp reg = <0x18180 0x40>; 188279377Simp ngpios = <2>; 189279377Simp gpio-controller; 190279377Simp #gpio-cells = <2>; 191279377Simp interrupt-controller; 192279377Simp #interrupt-cells = <2>; 193279377Simp interrupts = <91>; 194279377Simp }; 195279377Simp 196279377Simp /* 197279377Simp * Default UART pinctrl setting without RTS/CTS, can 198279377Simp * be overwritten on board level if a different 199279377Simp * configuration is used. 200279377Simp */ 201279377Simp uart0: serial@12000 { 202279377Simp pinctrl-0 = <&uart0_pins>; 203279377Simp pinctrl-names = "default"; 204279377Simp }; 205279377Simp 206279377Simp uart1: serial@12100 { 207279377Simp pinctrl-0 = <&uart1_pins>; 208279377Simp pinctrl-names = "default"; 209279377Simp }; 210279377Simp 211279377Simp system-controller@18200 { 212279377Simp compatible = "marvell,armada-370-xp-system-controller"; 213279377Simp reg = <0x18200 0x100>; 214279377Simp }; 215279377Simp 216279377Simp gateclk: clock-gating-control@18220 { 217279377Simp compatible = "marvell,armada-370-gating-clock"; 218279377Simp reg = <0x18220 0x4>; 219279377Simp clocks = <&coreclk 0>; 220279377Simp #clock-cells = <1>; 221279377Simp }; 222279377Simp 223279377Simp coreclk: mvebu-sar@18230 { 224279377Simp compatible = "marvell,armada-370-core-clock"; 225279377Simp reg = <0x18230 0x08>; 226279377Simp #clock-cells = <1>; 227279377Simp }; 228279377Simp 229279377Simp thermal@18300 { 230279377Simp compatible = "marvell,armada370-thermal"; 231279377Simp reg = <0x18300 0x4 232279377Simp 0x18304 0x4>; 233279377Simp status = "okay"; 234279377Simp }; 235279377Simp 236279377Simp sscg@18330 { 237279377Simp reg = <0x18330 0x4>; 238279377Simp }; 239279377Simp 240295436Sandrew interrupt-controller@20a00 { 241279377Simp reg = <0x20a00 0x1d0>, <0x21870 0x58>; 242279377Simp }; 243279377Simp 244279377Simp timer@20300 { 245279377Simp compatible = "marvell,armada-370-timer"; 246279377Simp clocks = <&coreclk 2>; 247279377Simp }; 248279377Simp 249279377Simp watchdog@20300 { 250279377Simp compatible = "marvell,armada-370-wdt"; 251279377Simp clocks = <&coreclk 2>; 252279377Simp }; 253279377Simp 254279377Simp cpurst@20800 { 255279377Simp compatible = "marvell,armada-370-cpu-reset"; 256279377Simp reg = <0x20800 0x8>; 257279377Simp }; 258279377Simp 259295436Sandrew cpu-config@21000 { 260295436Sandrew compatible = "marvell,armada-370-cpu-config"; 261295436Sandrew reg = <0x21000 0x8>; 262295436Sandrew }; 263295436Sandrew 264279377Simp audio_controller: audio-controller@30000 { 265279377Simp #sound-dai-cells = <1>; 266279377Simp compatible = "marvell,armada370-audio"; 267279377Simp reg = <0x30000 0x4000>; 268279377Simp interrupts = <93>; 269279377Simp clocks = <&gateclk 0>; 270279377Simp clock-names = "internal"; 271279377Simp status = "disabled"; 272279377Simp }; 273279377Simp 274279377Simp usb@50000 { 275279377Simp clocks = <&coreclk 0>; 276279377Simp }; 277279377Simp 278279377Simp usb@51000 { 279279377Simp clocks = <&coreclk 0>; 280279377Simp }; 281279377Simp 282279377Simp xor@60800 { 283279377Simp compatible = "marvell,orion-xor"; 284279377Simp reg = <0x60800 0x100 285279377Simp 0x60A00 0x100>; 286279377Simp status = "okay"; 287279377Simp 288279377Simp xor00 { 289279377Simp interrupts = <51>; 290279377Simp dmacap,memcpy; 291279377Simp dmacap,xor; 292279377Simp }; 293279377Simp xor01 { 294279377Simp interrupts = <52>; 295279377Simp dmacap,memcpy; 296279377Simp dmacap,xor; 297279377Simp dmacap,memset; 298279377Simp }; 299279377Simp }; 300279377Simp 301279377Simp xor@60900 { 302279377Simp compatible = "marvell,orion-xor"; 303279377Simp reg = <0x60900 0x100 304279377Simp 0x60b00 0x100>; 305279377Simp status = "okay"; 306279377Simp 307279377Simp xor10 { 308279377Simp interrupts = <94>; 309279377Simp dmacap,memcpy; 310279377Simp dmacap,xor; 311279377Simp }; 312279377Simp xor11 { 313279377Simp interrupts = <95>; 314279377Simp dmacap,memcpy; 315279377Simp dmacap,xor; 316279377Simp dmacap,memset; 317279377Simp }; 318279377Simp }; 319295436Sandrew 320295436Sandrew ethernet@70000 { 321295436Sandrew compatible = "marvell,armada-370-neta"; 322295436Sandrew }; 323295436Sandrew 324295436Sandrew ethernet@74000 { 325295436Sandrew compatible = "marvell,armada-370-neta"; 326295436Sandrew }; 327295436Sandrew 328295436Sandrew crypto@90000 { 329295436Sandrew compatible = "marvell,armada-370-crypto"; 330295436Sandrew reg = <0x90000 0x10000>; 331295436Sandrew reg-names = "regs"; 332295436Sandrew interrupts = <48>; 333295436Sandrew clocks = <&gateclk 23>; 334295436Sandrew clock-names = "cesa0"; 335295436Sandrew marvell,crypto-srams = <&crypto_sram>; 336295436Sandrew marvell,crypto-sram-size = <0x7e0>; 337295436Sandrew }; 338279377Simp }; 339295436Sandrew 340295436Sandrew crypto_sram: sa-sram { 341295436Sandrew compatible = "mmio-sram"; 342295436Sandrew reg = <MBUS_ID(0x09, 0x01) 0 0x800>; 343295436Sandrew reg-names = "sram"; 344295436Sandrew clocks = <&gateclk 23>; 345295436Sandrew #address-cells = <1>; 346295436Sandrew #size-cells = <1>; 347295436Sandrew ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>; 348295436Sandrew 349295436Sandrew /* 350295436Sandrew * The Armada 370 has an erratum preventing the use of 351295436Sandrew * the standard workflow for CPU idle support (relying 352295436Sandrew * on the BootROM code to enter/exit idle state). 353295436Sandrew * Reserve some amount of the crypto SRAM to put the 354295436Sandrew * cpuidle workaround. 355295436Sandrew */ 356295436Sandrew idle-sram@0 { 357295436Sandrew reg = <0x0 0x20>; 358295436Sandrew }; 359295436Sandrew }; 360279377Simp }; 361279377Simp}; 362279377Simp 363279377Simp&pinctrl { 364279377Simp compatible = "marvell,mv88f6710-pinctrl"; 365279377Simp 366279377Simp spi0_pins1: spi0-pins1 { 367279377Simp marvell,pins = "mpp33", "mpp34", 368279377Simp "mpp35", "mpp36"; 369279377Simp marvell,function = "spi0"; 370279377Simp }; 371279377Simp 372279377Simp spi0_pins2: spi0_pins2 { 373279377Simp marvell,pins = "mpp32", "mpp63", 374279377Simp "mpp64", "mpp65"; 375279377Simp marvell,function = "spi0"; 376279377Simp }; 377279377Simp 378279377Simp spi1_pins: spi1-pins { 379279377Simp marvell,pins = "mpp49", "mpp50", 380279377Simp "mpp51", "mpp52"; 381279377Simp marvell,function = "spi1"; 382279377Simp }; 383279377Simp 384279377Simp uart0_pins: uart0-pins { 385279377Simp marvell,pins = "mpp0", "mpp1"; 386279377Simp marvell,function = "uart0"; 387279377Simp }; 388279377Simp 389279377Simp uart1_pins: uart1-pins { 390279377Simp marvell,pins = "mpp41", "mpp42"; 391279377Simp marvell,function = "uart1"; 392279377Simp }; 393279377Simp 394279377Simp sdio_pins1: sdio-pins1 { 395279377Simp marvell,pins = "mpp9", "mpp11", "mpp12", 396279377Simp "mpp13", "mpp14", "mpp15"; 397279377Simp marvell,function = "sd0"; 398279377Simp }; 399279377Simp 400279377Simp sdio_pins2: sdio-pins2 { 401279377Simp marvell,pins = "mpp47", "mpp48", "mpp49", 402279377Simp "mpp50", "mpp51", "mpp52"; 403279377Simp marvell,function = "sd0"; 404279377Simp }; 405279377Simp 406279377Simp sdio_pins3: sdio-pins3 { 407279377Simp marvell,pins = "mpp48", "mpp49", "mpp50", 408279377Simp "mpp51", "mpp52", "mpp53"; 409279377Simp marvell,function = "sd0"; 410279377Simp }; 411279377Simp 412279377Simp i2c0_pins: i2c0-pins { 413279377Simp marvell,pins = "mpp2", "mpp3"; 414279377Simp marvell,function = "i2c0"; 415279377Simp }; 416279377Simp 417279377Simp i2s_pins1: i2s-pins1 { 418279377Simp marvell,pins = "mpp5", "mpp6", "mpp7", 419279377Simp "mpp8", "mpp9", "mpp10", 420279377Simp "mpp12", "mpp13"; 421279377Simp marvell,function = "audio"; 422279377Simp }; 423279377Simp 424279377Simp i2s_pins2: i2s-pins2 { 425279377Simp marvell,pins = "mpp49", "mpp47", "mpp50", 426279377Simp "mpp59", "mpp57", "mpp61", 427279377Simp "mpp62", "mpp60", "mpp58"; 428279377Simp marvell,function = "audio"; 429279377Simp }; 430279377Simp 431279377Simp mdio_pins: mdio-pins { 432279377Simp marvell,pins = "mpp17", "mpp18"; 433279377Simp marvell,function = "ge"; 434279377Simp }; 435279377Simp 436279377Simp ge0_rgmii_pins: ge0-rgmii-pins { 437279377Simp marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", 438279377Simp "mpp9", "mpp10", "mpp11", "mpp12", 439279377Simp "mpp13", "mpp14", "mpp15", "mpp16"; 440279377Simp marvell,function = "ge0"; 441279377Simp }; 442279377Simp 443279377Simp ge1_rgmii_pins: ge1-rgmii-pins { 444279377Simp marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", 445279377Simp "mpp23", "mpp24", "mpp25", "mpp26", 446279377Simp "mpp27", "mpp28", "mpp29", "mpp30"; 447279377Simp marvell,function = "ge1"; 448279377Simp }; 449279377Simp}; 450