1279377Simp/* 2279377Simp * Device Tree Include file for Marvell Armada 370 and Armada XP SoC 3279377Simp * 4279377Simp * Copyright (C) 2012 Marvell 5279377Simp * 6279377Simp * Lior Amsalem <alior@marvell.com> 7279377Simp * Gregory CLEMENT <gregory.clement@free-electrons.com> 8279377Simp * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9279377Simp * Ben Dooks <ben.dooks@codethink.co.uk> 10279377Simp * 11279377Simp * This file is dual-licensed: you can use it either under the terms 12279377Simp * of the GPL or the X11 license, at your option. Note that this dual 13279377Simp * licensing only applies to this file, and not this project as a 14279377Simp * whole. 15279377Simp * 16279377Simp * a) This file is free software; you can redistribute it and/or 17279377Simp * modify it under the terms of the GNU General Public License as 18279377Simp * published by the Free Software Foundation; either version 2 of the 19279377Simp * License, or (at your option) any later version. 20279377Simp * 21279377Simp * This file is distributed in the hope that it will be useful 22279377Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 23279377Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24279377Simp * GNU General Public License for more details. 25279377Simp * 26279377Simp * Or, alternatively 27279377Simp * 28279377Simp * b) Permission is hereby granted, free of charge, to any person 29279377Simp * obtaining a copy of this software and associated documentation 30279377Simp * files (the "Software"), to deal in the Software without 31279377Simp * restriction, including without limitation the rights to use 32279377Simp * copy, modify, merge, publish, distribute, sublicense, and/or 33279377Simp * sell copies of the Software, and to permit persons to whom the 34279377Simp * Software is furnished to do so, subject to the following 35279377Simp * conditions: 36279377Simp * 37279377Simp * The above copyright notice and this permission notice shall be 38279377Simp * included in all copies or substantial portions of the Software. 39279377Simp * 40279377Simp * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 41279377Simp * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42279377Simp * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43279377Simp * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44279377Simp * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 45279377Simp * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46279377Simp * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47279377Simp * OTHER DEALINGS IN THE SOFTWARE. 48279377Simp * 49279377Simp * This file contains the definitions that are common to the Armada 50279377Simp * 370 and Armada XP SoC. 51279377Simp */ 52279377Simp 53279377Simp/include/ "skeleton64.dtsi" 54279377Simp 55279377Simp#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 56279377Simp 57279377Simp/ { 58279377Simp model = "Marvell Armada 370 and XP SoC"; 59279377Simp compatible = "marvell,armada-370-xp"; 60279377Simp 61279377Simp aliases { 62295436Sandrew serial0 = &uart0; 63295436Sandrew serial1 = &uart1; 64279377Simp }; 65279377Simp 66279377Simp cpus { 67279377Simp #address-cells = <1>; 68279377Simp #size-cells = <0>; 69279377Simp cpu@0 { 70279377Simp compatible = "marvell,sheeva-v7"; 71279377Simp device_type = "cpu"; 72279377Simp reg = <0>; 73279377Simp }; 74279377Simp }; 75279377Simp 76295436Sandrew pmu { 77295436Sandrew compatible = "arm,cortex-a9-pmu"; 78295436Sandrew interrupts-extended = <&mpic 3>; 79295436Sandrew }; 80295436Sandrew 81279377Simp soc { 82279377Simp #address-cells = <2>; 83279377Simp #size-cells = <1>; 84279377Simp controller = <&mbusc>; 85279377Simp interrupt-parent = <&mpic>; 86279377Simp pcie-mem-aperture = <0xf8000000 0x7e00000>; 87279377Simp pcie-io-aperture = <0xffe00000 0x100000>; 88279377Simp 89279377Simp devbus-bootcs { 90279377Simp compatible = "marvell,mvebu-devbus"; 91279377Simp reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; 92279377Simp ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; 93279377Simp #address-cells = <1>; 94279377Simp #size-cells = <1>; 95279377Simp clocks = <&coreclk 0>; 96279377Simp status = "disabled"; 97279377Simp }; 98279377Simp 99279377Simp devbus-cs0 { 100279377Simp compatible = "marvell,mvebu-devbus"; 101279377Simp reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; 102279377Simp ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; 103279377Simp #address-cells = <1>; 104279377Simp #size-cells = <1>; 105279377Simp clocks = <&coreclk 0>; 106279377Simp status = "disabled"; 107279377Simp }; 108279377Simp 109279377Simp devbus-cs1 { 110279377Simp compatible = "marvell,mvebu-devbus"; 111279377Simp reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; 112279377Simp ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; 113279377Simp #address-cells = <1>; 114279377Simp #size-cells = <1>; 115279377Simp clocks = <&coreclk 0>; 116279377Simp status = "disabled"; 117279377Simp }; 118279377Simp 119279377Simp devbus-cs2 { 120279377Simp compatible = "marvell,mvebu-devbus"; 121279377Simp reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; 122279377Simp ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; 123279377Simp #address-cells = <1>; 124279377Simp #size-cells = <1>; 125279377Simp clocks = <&coreclk 0>; 126279377Simp status = "disabled"; 127279377Simp }; 128279377Simp 129279377Simp devbus-cs3 { 130279377Simp compatible = "marvell,mvebu-devbus"; 131279377Simp reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; 132279377Simp ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; 133279377Simp #address-cells = <1>; 134279377Simp #size-cells = <1>; 135279377Simp clocks = <&coreclk 0>; 136279377Simp status = "disabled"; 137279377Simp }; 138279377Simp 139279377Simp internal-regs { 140279377Simp compatible = "simple-bus"; 141279377Simp #address-cells = <1>; 142279377Simp #size-cells = <1>; 143279377Simp ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 144279377Simp 145279377Simp rtc@10300 { 146279377Simp compatible = "marvell,orion-rtc"; 147279377Simp reg = <0x10300 0x20>; 148279377Simp interrupts = <50>; 149279377Simp }; 150279377Simp 151279377Simp spi0: spi@10600 { 152279377Simp reg = <0x10600 0x28>; 153279377Simp #address-cells = <1>; 154279377Simp #size-cells = <0>; 155279377Simp cell-index = <0>; 156279377Simp interrupts = <30>; 157279377Simp clocks = <&coreclk 0>; 158279377Simp status = "disabled"; 159279377Simp }; 160279377Simp 161279377Simp spi1: spi@10680 { 162279377Simp reg = <0x10680 0x28>; 163279377Simp #address-cells = <1>; 164279377Simp #size-cells = <0>; 165279377Simp cell-index = <1>; 166279377Simp interrupts = <92>; 167279377Simp clocks = <&coreclk 0>; 168279377Simp status = "disabled"; 169279377Simp }; 170279377Simp 171279377Simp i2c0: i2c@11000 { 172279377Simp compatible = "marvell,mv64xxx-i2c"; 173279377Simp #address-cells = <1>; 174279377Simp #size-cells = <0>; 175279377Simp interrupts = <31>; 176279377Simp timeout-ms = <1000>; 177279377Simp clocks = <&coreclk 0>; 178279377Simp status = "disabled"; 179279377Simp }; 180279377Simp 181279377Simp i2c1: i2c@11100 { 182279377Simp compatible = "marvell,mv64xxx-i2c"; 183279377Simp #address-cells = <1>; 184279377Simp #size-cells = <0>; 185279377Simp interrupts = <32>; 186279377Simp timeout-ms = <1000>; 187279377Simp clocks = <&coreclk 0>; 188279377Simp status = "disabled"; 189279377Simp }; 190279377Simp 191279377Simp uart0: serial@12000 { 192279377Simp compatible = "snps,dw-apb-uart"; 193279377Simp reg = <0x12000 0x100>; 194279377Simp reg-shift = <2>; 195279377Simp interrupts = <41>; 196279377Simp reg-io-width = <1>; 197279377Simp clocks = <&coreclk 0>; 198279377Simp status = "disabled"; 199279377Simp }; 200279377Simp 201279377Simp uart1: serial@12100 { 202279377Simp compatible = "snps,dw-apb-uart"; 203279377Simp reg = <0x12100 0x100>; 204279377Simp reg-shift = <2>; 205279377Simp interrupts = <42>; 206279377Simp reg-io-width = <1>; 207279377Simp clocks = <&coreclk 0>; 208279377Simp status = "disabled"; 209279377Simp }; 210279377Simp 211279377Simp pinctrl: pin-ctrl@18000 { 212279377Simp reg = <0x18000 0x38>; 213279377Simp }; 214279377Simp 215279377Simp coredivclk: corediv-clock@18740 { 216279377Simp compatible = "marvell,armada-370-corediv-clock"; 217279377Simp reg = <0x18740 0xc>; 218279377Simp #clock-cells = <1>; 219279377Simp clocks = <&mainpll>; 220279377Simp clock-output-names = "nand"; 221279377Simp }; 222279377Simp 223279377Simp mbusc: mbus-controller@20000 { 224279377Simp compatible = "marvell,mbus-controller"; 225279377Simp reg = <0x20000 0x100>, <0x20180 0x20>, 226279377Simp <0x20250 0x8>; 227279377Simp }; 228279377Simp 229295436Sandrew mpic: interrupt-controller@20a00 { 230279377Simp compatible = "marvell,mpic"; 231279377Simp #interrupt-cells = <1>; 232279377Simp #size-cells = <1>; 233279377Simp interrupt-controller; 234279377Simp msi-controller; 235279377Simp }; 236279377Simp 237279377Simp coherency-fabric@20200 { 238279377Simp compatible = "marvell,coherency-fabric"; 239279377Simp reg = <0x20200 0xb0>, <0x21010 0x1c>; 240279377Simp }; 241279377Simp 242279377Simp timer@20300 { 243279377Simp reg = <0x20300 0x30>, <0x21040 0x30>; 244279377Simp interrupts = <37>, <38>, <39>, <40>, <5>, <6>; 245279377Simp }; 246279377Simp 247279377Simp watchdog@20300 { 248279377Simp reg = <0x20300 0x34>, <0x20704 0x4>; 249279377Simp }; 250279377Simp 251279377Simp pmsu@22000 { 252279377Simp compatible = "marvell,armada-370-pmsu"; 253279377Simp reg = <0x22000 0x1000>; 254279377Simp }; 255279377Simp 256279377Simp usb@50000 { 257279377Simp compatible = "marvell,orion-ehci"; 258279377Simp reg = <0x50000 0x500>; 259279377Simp interrupts = <45>; 260279377Simp status = "disabled"; 261279377Simp }; 262279377Simp 263279377Simp usb@51000 { 264279377Simp compatible = "marvell,orion-ehci"; 265279377Simp reg = <0x51000 0x500>; 266279377Simp interrupts = <46>; 267279377Simp status = "disabled"; 268279377Simp }; 269279377Simp 270279377Simp eth0: ethernet@70000 { 271279377Simp reg = <0x70000 0x4000>; 272279377Simp interrupts = <8>; 273279377Simp clocks = <&gateclk 4>; 274279377Simp status = "disabled"; 275279377Simp }; 276279377Simp 277279377Simp mdio: mdio { 278279377Simp #address-cells = <1>; 279279377Simp #size-cells = <0>; 280279377Simp compatible = "marvell,orion-mdio"; 281279377Simp reg = <0x72004 0x4>; 282279377Simp clocks = <&gateclk 4>; 283279377Simp }; 284279377Simp 285279377Simp eth1: ethernet@74000 { 286279377Simp reg = <0x74000 0x4000>; 287279377Simp interrupts = <10>; 288279377Simp clocks = <&gateclk 3>; 289279377Simp status = "disabled"; 290279377Simp }; 291279377Simp 292279377Simp sata@a0000 { 293279377Simp compatible = "marvell,armada-370-sata"; 294279377Simp reg = <0xa0000 0x5000>; 295279377Simp interrupts = <55>; 296279377Simp clocks = <&gateclk 15>, <&gateclk 30>; 297279377Simp clock-names = "0", "1"; 298279377Simp status = "disabled"; 299279377Simp }; 300279377Simp 301279377Simp nand@d0000 { 302279377Simp compatible = "marvell,armada370-nand"; 303279377Simp reg = <0xd0000 0x54>; 304279377Simp #address-cells = <1>; 305279377Simp #size-cells = <1>; 306279377Simp interrupts = <113>; 307279377Simp clocks = <&coredivclk 0>; 308279377Simp status = "disabled"; 309279377Simp }; 310279377Simp 311279377Simp mvsdio@d4000 { 312279377Simp compatible = "marvell,orion-sdio"; 313279377Simp reg = <0xd4000 0x200>; 314279377Simp interrupts = <54>; 315279377Simp clocks = <&gateclk 17>; 316279377Simp bus-width = <4>; 317279377Simp cap-sdio-irq; 318279377Simp cap-sd-highspeed; 319279377Simp cap-mmc-highspeed; 320279377Simp status = "disabled"; 321279377Simp }; 322279377Simp }; 323279377Simp }; 324279377Simp 325279377Simp clocks { 326279377Simp /* 2 GHz fixed main PLL */ 327279377Simp mainpll: mainpll { 328279377Simp compatible = "fixed-clock"; 329279377Simp #clock-cells = <0>; 330279377Simp clock-frequency = <2000000000>; 331279377Simp }; 332279377Simp }; 333279377Simp }; 334