arm-realview-pb1176.dts revision 279377
1279377Simp/* 2279377Simp * Copyright 2014 Linaro Ltd 3279377Simp * 4279377Simp * Permission is hereby granted, free of charge, to any person obtaining a copy 5279377Simp * of this software and associated documentation files (the "Software"), to deal 6279377Simp * in the Software without restriction, including without limitation the rights 7279377Simp * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8279377Simp * copies of the Software, and to permit persons to whom the Software is 9279377Simp * furnished to do so, subject to the following conditions: 10279377Simp * 11279377Simp * The above copyright notice and this permission notice shall be included in 12279377Simp * all copies or substantial portions of the Software. 13279377Simp * 14279377Simp * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15279377Simp * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16279377Simp * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17279377Simp * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18279377Simp * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19279377Simp * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20279377Simp * THE SOFTWARE. 21279377Simp */ 22279377Simp 23279377Simp/dts-v1/; 24279377Simp#include <dt-bindings/interrupt-controller/irq.h> 25279377Simp#include <dt-bindings/gpio/gpio.h> 26279377Simp#include "skeleton.dtsi" 27279377Simp 28279377Simp/ { 29279377Simp model = "ARM RealView PB1176"; 30279377Simp compatible = "arm,realview-pb1176"; 31279377Simp 32279377Simp chosen { }; 33279377Simp 34279377Simp aliases { 35279377Simp serial0 = &pb1176_serial0; 36279377Simp serial1 = &pb1176_serial1; 37279377Simp serial2 = &pb1176_serial2; 38279377Simp serial3 = &pb1176_serial3; 39279377Simp serial4 = &fpga_serial; 40279377Simp }; 41279377Simp 42279377Simp memory { 43279377Simp /* 128 MiB memory @ 0x0 */ 44279377Simp reg = <0x00000000 0x08000000>; 45279377Simp }; 46279377Simp 47279377Simp /* The voltage to the MMC card is hardwired at 3.3V */ 48279377Simp vmmc: fixedregulator@0 { 49279377Simp compatible = "regulator-fixed"; 50279377Simp regulator-name = "vmmc"; 51279377Simp regulator-min-microvolt = <3300000>; 52279377Simp regulator-max-microvolt = <3300000>; 53279377Simp regulator-boot-on; 54279377Simp }; 55279377Simp 56279377Simp xtal24mhz: xtal24mhz@24M { 57279377Simp #clock-cells = <0>; 58279377Simp compatible = "fixed-clock"; 59279377Simp clock-frequency = <24000000>; 60279377Simp }; 61279377Simp 62279377Simp timclk: timclk@1M { 63279377Simp #clock-cells = <0>; 64279377Simp compatible = "fixed-factor-clock"; 65279377Simp clock-div = <24>; 66279377Simp clock-mult = <1>; 67279377Simp clocks = <&xtal24mhz>; 68279377Simp }; 69279377Simp 70279377Simp mclk: mclk@24M { 71279377Simp #clock-cells = <0>; 72279377Simp compatible = "fixed-factor-clock"; 73279377Simp clock-div = <1>; 74279377Simp clock-mult = <1>; 75279377Simp clocks = <&xtal24mhz>; 76279377Simp }; 77279377Simp 78279377Simp kmiclk: kmiclk@24M { 79279377Simp #clock-cells = <0>; 80279377Simp compatible = "fixed-factor-clock"; 81279377Simp clock-div = <1>; 82279377Simp clock-mult = <1>; 83279377Simp clocks = <&xtal24mhz>; 84279377Simp }; 85279377Simp 86279377Simp sspclk: sspclk@24M { 87279377Simp #clock-cells = <0>; 88279377Simp compatible = "fixed-factor-clock"; 89279377Simp clock-div = <1>; 90279377Simp clock-mult = <1>; 91279377Simp clocks = <&xtal24mhz>; 92279377Simp }; 93279377Simp 94279377Simp uartclk: uartclk@24M { 95279377Simp #clock-cells = <0>; 96279377Simp compatible = "fixed-factor-clock"; 97279377Simp clock-div = <1>; 98279377Simp clock-mult = <1>; 99279377Simp clocks = <&xtal24mhz>; 100279377Simp }; 101279377Simp 102279377Simp /* FIXME: this actually hangs off the PLL clocks */ 103279377Simp pclk: pclk@0 { 104279377Simp #clock-cells = <0>; 105279377Simp compatible = "fixed-clock"; 106279377Simp clock-frequency = <0>; 107279377Simp }; 108279377Simp 109279377Simp soc { 110279377Simp #address-cells = <1>; 111279377Simp #size-cells = <1>; 112279377Simp compatible = "arm,realview-pb1176-soc", "simple-bus"; 113279377Simp regmap = <&syscon>; 114279377Simp ranges; 115279377Simp 116279377Simp syscon: syscon@10000000 { 117279377Simp compatible = "arm,realview-pb1176-syscon", "syscon"; 118279377Simp reg = <0x10000000 0x1000>; 119279377Simp 120279377Simp led@08.0 { 121279377Simp compatible = "register-bit-led"; 122279377Simp offset = <0x08>; 123279377Simp mask = <0x01>; 124279377Simp label = "versatile:0"; 125279377Simp linux,default-trigger = "heartbeat"; 126279377Simp default-state = "on"; 127279377Simp }; 128279377Simp led@08.1 { 129279377Simp compatible = "register-bit-led"; 130279377Simp offset = <0x08>; 131279377Simp mask = <0x02>; 132279377Simp label = "versatile:1"; 133279377Simp linux,default-trigger = "mmc0"; 134279377Simp default-state = "off"; 135279377Simp }; 136279377Simp led@08.2 { 137279377Simp compatible = "register-bit-led"; 138279377Simp offset = <0x08>; 139279377Simp mask = <0x04>; 140279377Simp label = "versatile:2"; 141279377Simp linux,default-trigger = "cpu0"; 142279377Simp default-state = "off"; 143279377Simp }; 144279377Simp led@08.3 { 145279377Simp compatible = "register-bit-led"; 146279377Simp offset = <0x08>; 147279377Simp mask = <0x08>; 148279377Simp label = "versatile:3"; 149279377Simp default-state = "off"; 150279377Simp }; 151279377Simp led@08.4 { 152279377Simp compatible = "register-bit-led"; 153279377Simp offset = <0x08>; 154279377Simp mask = <0x10>; 155279377Simp label = "versatile:4"; 156279377Simp default-state = "off"; 157279377Simp }; 158279377Simp led@08.5 { 159279377Simp compatible = "register-bit-led"; 160279377Simp offset = <0x08>; 161279377Simp mask = <0x20>; 162279377Simp label = "versatile:5"; 163279377Simp default-state = "off"; 164279377Simp }; 165279377Simp led@08.6 { 166279377Simp compatible = "register-bit-led"; 167279377Simp offset = <0x08>; 168279377Simp mask = <0x40>; 169279377Simp label = "versatile:6"; 170279377Simp default-state = "off"; 171279377Simp }; 172279377Simp led@08.7 { 173279377Simp compatible = "register-bit-led"; 174279377Simp offset = <0x08>; 175279377Simp mask = <0x80>; 176279377Simp label = "versatile:7"; 177279377Simp default-state = "off"; 178279377Simp }; 179279377Simp }; 180279377Simp 181279377Simp /* Primary DevChip GIC synthesized with the CPU */ 182279377Simp intc_dc1176: interrupt-controller@10120000 { 183279377Simp compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; 184279377Simp #interrupt-cells = <3>; 185279377Simp #address-cells = <1>; 186279377Simp interrupt-controller; 187279377Simp reg = <0x10121000 0x1000>, 188279377Simp <0x10120000 0x100>; 189279377Simp }; 190279377Simp 191279377Simp L2: l2-cache { 192279377Simp compatible = "arm,l220-cache"; 193279377Simp reg = <0x10110000 0x1000>; 194279377Simp interrupt-parent = <&intc_dc1176>; 195279377Simp interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; 196279377Simp cache-unified; 197279377Simp cache-level = <2>; 198279377Simp /* 199279377Simp * Override default cache size, sets and 200279377Simp * associativity as these may be erroneously set 201279377Simp * up by boot loader(s). 202279377Simp */ 203279377Simp arm,override-auxreg; 204279377Simp cache-size = <131072>; // 128kB 205279377Simp cache-sets = <512>; 206279377Simp cache-line-size = <32>; 207279377Simp }; 208279377Simp 209279377Simp pmu { 210279377Simp compatible = "arm,arm1176-pmu"; 211279377Simp interrupt-parent = <&intc_dc1176>; 212279377Simp interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 213279377Simp }; 214279377Simp 215279377Simp timer01: timer@10104000 { 216279377Simp compatible = "arm,sp804", "arm,primecell"; 217279377Simp reg = <0x10104000 0x1000>; 218279377Simp interrupt-parent = <&intc_dc1176>; 219279377Simp interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>; 220279377Simp clocks = <&timclk>, <&timclk>, <&pclk>; 221279377Simp clock-names = "timer1", "timer2", "apb_pclk"; 222279377Simp }; 223279377Simp 224279377Simp timer23: timer@10105000 { 225279377Simp compatible = "arm,sp804", "arm,primecell"; 226279377Simp reg = <0x10105000 0x1000>; 227279377Simp interrupt-parent = <&intc_dc1176>; 228279377Simp interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 229279377Simp arm,sp804-has-irq = <1>; 230279377Simp clocks = <&timclk>, <&timclk>, <&pclk>; 231279377Simp clock-names = "timer1", "timer2", "apb_pclk"; 232279377Simp }; 233279377Simp 234279377Simp pb1176_rtc: rtc@10108000 { 235279377Simp compatible = "arm,pl031", "arm,primecell"; 236279377Simp reg = <0x10108000 0x1000>; 237279377Simp interrupt-parent = <&intc_dc1176>; 238279377Simp interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 239279377Simp clocks = <&pclk>; 240279377Simp clock-names = "apb_pclk"; 241279377Simp }; 242279377Simp 243279377Simp pb1176_gpio0: gpio@1010a000 { 244279377Simp compatible = "arm,pl061", "arm,primecell"; 245279377Simp reg = <0x1010a000 0x1000>; 246279377Simp gpio-controller; 247279377Simp interrupt-parent = <&intc_dc1176>; 248279377Simp interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; 249279377Simp #gpio-cells = <2>; 250279377Simp interrupt-controller; 251279377Simp #interrupt-cells = <2>; 252279377Simp clocks = <&pclk>; 253279377Simp clock-names = "apb_pclk"; 254279377Simp }; 255279377Simp 256279377Simp pb1176_ssp: ssp@1010b000 { 257279377Simp compatible = "arm,pl022", "arm,primecell"; 258279377Simp reg = <0x1010b000 0x1000>; 259279377Simp interrupt-parent = <&intc_dc1176>; 260279377Simp interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; 261279377Simp clocks = <&sspclk>, <&pclk>; 262279377Simp clock-names = "SSPCLK", "apb_pclk"; 263279377Simp }; 264279377Simp 265279377Simp pb1176_serial0: serial@1010c000 { 266279377Simp compatible = "arm,pl011", "arm,primecell"; 267279377Simp reg = <0x1010c000 0x1000>; 268279377Simp interrupt-parent = <&intc_dc1176>; 269279377Simp interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 270279377Simp clocks = <&uartclk>, <&pclk>; 271279377Simp clock-names = "uartclk", "apb_pclk"; 272279377Simp }; 273279377Simp 274279377Simp pb1176_serial1: serial@1010d000 { 275279377Simp compatible = "arm,pl011", "arm,primecell"; 276279377Simp reg = <0x1010d000 0x1000>; 277279377Simp interrupt-parent = <&intc_dc1176>; 278279377Simp interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; 279279377Simp clocks = <&uartclk>, <&pclk>; 280279377Simp clock-names = "uartclk", "apb_pclk"; 281279377Simp }; 282279377Simp 283279377Simp pb1176_serial2: serial@1010e000 { 284279377Simp compatible = "arm,pl011", "arm,primecell"; 285279377Simp reg = <0x1010e000 0x1000>; 286279377Simp interrupt-parent = <&intc_dc1176>; 287279377Simp interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; 288279377Simp clocks = <&uartclk>, <&pclk>; 289279377Simp clock-names = "uartclk", "apb_pclk"; 290279377Simp }; 291279377Simp 292279377Simp pb1176_serial3: serial@1010f000 { 293279377Simp compatible = "arm,pl011", "arm,primecell"; 294279377Simp reg = <0x1010f000 0x1000>; 295279377Simp interrupt-parent = <&intc_dc1176>; 296279377Simp interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 297279377Simp clocks = <&uartclk>, <&pclk>; 298279377Simp clock-names = "uartclk", "apb_pclk"; 299279377Simp }; 300279377Simp }; 301279377Simp 302279377Simp /* These peripherals are inside the FPGA rather than the DevChip */ 303279377Simp fpga { 304279377Simp #address-cells = <1>; 305279377Simp #size-cells = <1>; 306279377Simp compatible = "simple-bus"; 307279377Simp ranges; 308279377Simp 309279377Simp fpga_mci: mmcsd@10005000 { 310279377Simp compatible = "arm,pl18x", "arm,primecell"; 311279377Simp reg = <0x10005000 0x1000>; 312279377Simp interrupt-parent = <&intc_fpga1176>; 313279377Simp interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>, 314279377Simp <0 2 IRQ_TYPE_LEVEL_HIGH>; 315279377Simp /* Due to frequent FIFO overruns, use just 500 kHz */ 316279377Simp max-frequency = <500000>; 317279377Simp bus-width = <4>; 318279377Simp cap-sd-highspeed; 319279377Simp cap-mmc-highspeed; 320279377Simp clocks = <&mclk>, <&pclk>; 321279377Simp clock-names = "mclk", "apb_pclk"; 322279377Simp vmmc-supply = <&vmmc>; 323279377Simp cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>; 324279377Simp wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>; 325279377Simp }; 326279377Simp 327279377Simp fpga_kmi0: kmi@10006000 { 328279377Simp compatible = "arm,pl050", "arm,primecell"; 329279377Simp reg = <0x10006000 0x1000>; 330279377Simp interrupt-parent = <&intc_fpga1176>; 331279377Simp interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; 332279377Simp clocks = <&kmiclk>, <&pclk>; 333279377Simp clock-names = "KMIREFCLK", "apb_pclk"; 334279377Simp }; 335279377Simp 336279377Simp fpga_kmi1: kmi@10007000 { 337279377Simp compatible = "arm,pl050", "arm,primecell"; 338279377Simp reg = <0x10007000 0x1000>; 339279377Simp interrupt-parent = <&intc_fpga1176>; 340279377Simp interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 341279377Simp clocks = <&kmiclk>, <&pclk>; 342279377Simp clock-names = "KMIREFCLK", "apb_pclk"; 343279377Simp }; 344279377Simp 345279377Simp fpga_charlcd: charlcd@10008000 { 346279377Simp compatible = "arm,versatile-lcd"; 347279377Simp reg = <0x10008000 0x1000>; 348279377Simp interrupt-parent = <&intc_fpga1176>; 349279377Simp interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 350279377Simp clocks = <&pclk>; 351279377Simp clock-names = "apb_pclk"; 352279377Simp }; 353279377Simp 354279377Simp fpga_serial: serial@10009000 { 355279377Simp compatible = "arm,pl011", "arm,primecell"; 356279377Simp reg = <0x10009000 0x1000>; 357279377Simp interrupt-parent = <&intc_fpga1176>; 358279377Simp interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 359279377Simp clocks = <&uartclk>, <&pclk>; 360279377Simp clock-names = "uartclk", "apb_pclk"; 361279377Simp }; 362279377Simp 363279377Simp /* This GIC on the board is cascaded off the DevChip GIC */ 364279377Simp intc_fpga1176: interrupt-controller@10040000 { 365279377Simp compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; 366279377Simp #interrupt-cells = <3>; 367279377Simp #address-cells = <1>; 368279377Simp interrupt-controller; 369279377Simp reg = <0x10041000 0x1000>, 370279377Simp <0x10040000 0x100>; 371279377Simp interrupt-parent = <&intc_dc1176>; 372279377Simp interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 373279377Simp }; 374279377Simp 375279377Simp fpga_gpio0: gpio@10014000 { 376279377Simp compatible = "arm,pl061", "arm,primecell"; 377279377Simp reg = <0x10014000 0x1000>; 378279377Simp gpio-controller; 379279377Simp interrupt-parent = <&intc_fpga1176>; 380279377Simp interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 381279377Simp #gpio-cells = <2>; 382279377Simp interrupt-controller; 383279377Simp #interrupt-cells = <2>; 384279377Simp clocks = <&pclk>; 385279377Simp clock-names = "apb_pclk"; 386279377Simp }; 387279377Simp 388279377Simp fpga_gpio1: gpio@10015000 { 389279377Simp compatible = "arm,pl061", "arm,primecell"; 390279377Simp reg = <0x10015000 0x1000>; 391279377Simp gpio-controller; 392279377Simp interrupt-parent = <&intc_fpga1176>; 393279377Simp interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 394279377Simp #gpio-cells = <2>; 395279377Simp interrupt-controller; 396279377Simp #interrupt-cells = <2>; 397279377Simp clocks = <&pclk>; 398279377Simp clock-names = "apb_pclk"; 399279377Simp }; 400279377Simp 401279377Simp fpga_rtc: rtc@10017000 { 402279377Simp compatible = "arm,pl031", "arm,primecell"; 403279377Simp reg = <0x10017000 0x1000>; 404279377Simp interrupt-parent = <&intc_fpga1176>; 405279377Simp interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 406279377Simp clocks = <&pclk>; 407279377Simp clock-names = "apb_pclk"; 408279377Simp }; 409279377Simp 410279377Simp 411279377Simp }; 412279377Simp}; 413